Scan Chain and Power Delivery Network Synthesis for Pre-Bond Test of 3D ICs

Transcription

1 Die 1 Die 0 Scan Chain and Power Delivery Network Synthesis for Pre-Bond Test of 3D ICs Shreepad Panth and Sung Kyu Lim School of Electrical and Computer Engineering Georgia Institute of Technology {spanth, limsk}@ece.gatech.edu Abstract Pre-bond testing of 3D ICs improves yield by preventing bad dies and/or wafers from being used in the final 3D stack. However, pre-bond testing is challenging because it requires special scan chains and power delivery mechanism. Any 3D scan chains that traverse multiple dies will be fragmentized in each individual die during pre-bond testing. In this paper we study the scan chain and power delivery network synthesis for pre-bond testing of 3D ICs. The testing of individual dies is facilitated by the addition of dedicated probe pads for power delivery and scan IO as a form of design-for-testing. We investigate the impact of scan-chain Through-Silicon-Vias (TSVs) on power consumption and voltage drop. We also study the requirements of power probe pads for power delivery during pre-bond structural test. Index Terms 3D ICs, pre-bond test, structural test, probe test, power delivery network Fig. 1. Gates C4 Bumps P/G TSV Signal TSV TSV landing pad Probe Pad The Structure of a 3D Integrated Circuit I. INTRODUCTION Three Dimensional (3D) Integrated Circuits have emerged as a solution to the interconnect scaling problem. A Through- Silicon Via (TSV) is used to connect multiple dies in the vertical dimension, and this extra dimension offers us the possibility of reducing the length of the longest wires, the total wirelength, increasing the system clock frequency, and reducing power consumption. However, these through silicon vias have non-negligible area, which affects the placement results of other surrounding logic or memory [1]. Thus, they cannot be treated simply as an interconnect, but their impact on the layout has to be considered as well. Testing of 3D ICs remains one of the major EDA challenges facing their widespread adoption [2]. Testing of the entire 3D stack is known as post-bond test, and is not overly challenging as we have a completely functional circuit, as well as solder bumps for providing test access. However, pre-bond test, which is the testing for each die prior to stacking, is challenging because each die may not have complete logic, and there are no solder bumps to connect to. A solution to the first problem is performing structural test, using scan chains, where the high-level functionality of the circuit is irrelevant, and a solution to the second problem is the addition of probe pads so that probe needles can touchdown during wafer test. We address the following issues related to the pre-bond testing for 3D ICs. First, we study the power delivery re- This material is based upon work supported by the National Science Foundation under Grant No. CCF , the FCRP Interconnect Focus Center (IFC), and Intel Corporation. quirements and methods for the structural post-bond testing of a 3D Stacked IC. Second, we investigate the impact of scan-chain TSV count on the scan chain length as well as the system parameters such as total circuit wirelength. Third, we investigate the impact of probe pad usage on the power delivery during pre-bond testing. II. PRELIMINARIES AND MOTIVATION A. Prior Work in 3D IC Testing Although the testing of 3D IC s is an important challenge facing their adoption, only limited work has been done in the field. Wu et al [3] compare several scan chain schemes, and provide a genetic algorithm and ILP based algorithms for routing them for post bond test. Zhao et al [4] provided a scheme for clock tree synthesis to facilitate pre-bond test. At the architecture level, Lewis and Lee [5] proposed a scan island based methodology to test incomplete circuits during pre-bond test. The 3D test flow, TSV defects, and possible changes to the test architecture were presented in [6]. The authors of [7], [8] provide test architecture design for 3D SoCs. B. Motivation Although some work has been done in the area of prebond test, none have yet considered the need for power supply during pre-bond test. The structure of a typical 3D IC is shown in Figure 1. Usually, only one die has C4 bumps, and all other dies receive power through P/G TSVs. During pre-bond test of these dies, no wire bond pads for power or ground exist, and probe pads need to be added to facilitate their testing as

2 PAD TSV (a) probe pads and TSVs (b) P/G TSV with P/G wires (c) signal TSV and P/G wires Fig. 2. Cadence Encounter image shots. (a) probe pads and TSVs, (b) P/G TSVs and P/G wire detours, (c) signal TSVs and P/G wires. P/G wires can be routed over signal TSVs. Fig. 3. Damage caused to the probe pad after a single probe touchdown [11] shown. In addition, any scan chains that traverse multiple dies will be broken, which may leave several unbalanced smaller chains which also need to be provided with test access in the form of probe pads. Fine grained touchdown probe needles are unlikely to be available at least for another decade [9], and today s probe pads are limited by available technology [10] to a minimum pitch of 35 40µm for cantilever probing, and 100µm for vertical probing with a minimum pad size of around 25µm. As seen from Figure 1, not only do these probes occupy significant area on the die in which it is placed, any TSVs in the previous die cannot be placed in the same location as the probe pad in order to avoid overlap with its landing pad. Therefore, several layout implications exist to the addition of probe pads, and their locations have to be chosen carefully. III. LOCATION OF PROBE PADS Ideally, we would like to place a probe pad over the landing pad of the TSV to which we wish to connect. This would minimize the area overhead, as well as provide a low resistance connection in the case of power delivery. However, when the probe makes contact with the probe pad, it creates a scrub mark, which significantly affects its planarity, as shown in Figure 3 [11]. It is still unclear how this scrub mark will affect the TSV bonding process, and for the sake of reliability, a certain distance has to be maintained between the probe pad and the TSV landing pad. Figure 2(a) shows such an arrangement, with Figure 2(b) showing a close up shot. P/G Probe Pads: In this case, we wish to have as low a resistance path as possible. Thus, the probe pad has to be placed close to the P/G landing pad and connected to it using a thick strip of the top metal layer. We must be careful to not place it too close, because the P/G TSV landing pad is connected to the power grid through an array of local vias. Such an array present near the probe needle at touchdown is a major source of dielectric cracking [12]. Other Probe Pads: These probe pads include probe pads added for the scan chain, as well as those for a die level wrapper. We add a IEEE 1500 compliant [13] die level wrapper, which gives us test access to the TSVs during pre-bond test. Since the resistance is not paramount for these probe pads, it can be left up to the router to connect the probe pad to the TSV landing pad. The location of these probe pads can be chosen based on ATE constrains, or to minimize the change in the layout of other dies. IV. 3D SCAN CHAINS Constructing a scan chain in a 3D fashion has several advantages over a 2D approach. Wu et al [3] have shown that around a 40% reduction in the scan wirelength can be achieved with 3D scan chains compared with 2D chains for post-bond testing of 3D ICs. This can significantly reduce the test time of the circuit. A 3D scan chain relies on the use of TSVs, and since TSVs occupy silicon area, the total number of scan TSVs that we can use is limited. In this section, we present a greedy heuristic to stitch a 3D scan chain, in order to minimize its wirelength. The constraints are the number of scan TSVs that can be used, and a fixed scan-in and scan-out pin. This is shown in Figure 4. Here, C represents the TSV constraint for each die, and there are k dies. Assuming that we use Face-to-Back (F2B) bonding, TSVs are absent on the last die, and we have k 1 constraints. X represents the set of all scan cells, we have m scan cells. x 0 represents the scan-in pin, and x m+1 represents the scan out pin. Next, the cost function between two cells are initialized. This cost function is given by Equation (1), where z represents

3 1: C {c 1, c 2,..., c k 1 } 2: X {x 0, x 1, x 2,..., x m, x m+1 } 3: i, j initialize Cost(i,j) 4: M = {x 0, x m+1 } 5: u x 0, v x m+1 6: while M X X do 7: u = Min(Cost(u, j)), j / M 8: M = M j 9: u = u 10: i, j update Cost(i,j) 11: v = min(cost(v, k)), j / M 12: M = M k 13: v = v 14: i, j update Cost(i,j) 15: end while Fig. 6. Re-use of existing signal TSVs for scan chain Fig. 4. Greedy algorithm to construct a 3D scan chain s t s t (a) (b) Fig. 7. (a) A 3D scan chain, and (b) multiple fragments connected together Fig. 5. (a) Scan Chain grown from one direction, and (b) Scan Chain grown from two directions all dies between x i and x j, and R z represents the remaining number of TSVs that we are allowed to use for that die. d ij i,j in same die Cost(i, j) = d ij (1) otherwise min R z /C z Next, set M represents the set of marked cells, and the scan-in and scan-out pin are initially marked. Next, we stitch the scan chain from two sides, both from the scan-in and the scan-out pins. We choose the cell with minimum cost in each iteration, and this process continues until all cells are marked. The cost function is dynamically updated, and as more TSVs are used in a particular die, it becomes less attractive to use them, until the cost eventually becomes infinity when all the TSVs are used. It is important to note that when this happens, it may not be possible to stitch all the scan cells without using more TSVs due to the presence of isolated chains. In this case, extra TSVs may be used, which will not exceed two TSVs per die. Each constraint may be subtracted by two to compensate for this effect. Although it is possible to grow the scan chain from one direction only, we grow it from both directions in order to ensure smaller wirelength, as shown in Figure 5. A. Re-Use of Signal TSVs So far, we have assumed that when a scan chain goes from one die to another, we require a dedicated scan TSV. In a scan chain, the output of a flip-flop is connected to the scan input of the next flip flop, as well as to some combinational logic that is of no consequence during the test mode. It might be possible as shown in Figure 6, that a flip flop drives some combinational logic on another die through an existing signal TSV. In this case, we do not need to insert an additional TSV just for the purpose of the scan chain, but we can re-use the existing signal TSV as shown. A careful choice of scan ordering can make use of several existing signal TSVs, thereby reducing the overall scan chain wirelength, without suffering the penalty of inserting a large TSV into the layout. B. Broken Scan Chains Once we have inserted a 3D scan chain into the design, it is used during post-bond test, and its scan-in and scan-out pins are accessed through solder bumps. However, if we wish to perform pre-bond test on each die, we are left with several scan chain fragments, whose number depend on the number of scan TSVs used. It is not feasible to probe all these fragments due to the large size of the required probe pads. Thus, we have to stitch together different fragments as shown in Figure 7 so that the test-pin count is reduced. We use tri-state buffers to stitch together the broken fragments, and they are enabled by a pre-bond test signal. A. Design Flow V. DESIGN AND ANALYSIS FLOW The addition of probe pads complicates the design flow process. This is because the probe pads added in a die not only affects components in its own die, but also affects the placement results of the adjacent die. Initially scan cells are

4 Fig. 8. (a) Scale representation of ICT along y-axis, (b) top die, (c) bottom die inserted into the 2D netlist, either during or after synthesis. Next, the original netlist is partitioned into as many dies as required, and individual netlists are obtained for each die. In the next step, we perform power planning where we decide the configuration and pitch of the number of the power and ground TSVs, as well as the location and number of power and ground probe pads to be used. Once the power plan is completed, we perform an initial placement of each die individually using Cadence Encounter to get the location of scan flip-flops. We then stitch the scan chains together using the greedy algorithm discussed in Section IV. This process introduces additional scan TSVs into the design, which change the placement results. In the next step, we decide the location of the additional probe pads as scan-in and scan out pads for both the scan chain and die-level wrapper, a clock pad, and the scan enable pad. Once the locations of the pads are determined, placement is again carried out to accommodate the new TSVs, as well as to avoid placing any TSVs at the location of probe pads. Finally, the design is routed on a die-by-die basis. B. 3D Power Analysis In order to analyze 3D power, we create a testbench for the two dimensional netlist using pseudo-random test vectors, and then conduct logic simulation using Synopsys VCS to obtain the 2D VCD (value change dump) file. With the information from the die netlists, this 2D VCD file is converted into several VCD files, one for each die. Once we have the VCD file for a given die, the TSV pins on that die are annotated with the TSV capacitance, and power simulations for each die are carried out using Cadence VoltageStorm. C. 3D Voltage Drop Analysis Once the 3D IC design is completed, we perform voltage drop analysis for the entire 3D IC to obtain IR-drop noise values. Our 3D IR-drop analysis tool is based on Cadence VoltageStorm, which is designed for 2D ICs. We take the following steps to handle 3D designs using VoltageStorm: 1) We modify the interconnect technology file (ICT), which contains information on all layers (device layer, dielectric layer, metal layer, vias, and TSVs) and their relative position and resistance values, to model our two die stacked configuration as shown in Figure 8. 2) We create a 3D technology file (TCH), which contains resistive and capacitive information for all and between layers, using Cadence Techgen. 3) We generate a 3D library exchange format (LEF) file so that layers and gates in different dies can be distinguished by the tools. For example, M1 in top-most die and M1 in bottom-most die should be differentiated so that 2D tools distinguish these M1 layers. 4) Power consumption data and layer mapping files, which maps design to appropriate LEF and GDS layers, are modified as well to be used for different dies accordingly. 5) Finally, we create a 3D design exchange format (DEF) file from the final layout of each die to form a single 3D design. After all these preparations are ready, we can run 3D IR-drop analysis on this combined design using Cadence VoltageStorm. Using our IR-drop estimation method, we were able to match both 2D and the two die-stacked 3D IR-drop results from the VoltageStorm within 7% error. Our computed resistance value based on the ICT file for each P/G wire segment overestimated by 6% compared to VoltageStorm. Since this is deterministic error, resistivity value is tuned to match the results. Due to the tools limitation on number of layers it can process, we validated our algorithm up to two die-stacked 3D ICs. VI. EXPERIMENTAL RESULTS The greedy heuristic for scan chain insertion was implemented in C++, and we choose a FFT circuit from [14] for our analysis. Synthesis was carried out in Synopsys Design Compiler using NCSU 45µm technology. The design was placed in two dies, and the number of TSVs is chosen to occupy around 20% of the entire die area. Statistics about the design used are as follows: the number of gates is 400, 213, signal TSV is 2953, Flip-Flops is 75, 723, power TSV is 81, and ground TSV is 64. We use TSVs with 6µm diameter and 10µm landing pad for both P/G and signal. Its height is assumed to be 50µm, and its resistance is 50mΩ. Power and Ground TSVs are inserted at a pitch of 150µm. The probe pad width is assumed to be 40µm, and is assumed to have a minimum pitch of 100µm. The inserted wrapper scan elements occupy 1.96% of the total die area, and have a total stitched wirelength of 75054µm. This corresponds to 0.48% of the baseline wirelength reported in Figure 9(a). A. Impact of Scan Chain TSV on Wirelength In order to study the impact of the number of scan TSV on the wirelength of the design, we construct three different scan chains as shown in Table I. Since we cannot construct a 3D

5 TABLE I SCAN CHAIN CONFIGURATIONS Name No. TSVs #TSV reused Stitch WL (µm) scan scan scan scan chain with no TSVs, we insert 2 TSVs in scan0, which is the minimum number required. Column 3 shows that even without using any specific algorithm to re-use existing signal TSVs, it is possible to re-use around 2% of the TSVs required for the scan chain. The number of scan-chain fragments formed per die is exactly half of the number of TSVs, and Column 4 gives the amount of additional wirelength that is required to stitch all the fragments together into a single scan chain. We observe that with an increase in the number of fragments, the wirelength required to stitch them together also increases. Next, we study the impact of the scan chain TSV count on the scan wirelength and the total wirelength of the 3D design. This is plotted in Figure 9(a). First, we observe that an increase in the number of scan TSVs always helps reduce the scan wirelength. But in the case of signal and total wirelength, adding more scan TSVs helps reduce them initially. But beyond a certain point they start to worsen. The initial improvement is achieved due to the lower scan wirelength reducing the routing blockage. With a further increase in the number of TSVs, either the die area or standard cell density increases. If the die area increases, the average distance between gates increases, increasing the overall wirelength. An increase in the cell density also increases routing congestion. B. Power and IR-drop Analysis during Post-bond Testing We vary the number of scan chain TSVs and study the impact on the power consumption and voltage drop of the 3D die stack during normal operation, and post-bond test. During the normal operation, we generate vectors at the primary inputs of the design. During post-bond structural test, we generate patterns at the scan-in terminal and shift them through the scan chain. Figure 9(b) shows the results of power analysis. As expected, we observe that structural test always has higher power consumption, when compared with the normal mode of operation. During test mode, we observe an initial drop in the power consumption of the circuit when we increase the number of scan TSVs. As we increase this further, no more gains are achieved. This can be attributed to the initial decrease in the scan wirelength, but further gains are offset by the increase in the total wirelength of the 3D FFT design. Next, the same study is carried out for voltage drop and shown in Figure 9(c). We again see worse IR drop during test. When we vary the number of scan TSVs, the same trends are observed here for both normal operation and test mode: an initial increase in voltage drop, followed by a decline as the scan TSV count increases. These results seem counterintuitive as they are exactly the opposite of the power analysis. However, two factors are noteworthy. First, the magnitude of (a) power distribution network (b) IR drop map Fig. 10. (a) GDSII image of our PDN for pre-bond testing, (b) IR drop map under P/G probe pad pitch of 600um using Cadence VoltageStorm. the change in voltage drop is quite small, with the maximum change being 6mV. Secondly, the voltage drop depends not only on the power results, but also on the resistance of the power network. This resistance is affected by the number of TSVs and their location. Inserting more TSVs into the design increases the resistance of the power network due to M1 power strips having to take a detour around them. This accounts for the initial increase in the voltage drop. However, the maximum voltage drop depends on the worst case resistance path to areas of highest power consumption. It is unlikely that all TSV s inserted will fall into this path. It is also possible that the TSVs inserted will avoid this path completely. This accounts for the seemingly unpredictable nature of the voltage drop. C. IR-drop Analysis during Pre-bond Testing In this section, we study the number of probe pads that are required to provide power during pre-bond test. The bottom die has 7 metal layers, and the top die has 6. Metal 7 on the bottom die is used exclusively for TSV landing pads and probe pads. Testing of the top die, the die which has solder bumps is trivial. Power can simply be provided to all the power pins. The voltage drop for Die0 is obtained as follows: scan0 =

6 (a) Impact of Scan TSV count on wirelength (b) Impact of scan TSV count on power (c) 3D IR-drop ( post-bond-testing ) (d) 2D IR-drop ( pre-bond testing ) Fig. 9. Various results 23mV, scan100 = 18mV, scan200 = 18mV. As expected, the voltage drop is well within noise margins, and power delivery for the top die is not an issue. In the case of the bottom die, however, probe pads have to be added at select locations to provide power. Additionally, it is not possible to smoothly control their pitch as they have to align with the power and ground TSVs. We add probe pads at two, three and four times the P/G TSV pitch and show the results in Figure 9(d). We observe that with an increase in pitch, there is a sharp increase in the voltage drop of die1. Thus, the P/G probe pads need to be inserted carefully to control voltage drop. Assuming a 150mV constraint, we see that a pitch of 600um violates the noise constraint. VII. CONCLUSION In this work, we explored the impact of scan chain TSVs on wirelength, power and voltage drop of 3D ICs. We also explored the design options and requirements for power delivery during pre-bond testing. Experimental results show that increasing the number of scan TSVs upto a certain point helps reduce both wirelength and power consumption. We also studied the impact of P/G probe pads used for pre-bond testing on voltage drop. REFERENCES [1] D. Kim, K. Athikulwongse, and S. Lim, A study of Through-Silicon- Via Impact on 3D Stacked ICs, in Proc. IEEE Int. Conf. on Computer- Aided Design, [2] T.Vucurevich. The Long Road to 3D Integration: Are we there yet? Key note speech at the 3D Architecture Conference, [3] X. Wu, P. Falkenstern, K. Chakrabarty, and Y. Xie, Scan Chain Design and Optimization for Three-Dimensional Integrated Circuits, ACM Journal on Emerging Technologies in Computing Systems, [4] X. Zhao, D. Lewis, H.-H. S. Lee, and S. K. Lim, Pre-bond Testable Low-Power Clock Tree Design for 3D Stacked ICs, in IEEE International Conference on Computer-Aided Design, [5] D. Lewis and H. H. S. Lee, A Scan Island Based Design Enabling Pre- Bond Testability in Die Stacked Microprocessors, in IEEE International Test Conference, [6] E. J. Marinissen and Y. Zorian, Testing 3D Chips Containing Through Silicon Vias, in IEEE International Test Conference, [7] L. Jiang, L. Huang, and Q. Xu, Test Architecture Design and Optimization of Three-Dimensional SoCs, in Design, Automation and Test in Europe, [8] L. Jiang, Q. Xu, K. Chakrabarty, and T. Mak, Layout-Driven test- Architecture design and Optimization for 3D SoCs under Pre-Bond Test- Pin-Count Constraint, in IEEE International Conference on Computer Aided Design, [9] International Technology Roadmap for Semiconductors 2009, [10] W. R. Mann, F. L. Taber, P. W. Seitzer, and J. J. Broz, The leading edge of Production Wafer Probe Test Technology, in IEEE International Test Conference. [11] K. Karklin, J. Broz, and B. Mann, Bond Pad Damage Tutorial, in IEEE Semiconductor Wafer Test Workshop, [12] T. Hauck, I. Schmadlak, C. Argento, and W. H. Muller, Damage Risk Assessment of Under-Pad structures in Vertical Wafer Probe Technology, in IEEE European Microelectronics and Packaging Conference, [13] E. Marinissen, J. Verbree, and M. Konijnenburg, A structured and scalable test access architecture for TSV-based 3D stacked ICs, in IEEE VLSI Test Symposium, [14]