3D IC Test through Power Line Methodology. Alberto Pagani

Transcription

1 3D IC Test through Power Line Methodology Alberto Pagani

2 Outline 2 Power Line Communication (PLC) approach 2D Test architecture through PLC Advantages Methodology Feasibility Study Rx test chip for digital signal on power line DUT testing reliability 3D Test architecture through PLC Methodology Test procedure Advantages Conclusions

3 Power Line Communication (PLC) approach 3D Options 3 Wafers 3D Chip 3D Integrated Circuits are well known 3D systems are numerous A house is a good example of 3D architecture

4 Power Line Communication (PLC) approach 4 Mixer + amplifier roof flat Power supply flat In TV antenna systems, RF signals and DC power supplies are superposed on the same coaxial cable 1 st floor Ground floor flat flat Our proposal is to apply the same concept to 3D IC wafer testing

5 2D Test architecture through PLC Advantages 5 Main advantages of 2D test architecture : Significant reduction of probe card complexity due to low number of probes (best case only two probes) DUT DUT Significant reduction of pad damage Pad area reduction Possibility to Analyze customer returns Test IC in the final application Facilitates in system programming

6 DUT Probe Card 2D Test architecture through PLC Methodology 6 GND V cc L 1 TxRx Through PLC, we use the same electrical line to supply power (DC) and exchange test signals (AC signal). Probe-pad Interface 2 I 1 I A I 2 I 1 B I 2 Probe-pad Interface 1 C 1 C 2 Radio Frequency (RF) circuits (TxRx) must be introduced between DUT (Device Under Test) and tester. Test signals and power supply are mixed & demixed by filters. L 2 TxRx A dedicated test protocol must be conceived. GND V cc BIST / DFT Power line communication testing system (with ideal filters) All DFT circuits are concentrated in the BIST / DFT block.

7 Feasibility study Rx test chip for digital signal on power line 7 The figure below represents design architecture of the capacitive Rx. Rx works in asynchronous mode, switching when a signal edge transition is detected. PRECHARGE CIRCUIT Vmax Vmax α β IN C C RX COMPARATOR α β C PAD Vmin OUT S RESET A more detailed paper will be submitted for a future IEEE conference. Courtesy of R.Canegallo

8 Feasibility study Rx test chip for digital signal on power line 8 The figure below is a demo board that uses the Capacitive Rx test chip to demonstrate feasibility of low frequency PLC. Rx Test Chip Demo board Filter Courtesy of R.Canegallo

9 Feasibility study Rx test chip for digital signal on power line 9 Square waveform used for modulation Input signal (mix of digital signal + DC power ) Digital signal after separation DC power supply after separation Oscilloscope waveforms tested on PCB Courtesy of R.Canegallo

10 Feasibility study DUT testing reliability 10 A commercial VLSI product and production ATE were used to verify that an additional RF signal superimposed on power line does not affect DUT test results. Sine wave generator Spectrum & Oscilloscope ATE DUT Measurement setup Test bench with a production ATE (Automatic Test Equipment) No filter was added on DUT power supply lines.

11 Feasibility study DUT testing reliability 11-20dBm -8.9dBm Power supply spectrum of the entire test program without additional RF signal (standard test condition) Power supply spectrum of the entire test program with additional RF signal (sine wave is superimposed over DC power supply) The test passed demonstrating that an additional RF signal does not affect DUT test results. It suggests that power supply filters can probably be simplified (avoiding integration of inductors for example), but this must be evaluated on a product by product basis.

12 3D Test architecture through PLC Methodology 12 The new proposed methodology consists of using power TSVs that connect several chips in a 3D stack, thus allowing PLC implementation I/O I/O V cc GND GND V cc ICA Test signal ICA Test signal ICB power TSV signal TSV power TSV ICB power TSV signal TSV power TSV Test signal Test signal Dedicated test TSV Dedicated test TSV Standard test architectures use dedicated TSVs for test signals New proposed test architecture shares power TSVs for power supply and test signals

13 3D Test architecture through PLC Test procedure 13 Test stimuli directed to integrated circuit ICA are transmitted for example, using a first modulation frequency, while test stimuli directed to integrated circuit ICB are transmitted using a second modulation frequency which is different from the first Test responses can use other frequencies Several implementations are possible for example, using CDMA (Code Division Multiple Access) communication scheme, etc V cc GND GND V cc ICA Test signal ICB power TSV signal TSV power TSV Test signal

14 3D Test architecture through PLC Advantages 14 Main advantages of this new proposed test architecture are: Reduction of test pad numbers for 2D pre-bond test and 3D post-bond test Simplification of 3D test standardization Less constraints at routing design level No dedicated TSVs for test signals saving silicon area Fault tolerance for power TSV defects due to multiple power TSVs used for each power supply

15 3D Test architecture through PLC Advantages 15 Architecture is fault tolerant for power TSV defects due to multiple TSVs used for each power supply (in order to supply right current to each 2D DUT), then there is TSV self-redundancy that will allow to test 3D DUT also in case of some defective power TSVs. V cc V cc ICA Test signal TSV fail ICB power TSV signal TSV power TSV Test signal There are also some considerations to be made when introducing a TxRx and testing protocol. A probable compromise can be found between: - TxRx silicon area and area saved by avoiding test TSVs - TxRx complexity and testing requirements In any case, different power supplies can be present in 3D DUT, thus simplifying TxRx.

16 Conclusions 16 We demonstrated the feasibility of 2D Test architecture through power line communication. We proposed new methodology for 2D (pre-bond) and 3D (mid-bond & postbond) testing through power line communication architecture and related advantages to 3D testing. This has been a research project up till now and we need a customer to develop and apply it to a product. Thank you!