Chapter 7 Sequential Circuits
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1 Chapter 7 Sequential Circuits Jin-Fu Li Advanced Reliable Systems (ARES) Lab. epartment of Electrical Engineering National Central University Jungli, Taiwan
2 Outline Latches & Registers Sequencing Timing iagram Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 2
3 Combinational logic Sequencing Output depends on current inputs Sequential logic Output depends on current and previous inputs Requires separating previous, current, future Called state or tokens Ex: FSM, pipeline in CL out CL CL Finite State Machine Pipeline Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 3
4 Sequencing Elements Latch: Level sensitive A.k.a. transparent latch, latch Flip-flop: edge triggered A.k.a. master-slave flip-flop, flip-flop, register Timing iagrams Transparent Opaque Edge-trigger Latch Flop (latch) (flop) Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 4
5 Latches Negative-level sensitive latch 0 1 Positive-level sensitive latch 0 1 Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 5
6 Registers Positive-edge triggered register (singlephase clock) 0 1 S M 0 1 S M master slave Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 6
7 Registers Operations of the positive-edge triggered register =0 =1 Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 7
8 Registers CMOS circuit implementation of the positiveedge triggered register Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 8
9 Single-Phase Latch Positive active-static latch - 1. Low area cost 2. riving capability of must override the feedback inverter - - Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 9
10 Typical Latch Symbolic Layouts V dd V ss Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 10
11 CVSL (ifferential) Style Register The following figure shows latches based on a CVSL structure An N and a P version are shown that are cascaded to form a register - Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 11
12 ouble-edge Triggered Register The following figure shows latches that may be used to clock data on both edges of the clock Latch 1 Latch Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 12
13 ouble-edge Triggered Register ouble-edge triggered register can be implemented by combining Latch 1 & Latch 2 as follows Latch Latch 1 Latch 1 enabled Latch 2 enabled 2=-2=low 1=-1=high Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 13
14 Asynchronously Register Asynchronously resettable register - -reset reset Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 14
15 Asynchronously Register Asynchronously resettable and settable register - -reset set Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 15
16 ynamic Latches & Registers ynamic single clock latches ynamic single clock registers Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 16
17 Clock active high latch ynamic Latches n CLK X n n CLK X H H L X n-1 n-1 0 L 1 n-1 Clock active high latch with buffer X CLK - Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 17
18 Clock active low latch ynamic Latches n CLK X n n CLK X L L H H X n-1 n-1 n-1 Clock active low latch with buffer CLK X - Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 18
19 ynamic Latches Clock active high and low latches without feedback X CLK CLK X The problem of leakage current Assume that the capacitance of node X is 0.002pF and the leakage current I is 1nA Therefore, T=CV/I=0.002pFx5V/1nA=100us That is, the latch needs to be refreshed each 100us. Otherwise, the output will become high Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 19
20 Sequencing Methods Flip-flops T c 2-Phase Latches Pulsed Latches Flip-Flops Flop Combinational Logic Flop 2-Phase Transparent Latches Pulsed Latches 1 2 p Latch t pw p Latch T c /2 Combinational Logic t nonoverlap Latch Combinational Logic Combinational Logic Half-Cycle 1 Half-Cycle 1 t nonoverlap Latch p Latch Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 20
21 Timing iagrams Contamination and Propagation elays t pd Logic Prop. elay A Combinational Logic Y A Y t cd t pd t cd t pcq Logic Cont. elay Latch/Flop Clk- Prop elay t setup t hold t ccq Latch/Flop Clk- Cont. elay Flop t pdq t pcq Latch - Prop elay Latch - Cont. elay t ccq t pcq t setup t hold Latch/Flop Setup Time Latch/Flop Hold Time t setup t hold t t ccq pcq Latch t cdq t pdq Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 21
22 Max-elay: Flip-Flops tpd Tc tsetup tpcq sequencing overhead F1 1 Combinational Logic 2 F2 T c t pcq t setup 1 t pd 2 Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 22
23 Max elay: 2-Phase Latches tpd tpd1 tpd 2 Tc 2tpdq sequencing overhead Combinational 2 2 Combinational 3 Logic 1 Logic 2 L1 L2 L T c 1 t pdq1 1 t pd1 2 t pdq2 2 t pd2 3 Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 23
24 Max elay: Pulsed Latches tpd Tc max tpdq, tpcq tsetup tpw sequencing overhead p p 1 L1 1 Combinational Logic 2 L2 2 T c 1 t pdq (a) t pw > t setup 1 t pd 2 p (b) t pw < t setup 1 2 t pcq T c t pw tpd tsetup Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 24
25 cd Min-elay: Flip-Flops t t t hold ccq F1 1 CL 2 F2 1 t ccq t cd 2 t hold Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 25
26 Min-elay: 2-Phase Latches t t t t t cd1, cd 2 hold ccq nonoverlap Hold time reduced by nonoverlap 1 L1 1 CL Paradox: hold applies twice each cycle, vs. only once for flops. 2 2 L2 But a flop is made of two latches! 1 t nonoverlap 2 t ccq 1 t cd 2 t hold Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 26
27 Min-elay: Pulsed Latches t t t t cd hold ccq pw Hold time increased by pulse width p L1 1 CL p 2 L2 p t pw t hold 1 t ccq t cd 2 Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 27
28 Time Borrowing In a flop-based system: ata launches on one rising edge Must setup before next rising edge If it arrives late, system fails If it arrives early, time is wasted Flops have hard edges In a latch-based system ata can pass through latch while transparent Long cycle of logic can borrow time into next As long as each loop completes in one cycle Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 28
29 Time Borrowing Example (a) Latch Combinational Logic Latch Combinational Logic Latch Borrowing time across half-cycle boundary Borrowing time across pipeline stage boundary 1 2 (b) Latch Combinational Logic Latch Combinational Logic Loops may borrow time internally but must complete within the cycle Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 29
30 How Much Borrowing? Phase Latches T borrow c setup nonoverlap t t t L1 1 Combinational Logic 1 2 L2 2 Pulsed Latches 2 T c t nonoverlap t t t borrow pw setup T c /2 Nominal Half-Cycle 1 elay t borrow t setup 2 Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 30
31 Clock Skew We have assumed zero clock skew Clocks really have uncertainty in arrival time ecreases maximum propagation delay Increases minimum contamination delay ecreases time borrowing Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 31
32 Skew: Flip-Flops t T t t t pd c pcq setup skew sequencing overhead F1 1 Combinational Logic T c 2 F2 t t t t cd hold ccq skew t pcq t skew 1 t pdq t setup 2 F1 1 CL 2 F2 t skew t hold 1 t ccq 2 t cd Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 32
33 Skew: Latches 2-Phase Latches tpd Tc 2tpdq sequencing overhead Combinational 2 2 Combinational 3 Logic 1 Logic 2 L1 L2 L3 3 t, t t t t t cd1 cd 2 hold ccq nonoverlap skew T t t t t 2 c borrow setup nonoverlap skew Pulsed Latches t T max t, t t t t pd c pdq pcq setup pw skew sequencing overhead t t t t t cd hold pw ccq t t t t skew borrow pw setup skew 1 2 Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 33
34 Two-Phase Clocking If setup times are violated, reduce clock speed If hold times are violated, chip fails at any speed In this class, working chips are most important No tools to analyze clock skew An easy way to guarantee hold times is to use 2-phase latches with big nonoverlap times Call these clocks 1, 2 (ph1, ph2) Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 34
35 Safe Flip-Flop In class, use flip-flop with nonoverlapping clocks Very slow nonoverlap adds to setup time But no hold times In industry, use a better timing analyzer Add buffers to slow signals if hold time is at risk X Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 35
36 Clock istribution In a large CMOS chip, clock distribution is a serious problem For example, V dd =5V C reg =2000pF (20K register 0.1pF) T =10ns T rise/fall =1ns I peak =C(dv/dt)=(2000p)x(5/1n)=10A P d =C(V dd ) 2 f=2000px25x100=5w Methods for reducing the values of I peak and P d Reduce C Interleaving the rise/fall time Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 36
37 Clock istribution Clocking is a floorplanning problem because clock delay varies with position on the chip Ways to improve clock distribution Physical design Make clock delays more even At least more predictable Circuit design Minimizing delays using several stages of drivers Two most common types of physical clocking networks H-tree clock distribution Balanced-tree clock distribution Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 37
38 H-Tree Clock istribution clock Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 38
39 H-Tree Clock istribution Source: Prof. Irwin Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 39
40 Balanced-Tree Clock istribution clock Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 40
41 Reduce Clocking Power Techniques used to reduce the high dynamic power dissipation Use a low capacitance clock routing line such as metal3. This layer of metal can be, for example, dedicated to clock distribution only Using low-swing drivers at the top level of the tree or in intermediate levels Vdd C1 C2 p - p CA V out Gnd n C3 - n C4 CB Clock Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 41
42 Power & Ground istribution Source: Prof. Irwin Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 42
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