DIGITAL ELECTRONICS MCQs


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1 DIGITAL ELECTRONICS MCQs 1. A 8bit serial in / parallel out shift register contains the value 8, clock signal(s) will be required to shift the value completely out of the register. A. 1 B. 2 C. 4 D In a sequential circuit the next state is determined by and. A. State variable, current state B. Current state, flipflop output C. Current state and external input D. Input and clock signal applied 3. The divideby60 counter in digital clock is implemented by using two cascading counters: A. Mod6, Mod10 B. Mod50, Mod10 C. Mod10, Mod50 D. Mod50, Mod6 4. The minimum time for which the input signal has to be maintained at the input of flipflop is called of the flipflop. A. Setup time B. Hold time C. Pulse Interval time D. Pulse Stability time (PST) 5. is said to occur when multiple internal variables change due to change in one input variable. A. Clock Skew B. Race condition C. Hold delay D. Hold and Wait 6. The input overrides the input. A. Asynchronous, synchronous B. Synchronous, asynchronous C. Preset input (PRE), Clear input (CLR) D. Clear input (CLR), Preset input (PRE) 7. A decade counter is. A. Mod3 counter B. Mod5 counter C. Mod8 counter D. Mod10 counter 8. In asynchronous transmission when the transmission line is idle,. A. It is set to logic low B. It is set to logic high C. Remains in previous state D. State of transmission line is not used to start transmission 9. A Nibble consists of bits. A. 2 B. 4 C. 8 D The voltage gain of the Inverting Amplifier is given by the relation. A. Vout / Vin =  Rf / Ri B. Vout / Rf =  Vin / Ri C. Rf / Vin =  Ri / Vout D. Rf / Vin = Ri / Vout
2 11. LUT is acronym for. A. Look Up Table B. Local User Terminal C. Least Upper Time Period D. None of given options 12. The three fundamental gates are. A. AND, NAND, XOR B. OR, AND, NAND C. NOT, NOR, XOR D. NOT, OR, AND 13. The total amount of memory that is supported by any digital system depends upon. A. The organization of memory B. The structure of memory C. The size of decoding unit D. The size of the address bus of the microprocessor 14. Stack is an acronym for. A FIFO memory B. LIFO memory C. Flash Memory D. Bust Flash Memory 15. is one of the examples of synchronous inputs. A. JK input B. EN input C. Preset input (PRE) D. Clear Input (CLR) 16. In a state diagram, the transition from a current state to the next state is determined by: A. Current state and the inputs B. Current state and outputs C. Previous state and inputs D. Previous state and outputs 17. is used to simplify the circuit that determines the next state. A. State diagram B. Next state table C. State reduction D. State assignment 18. A 8bit serial in / parallel out shift register contains the value 8, clock signal(s) will be required to shift the value completely out of the register. A. 1 B. 2 C. 4 D The operation of JK flipflop is similar to that of the SR flipflop except that the JK flipflop. A. Doesn t have an invalid state B. Sets to clear when both J = 0 and K = 0 C. It does not show transition on change in pulse D. It does not accept asynchronous inputs 20. A positive edgetriggered flipflop changes its state when.
3 A. Lowtohigh transition of clock B. Hightolow transition of clock C. Enable input (EN) is set D. Preset input (PRE) is set 21. In a sequential circuit the next state is determined by and. A. State variable, current state B. Current state, flipflop output C. Current state and external input D. Input and clock signal applied 22. The divideby60 counter in digital clock is implemented by using two cascading counters: A. Mod6, Mod10 B. Mod50, Mod10 C. Mod10, Mod50 D. Mod50, Mod Flip flops are also called. A. Bistable dualvibrators B. Bistable transformer C. Bistable multivibrators D. Bistable singlevibrators 24. The minimum time for which the input signal has to be maintained at the input of flipflop is called of the flipflop. A. Setup time B. Hold time C. Pulse Interval time D. Pulse Stability time (PST) 25. A decade counter is. A. Mod3 counter B. Mod5 counter C. Mod8 counter D. Mod10 counter 26. DRAM stands for. A. Dynamic RAM B. Data RAM C. Demoduler RAM D. None of above 27. The expression F=A+B+C describes the operation of three bits Gate. A. OR B. AND C. NOT D. NAND 28. The decimal 17 in BCD will be represented as. A B C D The basic building block for a logical circuit is. A. A FlipFlop B. A Logical Gate C. An Adder D. None of above 30. The output of the expression F=A.B.C will be Logic when A=1, B=0, C=1. A. Undefined B. One C. Zero D. No Output as input is invalid
4 31. is invalid number of cells in a single group formed by the adjacent cells in K map. A. 2 B. 8 C. 12 D is one of the examples of asynchronous inputs. A. JK input B. SR input C. D input D. Clear Input (CLR) bit Johnson counter sequences through states. A. 7 B. 10 C. 32 D FIFO is an acronym for. A. First In, First Out B. Fly in, Fly Out C. Fast in, Fast Out D. None of given options 35. of a D/A converter is determined by comparing the actual output of a D/A converter with the expected output. A. Resolution B. Accuracy C. Quantization D. Missing Code 36. The sequence of states that are implemented by a nbit Johnson counter is: A. n+2 (n plus 2) B. 2n (n multiplied by 2) C. 2n (2 raise to power n) D. n2 (n raise to power 2) 37. "A + B = B + A" is. A. Demorgan s Law B. Distributive Law C. Commutative Law D. Associative Law 38. Demultiplexer is also called: A. Data selector B. Data router C. Data distributor D. Data encoder 39. The operation of JK flipflop is similar to that of the SR flipflop except that the JK flipflop. A. Doesn t have an invalid state B. Sets to clear when both J = 0 and K = 0 C. It does not show transition on change in pulse D. It does not accept asynchronous inputs 40. A flipflop is connected to +5 volts and it draws 5 ma of current during its operation, the power dissipation of the flipflop is: A. 10 mw B. 25 mw C. 64 mw D mw
5 41. counters as the name indicates are not triggered simultaneously. A. Asynchronous B. Synchronous C. PositiveEdge triggered D. NegativeEdge triggered 42. A synchronous decade counter will have flipflops. A. 3 B. 4 C. 7 D A frequency counter. A. Counts pulse width B. Counts no. of clock pulses in 1 second C. Counts high and low range of given clock pulse D. None of given options 44. The storage cell in SRAM is: A. a flip flop B. a capacitor C. a fuse D. a magnetic domain 45. For a positive edgetriggered JK flipflop with both J and K HIGH, the outputs will if the clock goes HIGH. A. toggle B. Set C. reset D. not change 46. If an SR latch has a 1 on the S input and a 0 on the R input and then the S input goes to 0, the latch will be: A. set B. reset C. invalid D. Clear 47. The power dissipation (PD) of a logic gate is the product of the: A. dc supply voltage and the peak current B. dc supply voltage and the average supply current C. ac supply voltage and the peak current D.ac supply voltage and the average supply current 48. The 3variable Karnaugh Map (KMap) has cells for min or max terms. A. 4 B. 8 C. 12 D Sum term (Max term) is implemented using gates. A. OR B. AND C. NOT D. ORAND 50. The output of an AND gate is one when. A. All of the inputs are one B. Any of the input is one C. Any of the input is zero D. All the inputs are zero
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