ICM7228AIPI Sequential Common Anode -40 to Ld PDIP E28.6. ICM7228BIPI Sequential Common Cathode -40 to Ld PDIP E28.6

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1 ICM22 May 22 -Digit, Microprocessor- Compatible, LED Display Decoder Driver Features Improved 2nd Source to Maxim ICM2 Fast Write Access Time of 2ns Multiple Microprocessor Compatible Versions Hexadecimal, Code B and o Decode Modes Individual Segment Control with o Decode Feature Digit and Segment Drivers On-Chip on-overlapping Digits Drive Common Anode and Common Cathode LED Versions Low Power CMOS Architecture Single V Supply Applications Instrumentation Test Equipment Hand Held Instruments Bargraph Displays umeric and on-umeric Panel Displays High and Low Temperature Environments where LCD Display Integrity is Compromised Description The Intersil ICM22 display driver interfaces microprocessors to an -digit, -segment, numeric LED display. Included on chip are two types of -segment decoder, multiplex scan circuitry, LED display segment drivers, LED display digit drivers and an -byte static memory as display RAM. Data can be written to the ICM22A and ICM22B s display RAM in sequential -digit update or in single-digit update format. Data is written to the ICM22C and ICM22D display RAM in parallel random access format. The ICM22A and ICM22C drive common anode displays. The ICM22B and ICM22D drive common cathode displays. All versions can display the RAM data as either Hexadecimal or Code B format. The ICM22A and ICM22B incorporate a o Decode mode allowing each bit of each digit's RAM word to drive individual display segments resulting in independent control of all display segments. As a result, bargraph and other irregular display segments and formats can be driven directly by this chip. The Intersil ICM22 is an alternative to both the Maxim ICM2 and the Intersil ICM2 display drivers. otice that the ICM22A/B has an additional single digit access mode. This could make the Intersil ICM2A/B software incompatible with ICM22A/B operation. Ordering Information PART UMBER DATA ETRY PROTOCOL DISPLAY TYPE TEMP. RAGE ( o C) PACKAGE PKG. O. ICM22AIPI Sequential Common Anode - to 2 Ld PDIP E2.6 ICM22BIPI Sequential Common Cathode - to 2 Ld PDIP E2.6 ICM22CIPI Random Common Anode - to 2 Ld PDIP E2.6 ICM22DIPI Random Common Cathode - to 2 Ld PDIP E2.6 ICM22AIJI Sequential Common Anode - to 2 Ld CERDIP F2.6 ICM22CIJI Random Common Anode - to 2 Ld CERDIP F2.6 ICM22AIBI Sequential Common Anode - to 2 Ld SOIC M2. ICM22BIBI Sequential Common Cathode - to 2 Ld SOlC M2. ICM22CIBI Random Common Anode - to 2 Ld SOlC M2. CAUTIO: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. --ITERSIL or 2-2- Intersil (and design) is a trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 22. All Rights Reserved F6.2

2 ICM22 Pinouts ICM22A (CERDIP, PDIP, SOIC) COMMO AODE TOP VIEW ICM22B (CERDIP, PDIP, SOIC) COMMO CATHODE TOP VIEW SEG c 2 DIGIT 2 SEG e 2 2 SEG a DIGIT DIGIT SEG b 26 SEG g DIGIT 26 DIGIT DP 2 SEG d DIGIT 2 DIGIT 2 ID6 (HEXA/CODE B) 2 SEG f ID6 (HEXA/CODE B) 2 DIGIT ID (DECODE) 6 2 DIGIT ID (DECODE) 6 2 SEG g ID (DATA COMIG) 22 DIGIT 6 ID (DATA COMIG) 22 SEG f 2 DIGIT 2 SEG e MODE 9 2 DIGIT MODE 9 2 SEG c ID (SHUTDOW) 9 ID (SHUTDOW) 9 ID DIGIT ID SEG d ID 2 DIGIT ID 2 SEG b ID2 6 DIGIT 2 ID2 6 SEG a ID DIGIT ID DP ICM22C (CERDIP, PDIP, SOIC) COMMO AODE TOP VIEW ICM22D (CERDIP, PDIP, SOIC) COMMO CATHODE TOP VIEW SEG c 2 DIGIT 2 SEG e 2 2 SEG a DIGIT DIGIT SEG b 26 SEG g DIGIT 26 DIGIT DP 2 SEG d DIGIT 2 DIGIT 2 DA (DIGIT ADDRESS ) 2 SEG f DA (DIGIT ADDRESS ) 2 DIGIT DA (DIGIT ADDRESS ) 6 2 DIGIT DA (DIGIT ADDRESS ) 6 2 SEG g ID (IPUT DP) 22 DIGIT 6 ID (IPUT DP) 22 SEG f 2 DIGIT 2 SEG e HEXA/CODE B/SHUTDOW 9 2 DIGIT HEXA/CODE B/SHUTDOW 9 2 SEG c DA2 (DIGIT ADDRESS 2) 9 DA2 (DIGIT ADDRESS 2) 9 ID DIGIT ID SEG d ID 2 DIGIT ID 2 SEG b ID2 6 DIGIT 2 ID2 6 SEG a ID DIGIT ID DP 2

3 ICM22 Functional Block Diagram ICM22A, ICM22B ICM22C, ICM22D ID - ID IPUT DATA ID - ID COTROL IPUTS MODE ID - ID ID DATA IPUT HEXADECIMAL/ CODE B/ SHUTDOW DA - DA2 DIGIT ADDRESS DECODE HEXA/CODE B COTROL LOGIC SHUTDOW THREE LEVEL IPUT LOGIC SHUTDOW -BYTE STATIC RAM ADDRESS COUTER -BYTE STATIC RAM ADDRESS COUTER READ ADDRESS, DIGIT MULTIPLEXER READ ADDRESS MULTIPLEXER HEXADECIMAL/ CODE B DECODER MULTIPLEX OSCILLATOR HEXADECIMAL/ CODE B DECODER MULTIPLEX OSCILLATOR DECODE O-DECODE DECIMAL POIT ITERDIGIT BLAKIG DECIMAL POIT ITERDIGIT BLAKIG SEGMET DRIVERS DIGIT DRIVERS SEGMET DRIVERS DIGIT DRIVERS

4 ICM22 Absolute Maximum Ratings Supply Voltage ( - ) V Digit Output Current ma Segment Output Current ma Input Voltage (ote ) (Any Terminal)..( -.V)<V I <( +.V) Operating Conditions Operating Temperature Range IPI, IJI, IBI Suffix o C to o C Thermal Information Thermal Resistance (Typical, ote 2) θ JA ( o C/W) θ JC ( o C/W) CERDIP Package PDIP Package /A SOIC Package /A Maximum Junction Temperature IPI, IBI Suffix o C IJI Suffix o C Maximum Storage Temperature Range o C to o C Maximum Lead Temperature (Soldering s) o C (SOIC - Lead Tips Only) CAUTIO: Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. OTES:. Due to the SCR structure inherent in the CMOS process used to fabricate these devices, connecting any terminal to a voltage greater than or less then may cause destructive device latchup. For this reason, it is recommended that no inputs row sources operating on a different power supply be applied to the device before its own supply is established, and when using multiple supply systems the supply to the ICM22 should be turned on first. 2. θ JA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief 9 for details. Electrical Specifications = +.V ±%, = V, Unless Otherwise Specified IDUSTRIAL TEMPERATURE RAGE, IPI, IJI, IBI DEVICES T A = 2 o C - o C TO o C PARAMETER TEST CODITIOS MI TYP MAX MI TYP MAX UITS Supply Voltage Range, V SUPPLY Operating V Power Down Mode Quiescent Supply Current, I Q Shutdown, ICM22A, IMC22B - - µa Shutdown, 22C, 22D Operating Supply Current, I DD Common Anode, ICM22A/C µa Segments = O; Outputs = OPE Digit Drive Current, I DIG Common Anode, ICM22A/C Segments = OFF; Outputs = OPE Common Cathode, ICM22B/D Segments = O; Outputs = OPE Common Cathode, ICM22B/D Segments = OFF; Outputs = OPE Common Anode, ICM22A/C V OUT = - 2.V Common Cathode, ICM22B/D V OUT = +.V Digit Leakage Current, I DLK Shutdown Mode, V OUT = 2.V Common Anode, ICM22A/C Peak Segment Drive Current, I SEG Segment Leakage Current, I SLK Shutdown Mode, V OUT =.V Common Cathode, 22B/D Common Anode, ICM22A/C V OUT = +.V Common Cathode, 22B/D V OUT = - 2.V Shutdown Mode, V OUT = Common Anode, ICM22A/C Shutdown Mode, V OUT = Common Cathode, ICM22B/D ma µa ma µa - - Input Leakage Current, I IL All Inputs Except Pin 9 ICM22C, ICM22D V I = µa All Inputs Except Pin 9 ICM22C, ICM22D V I =.V

5 ICM22 Electrical Specifications = +.V ±%, = V, Unless Otherwise Specified IDUSTRIAL TEMPERATURE RAGE, IPI, IJI, IBI DEVICES (Continued) PARAMETER Display Scan Rate, f MUX Per Digit Hz Inter-Digit Blanking Time, t IDB µs Logical Input Voltage, V IH Three Level Input: Pin 9 ICM22C, ICM22D Hexadecimal = V V Floating Input, V IF Three Level Input: Pin 9 ICM22C, ICM22D Code B = V Logical Input Voltage, V IL Three Level Input: Pin 9 ICM22C, ICM22D Shutdown = V Three Level Input Impedance, Z I Logical Input Voltage, V IH Logical Input Voltage, V IL TEST CODITIOS V CC = V Pin 9 of ICM22C and ICM22D All Inputs Except Pin 9 of ICM22C, ICM22D = V All Inputs Except Pin 9 of ICM22C, ICM22D = V T A = 2 o C - o C TO o C MI TYP MAX MI TYP MAX V V kω V V SWITCHIG SPECIFICATIOS = +.V ±%, = V, V IL = +.V, V IH = +2.V Write Pulsewidth (Low), t WL ns Write Pulsewidth (High), t WH ns Mode Hold Time, t MH ICM22A, ICM22B ns Mode Setup Time, t MS ICM22A, ICM22B ns Data Setup Time, t DS ns Data Hold Time, t DH ns Digit Address Setup Time, t AS ICM22C, ICM22D ns Digit Address Hold Time, t AH ICM22C, ICM22D ns UITS

6 ICM22 Timing Diagrams MODE t MS t MH MODE IPUT DATA t WL t DS VALID t DH t WH (D) DATA PULSES COTROL WORD TYPE OF DECODER?ID6 DECODE/O DECODE? ID SHUTDOW?ID DATA COMIG ID (D) DO T CARE COTROL WORD TYPE OF DECODER?ID6 DECODE/O DECODE? ID SHUTDOW? ID DATA COMIG ID FIGURE. ICM22A/B CYCLE FIGURE 2. ICM22A/B SEQUETIAL -DIGIT RAM UPDATE DIGIT ADDRESS DAO-DAZ t AS VALID t AH t WL twh t DS t DH DATA VALID DATA FIGURE. ICM22C/D CYCLE ITERDIGIT BLAKIG ITERAL SIGAL D2 D D D µs (TYP) FREE RUIG ITERDIGIT BLAKIG 2µs (TYP) FREE RUIG (PER DIGIT) TYPICAL DIGITS PULSES D D6 D D FIGURE. DISPLAY DIGITS MULTIPLEX (COMMO AODE DISPLAY) 6

7 ICM22 Typical Performance Curves - o C 2 o C 2 o C 2 o C 2 o C 2 ) A (m I DIG ) A (m 6 I SEG - o C 2 o C 2 o C o C. 2. -V DIG (V) V SEG (V) FIGURE. COMMO AODE DIGIT DRIVER I DIG vs ( - V DIG ) FIGURE 6. COMMO AODE SEGMET DRIVER I SEG vs V SEG - o 2 o C C 2 o C ) A (m I DIG 2 - o C 2 o C 2 ) A (m I SEG 2 o C V DIG (V) -V SEG (V) FIGURE. COMMO CATHODE DIGIT DRIVER I DIG vs V DIG FIGURE. COMMO CATHODE SEGMET DRIVER I SEG vs ( - V SEG ) TABLE. ICM22A PI ASSIGMETS AD DESCRIPTIOS PI O. AME FUCTIO DESCRIPTIO SEG c Output LED Display Segments c, e, b and Decimal Point Drive Lines. 2 SEG e SEG b DP ID6, (HEXA/CODE B) Input When MODE Low: Display Data Input, Bit. When MODE High: Control Bit, Decoding Scheme Selection: High, Hexadecimal Decoding; Low, Code B Decoding. 6 ID, (DECODE) Input When MODE Low: Display Data Input, Bit 6. When MODE High: Control Bit, Decode/o Decode Selection: High, o Decode; Low, Decode. ID, (DATA COMIG) Input When MODE Low: Display Data Input, Bit, Decimal Point Data. When MODE High: Control Bit, Sequential Data Update Select: High, Data Coming; Low, o Data Coming. Input Data Input Will Be Written to Control Register or Display RAM on Rising Edge of.

8 ICM22 TABLE. ICM22A PI ASSIGMETS AD DESCRIPTIOS (Continued) PI O. AME FUCTIO DESCRIPTIO 9 MODE Input Selects Data to Be Loaded to Control Register or Display RAM: High, Loads Control Register; Low, Loads Display RAM. ID, (SHUTDOW) Input When MODE Low: Display Data Input, Bit. When MODE High: Control Bit, Low Power Mode Select: High, ormal Operation; Low, Oscillator and Display Disabled. ID Input When MODE Low: Display Data Input, Bit 2. When MODE High and ID (DATA COMIG) Low: Digit Address, Bit 2, Single Digit Update Mode. 2 ID Input When MODE Low: Display Data Input, Bit. When MODE High and ID (DATA COMIG) Low: Digit Address, LSB, Single Digit Update Mode. ID2 Input When MODE Low: Display Data Input, Bit. When MODE High and ID (DATA COMIG) Low: Digit Address, MSB, Single Digit Update Mode. ID Input When MODE Low: Display Data Input, Bit. When MODE High: RAM Bank Select (Decode Modes Only): High, RAM Bank A; Low, RAM Bank B DIGIT Output LED Display Digits, 2, and Drive Lines. 6 DlGlT 2 DIGIT DlGlT 9 Supply Device Positive Power Supply Rail. 2 DIGIT Output LED Display Digits,, 6 and Drive Lines. 2 DlGlT 22 DlGlT 6 2 DIGlT 2 SEG f Output LED Display Segments f, d, g and a Drive Lines. 2 SEG d 26 SEG g 2 SEG a 2 Supply Device Ground or egative Power Supply Rail. TABLE 2. ICM22B PI ASSIGMETS AD DESCRIPTIOS PI O. AME FUCTIO DESCRIPTIO DIGIT Output LED Display Digits, 6, and Drive Lines. 2 DlGlT 6 DIGIT DlGlT ID6, (HEXA/CODE B) Input When MODE Low: Display Data Input, Bit. When MODE High: Control Bit, Decoding Scheme Selection: High, Hexadecimal Decoding; Low, Code B Decoding. 6 ID, (DECODE) Input When MODE Low: Display Data Input, Bit 6. When MODE High: Control Bit, Decode/o Decode Selection: High, o Decode; Low, Decode.

9 ICM22 TABLE 2. ICM22B PI ASSIGMETS AD DESCRIPTIOS (Continued) PI O. AME FUCTIO DESCRIPTIO ID, (DATA COMIG) Input When MODE Low: Display Data Input, Bit, Decimal Point Data. When MODE High: Control Bit, Sequential Data Update Select: High, Data Coming; Low, o Data Coming. Input Data Input Will Be Written to Control Register or Display RAM on Rising Edge of. 9 MODE Input Selects Data to Be Loaded to Control Register or Display RAM: High, Loads Control Register; Low, Loads Display RAM. ID, (SHUTDOW) Input When MODE Low: Display Data Input, Bit. When MODE High: Control Bit, Low Power Mode Select: High, ormal Operation; Low, Oscillator and Display Disabled. ID Input When MODE Low: Display Data Input, Bit 2. When MODE High and ID (DATA COMIG) Low: Digit Address, Bit 2, Single Digit Update Mode. 2 ID Input When MODE Low: Display Data Input, Bit. When MODE High and ID (DATA COMIG) Low: Digit Address, LSB, Single Digit Update Mode. ID2 Input When MODE Low: Display Data Input, Bit. When MODE High and ID (DATA COMIG) Low: Digit Address, MSB, Single Digit Update Mode. ID Input When MODE Low: Display Data Input, Bit. When MODE High: RAM Bank Select (Decode Modes Only): High, RAM Bank A; Low, RAM Bank B. DP Output LED Display Decimal Point and Segments a, b, and d Drive Lines 6 SEG a SEG b SEG d 9 Supply Device Positive Power Supply Rail. 2 SEG c Output LED Display Segments c, e, f and g Drive Lines. 2 SEG e 22 SEG f 2 SEG g 2 DIGIT Output LED Display Digits, 2, and Drive Lines. 2 DIGIT 2 26 DIGIT 2 DIGIT 2 Supply Device Ground or egative Power Supply Rail. TABLE. ICM22C PI ASSIGMETS AD DESCRIPTIOS PI O. AME FUCTIO DESCRIPTIO SEG c Output LED Display Segments c, e, band Decimal Point Drive Lines. 2 SEG e SEG b DP DA Input Digit Address Input, Bit LSB. 6 DA Input Digit Address Input, Bit 2. 9

10 ICM22 TABLE. ICM22C PI ASSIGMETS AD DESCRIPTIOS (Continued) PI O. AME FUCTIO DESCRIPTIO ID, (IPUT DP) Input Display Decimal Point Data Input, egative True. Input Data Input Will Be Written to Display RAM on Rising Edge of. 9 HEXA/CODE B/SHUTDOW Input DA2 Input Digit Address Input, Bit, MSB. ID Input Display Data Inputs. 2 ID ID2 ID Three Level Input. Display Function Control: High, Hexadecimal Decoding; Float, Code B Decoding; Low, Oscillator, and Display Disabled. DIGIT Output LED Display Digits, 2, and Drive Lines. 6 DlGlT 2 DIGIT DlGlT 9 Supply Device Positive Power Supply Rail. 2 DIGIT Output LED Display Digits,, 6 and Drive Lines. 2 DlGlT 22 DlGlT 6 2 DIGlT 2 SEG f Output LED Display Segments f, d, g and a Drive Lines. 2 SEG d 26 SEG g 2 SEG a 2 Supply Device Ground or egative Power Supply Rail. TABLE. ICM22D PI ASSIGMETS AD DESCRIPTIOS PI O. AME FUCTIO DESCRIPTIO DIGIT Output LED Display Digits, 6, and Drive Lines. 2 DlGlT 6 DIGIT DlGlT DA Input Digit Address Input, Bit LSB. 6 DA Input Digit Address Input, Bit 2. ID, (IPUT DP) Input Display Decimal Point Data Input, egative True. Input Data Input Will Be Written to Display RAM on Rising Edge of. 9 HEXA/CODE B/SHUTDOW Input DA2 Input Digit Address Input, Bit, MSB. ID Input Display Data Inputs. 2 ID ID2 ID Three Level Input. Display Function Control: High, Hexadecimal Decoding; Float, Code B Decoding; Low, Oscillator and Display Disabled.

11 ICM22 TABLE. ICM22D PI ASSIGMETS AD DESCRIPTIOS (Continued) PI O. AME FUCTIO DESCRIPTIO DP Output LED Display Decimal Point and Segments a, b, and d Drive Lines. 6 SEG a SEG b SEG d 9 Supply Device Positive Power Supply Rail. 2 SEG c Output LED Display Segments c, e, f and g Drive Lines. 2 SEG e 22 SEG f 2 SEG g 2 DIGIT Output LED Display Digits, 2, and Drive Lines. 2 DIGIT 2 26 DIGIT 2 DIGIT 2 Supply Device Ground or egative Power Supply Rail. Detailed Description System Interfacing and Data Entry Modes, ICM22A and ICM22B The ICM22A/B devices are compatible with the architectures of most microprocessor systems. Their fast switching characteristics makes it possible to access them as a memory mapped I/O device with no wait state necessary in most microcontroller systems. All the ICM22A/B inputs, including MODE, feature a 2ns minimum setup and ns hold time with a 2ns minimum pulse. Input logic levels are TTL and CMOS compatible. Figure 9 shows a generic method of driving the ICM22A/B from a microprocessor bus. To the microprocessor, each device appears to be 2 separate I/O locations; the Control Register and the Display RAM. Selection between the two is accomplished by the MODE input driven by address line A. Input data is placed on the ld - ld lines. The input acts as both a device select and write cycle timing pulse. See Figure and Switching Specifications Table for write cycle timing parameters. The ICM22A/B have three data entry modes: Control Register update without RAM update, sequential -digit update and single digit update. In all three modes a control word is first written by pulsing the input while the MODE input is high, thereby latching data into the Control Register. The logic level of individual bits in the Control Register select Shutdown, Decode/o Decode, Hex/Code B, RAM bank A/B and Display RAM digit address as shown in Tables and 2. The ICM22A/B Display RAM is divided into 2 banks, called bank A and B. When using the Hexadecimal or code B display modes, these RAM banks can be selected separately. This allows two separate sets of display data to be stored and displayed alternately. otice that the RAM bank selection is not possible in o-decode mode, this is because the display data in the o-decode mode has bits, but in Decoded schemes (Hex/Code B) is only bits (ld - ld data). It should also be mentioned that the decimal point is independent of selected bank, a turned on decimal point will remain on for either bank. Selection of the RAM banks is controlled by ld input. The ld logic level (during Control Register update) selects which bank of the internal RAM to be written to and/or displayed. Control Register Update without RAM Update The Control Register can be updated without changing the display data by a single pulse on the input, with MODE high and DATA COMIG low. If the display is being decoded (Hex/Code B), then the value of ld determines which RAM bank will be selected and displayed for all eight digits. Sequential -Digit Update The logic state of DATA COMIG (ld) is also latched during a Control Register update. If the latched value of DATA COMIG (ld) is high, the display becomes blanked and a sequential -digit update is initiated. Display data can now be written into RAM with successive pulses, starting with digit and ending with digit (See Figure 2). After all RAM locations have been written to, the display turns on again and the new data is displayed. Additional write pulses are ignored until a new Control Register update is performed. All digits are displayed in the format (Hex/Code B or o Decode) specified by the control word that preceded the digit update. If a decoding scheme (Hex/Code B) is to be used, the value of ld during the control word update determines which RAM bank will be written to. Single Digit Update In this mode each digit data in the display RAM can be updated individually without changing the other display data. First, with MODE input high, a control word is written to the Control Register carrying the following information; DATA COMIG (ld) low, the desired display format data on ld - ld6, the RAM bank selected by ld (if decoding is selected) and the address of the digit to be updated on data lines ld - ld2 (See Table ). A second write to the ICM22A/B, this time with MODE input low,

12 ICM22 transfers the data at the ld - ld inputs into the selected digit s RAM location. In single digit update mode, each individual digit s data can be specified independently for being displayed in Decoded or o-decode mode. For those digits which decoding scheme (Hex/Code B) is selected, only one can be effective at a time. Whenever a control word is written, the specified decoding scheme will be applied to all those digits which selected to be displayed in Decoded mode. DATA BUS D-D M E T S Y S R O S E C O R P O R IC M I/O OR MEMORY PULSE A-A DECODER EABLE ADDRESS DECODER D - D DEVICE SELECT AD PULSE A ID ID MODE ITERSIL ICM22A/B SEGMETS DRIVE DIGITS DRIVE LED DISPLAY ADDRESS BUS A - A FIGURE 9. ICM22A/B MICROPROCESSOR SYSTEM ITERFACIG TABLE. DIGITS ADDRESS, ICM22A/B The ICM22C/D devices do not have any control register, and also they do not provide the o Decode display format. Hexadecimal D2 IPUT DATA LIES ld2 ld SELECTED DIGIT DlGlT DlGlT 2 DIGlT DlGlT DIGIT DlGlT 6 DlGlT DlGlT or Code B character selection and shutdown mode are directly controlled through the three level input at Pin 9, which is accordingly called HEXA/CODE B/SHUTDOW. See Tables and for input and output definitions of the ICM22C/D devices. Display Formats The ICM22A and ICM22B have three possible display formats; Hexadecimal, Code B and o Decode. Table 6 shows the character sets for the decode modes and their corresponding input code. The display formats of the ICM22A/B are selected by writing data to bits ID, ID and ID6 of the Control Register (See Table and 2 for input Definitions). Hexadecimal and Code B data is entered via ID-lD and ID controls the decimal point. System Interfacing, ICM22C and ICM22D The ICM22C/D devices are directly compatible with the architecture of most microprocessor systems. Their fast switching characteristics make it possible to access them as a memory mapped I/O device with no wait state necessary in most microcontroller systems. All the ICM22C/D inputs, excluding HEXA/CODE B/SHUTDOW, feature a 2ns minimum setup and ns hold time with a 2ns minimum pulse. Input logic levels are TTL and CMOS compatible. Figure shows a generic method of driving the ICM22C/D from a microprocessor bus. To the microprocessor, the bytes of the Display RAM appear to be separate I/O locations. Loading the ICM22C/D is quite similar to a standard memory write cycle. The address of the digit to be updated is placed on lines DA - DA2, the data to be written is placed on lines ID - ld and ID, then a low pulse on input will transfer the data in. See Figure and Switching Characteristics Table for write cycle timing parameters. TABLE 6. DISPLAY CHARACTER SETS IPUT DATA CODE DISPLAY CHARACTERS ID ID2 ID ID HEXADECIMAL CODE B

13 ICM22 TABLE 6. DISPLAY CHARACTER SETS (Continued) IPUT DATA CODE DISPLAY CHARACTERS ID ID2 ID ID HEXADECIMAL CODE B A - b E C H d L E P F (Blank) M E T S Y S R O S E C O R P O R IC M I/O OR MEMORY PULSE A - A DECODER EABLE DATA BUS D - D ADDRESS DECODER DEVICE SELECT AD PULSE A - A2 ID - ID AD ID ITERSIL ICM22C/D SEGMETS DRIVE DA - DA2 DIGITS DRIVE LED DISPLAY ADDRESS BUS A - A FIGURE. ICM22C/D MICROPROCESSOR SYSTEM ITERFACIG The o Decode mode of the ICM22A and ICM22B allows the direct segment-by-segment control of all 6 segments driven by the device. In the o Decode mode, the input data directly control the outputs as shown in Table. TABLE. O DECODE SEGMET LOCATIOS DATA IPUT ID ID6 ID ID ID ID2 ID ID Controlled Segment Decimal Point a f b g e c d a b c e g f d An input high level turns on the respective segment, except for the decimal point, which is turned on by an input low level on ID. The o Decode mode can be used in different applications such as bar graph or status panel driving where each segment controls an individual LED. DP FIGURE. DIGITS SEGMET ASSIGMETS The ICM22C and ICM22D have only the Hexadecimal and Code B character sets. The HEXA/CODE B/SHUTDOW input, pin 9, requires a three level input. Pin 9 selects the Hexadecimal format when pulled high, the Code B format when floating or driven to mid-supply, and the shutdown mode when pulled low (See Tables and ). Table 6 also applies to the ICM22C/D devices. Shutdown and Display Banking When shutdown, the ICM22 enters a low power standby mode typically consuming only µa of supply current for the ICM22A/B and 2.µA for the ICM22C/D. In this mode the ICM22 turns off the multiplex scan oscillator as well as the digit and segment drivers. However, input data can still be entered when in the shutdown mode. Data is retained in memory even with the supply voltage as low as 2V. The ICM22A/B is shutdown by writing a control word with Shutdown (ld) low. The ICM22C/D is put into shutdown mode by driving pin 9, HEXA/CODE B/SHUTDOW, low. The ICM22 operating current with the display blanked is within µa - 2µA for all versions. All versions of the ICM22 can be blanked by writing Hex FF to all digits and selecting Code B format. The ICM22A and ICM22B can also be blanked by selecting o Decode mode and writing Hex to all digits (See Tables 6 and ).

14 ICM22 Common Anode Display Drivers, ICM22A and ICM22C The common anode digit and segment driver output schematics are shown in Figure 2. The common anode digit driver output impedance is approximately Ω. This provides a nearly constant voltage to the display digits. Each digit has a minimum of 2mA drive capability. The -Channel segment driver s output impedance of Ω limits the segment current to approximately 2mA peak current per segment. Both the segment and digit outputs can directly drive the display, current limiting resistors are not required. Individual segment current is not significantly affected by whether other segments are on or off. This is because the segment driver output impedance is much higher than that of the digit driver. This feature is important in bar graph applications where each bar graph element should have the same brightness, independent of the number of elements being turned on. Common Cathode Display Drivers, ICM22B and ICM22D The common cathode digit and segment driver output schematics are shown in Figure. The -channel digit drivers have an output impedance of approximately Ω. Each digit has a minimum of ma drive capability. The segment drivers have an output impedance of approximately Ω with typically ma peak current drive for each segment. The common cathode display driver output currents are only / of the common anode display driver currents. Therefore, the ICM22A and ICM22C common anode display drivers are recommended for those applications where high display brightness is desired. The ICM22B and ICM22D common cathode display drivers are suitable for driving bubble-lensed monolithic segment displays. They can also drive individual LED displays up to. inches in height when high brightness is not required. Display Multiplexing Each digit of the ICM22 is on for approximately 2µs, with a multiplexing frequency of approximately 9Hz. The ICM22 display drivers provide interdigit blanking. This ensures that the segment information of the previous digit is gone and the information of the next digit is stable before the next digit is driven on. This is necessary to eliminate display ghosting (a faint display of data from previous digit superimposed on the next digit). The interdigit blanking time is µs typical with a guaranteed 2µs minimum. The ICM22 turns off both the digit drivers and the segment drivers during the interdigit blanking period. The digit multiplexing sequence is: D2, D, D, D, D, D6, D and D. A typical digit s drive pulses are shown on Figure. Due to the display multiplexing, the driving duty cycle for each digit is 2% ( x / ) This means the average current for each segment is / of its peak current. This must be considered while designing and selecting the displays. Driving Larger Displays If very high display brightness is desired, the ICM22 display driver outputs can be externally buffered. Figures thru 6 show how to drive either common anode or common cathode displays using the ICM22 and external driver circuit for higher current displays. Another method of increasing display currents is to connect two digit outputs together and load the same data into both digits. This drives the display with the same peak current, but the average current doubles because each digit of the display is on for twice as long, i.e., / duty cycle versus /. DIGIT STROBE ITERDIGIT BLAKIG SHUTDOW P 2kΩ 2kΩ 2mA COMMO AODE DIGIT OTE: When SHUTDOW goes low ITERDIGIT BLAKIG also stays low. FIGURE 2A. DIGIT DRIVER SEGMET DATA ITERDIGIT BLAKIG SHUTDOW P 2kΩ COMMO AODE SEGMET Ω FIGURE 2B. SEGMET DRIVER FIGURE 2. COMMO AODE DISPLAY DRIVERS DIGIT STROBE ITERDIGIT BLAKIG SHUTDOW FIGURE A. DIGIT DRIVER P 2kΩ COMMO CATHODE DIGIT Ω

15 ICM22 SEGMET DATA P 2mA K.A PEAK 26 ITERDIGIT BLAKIG SHUTDOW 2kΩ 2kΩ Ω COMMO CATHODE SEGMET OTE: When SHUTDOW goes low ITERDIGIT BLAKIG also stays low. FIGURE B. SEGMET DRIVER FIGURE. COMMO CATHODE DISPLAY DRIVERS Ω ICM22C/D Ω SEGMET DIGIT Ω K 2Ω (ma PEAK ) 2229 FIGURE 6. DRIVIG HIGH CURRET DISPLAY, COMMO CATHODE ICM22B/D TO COMMO CATHODE DISPLAY K Three Level Input, ICM22C and ICM22D ICM22A/B DIGIT UP TO A As mentioned before, pin 9 is a three level input and controls three functions: Hexadecimal display decoding, Code B display decoding and shutdown mode. In many applications, pin 9 will be left open or permanently wired to one state. When pin 9 can not be permanently left in one state, the circuits illustrated in Figure can be used to drive this three level input. SEGMET K HIGH = HEX LOW = SHUTDOW C26 THREE-STATE BUFFER PI 9 HIGH = HEX OR SHUTDOW FIGURE. DRIVIG HIGH CURRET DISPLAY, COMMO AODE ICM22A/C TO COMMO AODE DISPLAY Ω ICM22C/D SEGMET 2229 Ω (ma PEAK ) LOW = CODE B HIGH = HEX LOW = SHUTDOW HIGH = HEX OR SHUTDOW LOW = CODE B HIGH = CODE B LOW = HEX HIGH = SHUTDOW LOW = CODE B HIGH = SHUTDOW LOW = HEX HIGH = SHUTDOW LOW = CODE B CD6 CD66 COTROL CD69 CD69 CD69 OPE DRAI OR OPE COLLECTOR PI 9 PI 9 PI 9 PI 9 PI 9 Ω DIGIT ma 26.A PEAK FIGURE. DRIVIG HIGH CURRET DISPLAY, COMMO CATHODE ICM22B/D TO COMMO CATHODE DISPLAY FIGURE. ICM22C/D PI 9 DRIVE CIRCUITS Power Supply Bypassing Connect a minimum of µf in parallel with.µf capacitors between and of ICM22. These capacitors should be placed in close proximity to the device to reduce the power supply ripple caused by the multiplexed LED display drive current pulses.

16 ICM22 Test Circuits + V - 2 ID6 (HEXA/CODE B) ID (DECODE) 6 ID (DATA COMIG) MODE 9 ID (SHUTDOW) ID ID 2 ID2 ID µf +.µf ICM22A COMMO AODE DISPLAY D D D6 D D D D2 D f d g a c e b DP FIGURE. FUCTIOAL TEST CIRCUIT # 6

17 ICM22 Test Circuits (Continued) DIGIT ADDRESS DIGIT ADDRESS 6 ID (D.P.) HEXA/CODE B/SHUTDOW 9 DIGIT ADDRESS 2 ID ID 2 ID2 ID ICM22D V - µf +.µf g f e c d b a DP D D D6 D D D D2 D COMMO AODE DISPLAY FIGURE 9. FUCTIOAL TEST CIRCUIT #2 All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9 quality systems. Intersil Corporation s quality certifications can be viewed at Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. o license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see