Simultaneous Control of Subthreshold and Gate Leakage Current in Nanometer-Scale CMOS Circuits

Transcription

1 Simultaneous Control of Subthreshold and Gate Leakage Current in Nanometer-Scale CMOS Circuits Youngsoo Shin 1, Sewan Heo 1, Hyung-Ock Kim 1, Jung Yun Choi 2 1 Dept. of Electrical Engineering, KAIST, KOREA 2 Samsung Electronics, KOREA

2 Outline Introduction: leakage current, power gating Supply switching with ground collapse (SSGC) Implementation of SSGC Experimental results Summary 2

3 Leakage Current Leakage current in nanometer regime Exponential growth of leakage Subthreshold leakage due to reduced V th Gate leakage due to reduced T ox 2 1 Active V ss 2 Current (A) Leakage 1 Year Courtesy of Intel art01_advpackagetech/p04_techtrends.htm 3

4 L e k a g e c u r r e n t [ u A ] Leakage Current Gate leakage current Grow faster than subthreshold leakage May dictate the total leakage in future technology Leakage current [ua] Subthreshold leakage Gate leakage 74% 58% 65-nm 45-nm ISCAS benchmark s3384 4

5 Power gating Power Gating Widely used to suppress subthreshold leakage Active mode: footer turned-on mode: footer cuts off power rail D inputs State-retention element Combinational logic B1 B2 Q Output-holding Input circuit outputs Output -holding Output V ssv Footer B2 Balloon circuit [Schigematsu-JSSC-1997] State-retention elements 5

6 Power Gating Power gating in nanometer regime State-retention and output-holding circuit leak gate leakage Leakage saving from power gating greatly reduced Leakage saving [X] Decreased leakage saving nm 90-nm 65-nm 45-nm Technology ISCAS benchmark s1269 w/ power gating 6

7 Supply Switching with Ground Collapse SSGC: supply control + power gating V sv Supply switching v Active Supply switching : Footer: on inputs Combinational logic Footer V ssv Output -holding outputs Supply switching : V sv (< Footer: off dd ) 7

8 Supply Switching with Ground Collapse SSGC circuit Reduce leakage of combinational logic through power gating (ground collapse) Reduce leakage of FF through lowered voltage (supply switching) and power gating No need to use state-retention FF inputs Combinational logic V sv V sv Supply switching v v outputs Output -holding outputs V ss Footer V ssv 8

9 Supply Switching with Ground Collapse Implementation of SSGC Design of supply switching Physical design Power networks SSGC flip-flop flop Footer Output-holding circuit inputs Combinational logic V sv V sv Supply switching v v outputs Output -holding outputs V ss Footer V ssv 9

10 Supply Switching Circuits M1 switch Supplying active High V th PMOS Sizing affects circuit performance M2 switch Supplying standby-mode V sv Low V th NMOS M1 (high V th ) inputs Combinational logic V sv V sv Supply switching Footer V ssv v Output -holding Supply switching M2 (low V th ) outputs v 10

11 Supply Switching Circuits v in standby Bounded by the potential to retain states in FFs + noise margin Factors: temperature, process variation, states (0 or 1), FF types 260mV for state retention D Q Lowest v [mv] nm, 1.0V Temperature [ C] 11

12 Supply Switching Circuits Design of M2 switch Selection of M2 size and V sv for Efficient leakage saving Lowest v (e.g. 260mV) Voltage drop across M2 dictates V sv M2 M2 size and V sv V sv v R M2 V sv v I leakage (125 C) V = V + I R sv R ddv M2 = leakage Rmin M2 size M2 12

13 V [ m V ] s v Supply Switching Circuits Design of M2 switch M2 size vs. V sv V Trade-off between area overhead and leakage power = V + I sv ddv leakage Rmin M2 size Vsv [mv] V sv -M2 size of ETM Temp=125 C M2 size = 20um Leakage current [ua] Leakage-M2 size of ETM Temp=25 C M2 size = 20um M2 size [um] M2 size [um] 13

14 V d d Physical Design of SSGC Power networks for SSGC Conventional and V ss rails as v and V ssv rails Vsv footer M2 : vertical rails V ss : horizontal rails V sv Supply switching v M1 Vss inputs Combinational logic Footer V ssv Output -holding outputs Vddv Vssv FF v and V ssv rails for combinational logic cells 14

15 Physical Design of SSGC SSGC flip-flop flop State maintained in slave latch with low V sv No need of state-retention element Low gate and subthreshold leakage current Other parts are power gated for further reduction Clock TE TE Conventional flip-flop D TE TI TE Q Q PG flip-flop State retention SSGC flip-flop (16% increase) 15

16 Physical Design of SSGC Footer layout Isolated body (body bias to V ss ) preferred for leakage current area overhead due to well isolation Building block-based based approach: : flexible placement, control of area overhead Vddv V ss Isolater A Slice Isolated p-well B Isolater C V ssv D 16

17 Physical Design of SSGC Output-holding circuit Output-holding are needed due to V sv (< ) in standby Utilize high V th to reduce subthreshold leakage Output Input Output Input Isolated n-well 17

18 SSGC Design Flow Gate-level netlist Footer sizing M1 sizing M2 and V sv design Footer and supply switching design Inserting footer, M1, M2 Replacing Flip-flops Inserting output-holding Modifying SSGC netlist SSGC physical design Power network Footer, M1, M2 placement Auto P & R SSGC layout 18

19 Experimental Results Test ISCAS and ITC benchmark 65- and 45-nm predictive models Leakage reduction [x] PG AVG. PG: 8.2 SSGC AVG. SSGG: 51.4 Circuits s344 s1269 s3384 b03 b14 65nm I / Os 8 / / / 26 4 / 4 32 / 54 s344 s1269 s3384 b03 b14 SEs Gates PG AVG. PG: SSGC AVG. SSGG: nm s344 s1269 s3384 b03 b14 19

20 Case Study: ETM Embedded Trace Macrocell (ETM) Debugging and tracing core for ARM 90nm, 1.0V commercial process I / Os SEs Gates Leakage 320 / 124 5,501 90, uA Footer, M1, and M2 sizing M1 and footer sizing for 10% delay increase M2 sizing to optimize leakage at room temperature Vsv [mv] V sb [mv] M2 size [um] Total leakage current [ua] 20

21 m m Case Study: ETM SSGC implementation result Total leakage saving: 32 at 25 C Area increase: 3% Wirelength increase: 6% Power rings Leakage current breakdown Output-holding 0.3µA Footer 0.1µA 0.71 mm SEs 12.8µA 0.71 mm 21

22 Summary Power gating Widely used to suppress subthreshold leakage NOT efficient in nanometer technology due to gate leakage of storage elements and output-holding Supply switching with ground collapse Overcomes the limitation of power gating Demonstrates cell-based semicustom design flow based on SSGC 22