MOS Logic Families. Somayyeh Koohi. Department of Computer Engineering Sharif University of Technology

Transcription

1 MOS Logic Families Somayyeh Koohi Department of Computer Engineering Adapted with modifications from lecture notes prepared by author

2 Topics Pseudo-nMOS gates DCVS logic Domino gates Modern VLSI Design: Chap3 2of 29

3 Pseudo-NMOS Uses a p-type transistor as a resistive pullup vn-type network for pulldowns Modern VLSI Design: Chap3 3of 29

4 Characteristics Consumes static power Much smaller pullup network than static gate Falling time is longer because pullup is fighting Modern VLSI Design: Chap3 4of 29

5 Output voltages Logic 1 output is always at V DD Logic 0 output is above Vss V OL = 0.25 (V DD -V SS ) is one plausible choice Modern VLSI Design: Chap3 5of 29

6 Producing output voltages For logic 0 output: pullup and pulldown form a voltage divider vmust choose n, p transistor sizes to create effective resistances of the required ratio Effective resistance of pulldown network must be comptued in worst case vseries n-types means higher resistance Ł larger transistors Modern VLSI Design: Chap3 6of 29

7 Transistor ratio calculation For creatinglogic 0 output, (initially): v Pullup is in linear region,v ds = V out -(V DD -V SS ) v Pulldown is in saturationv ds = (V DD -V SS ) Pullup and pulldown have same current flowing through them( - I dp = I dn ) For equal noise margins, using 0.5 µm parameters, 3.3V power supply: v (W p /L p )/ (W n /L n ) = 3.9 Modern VLSI Design: Chap3 7of 29

8 Topics Pseudo-nMOS gates DCVS logic Domino gates Modern VLSI Design: Chap3 8of 29

9 DCVS logic DCVSL Ł Differential Cascode Voltage Switch Logic Static logic vconsumes no staticpower(like standard CMOS) Uses latch to compute output quickly Requires true/complement inputs vproduces true/complement outputs Modern VLSI Design: Chap3 9of 29

10 DCVS structure Modern VLSI Design: Chap3 10 of 29

11 DCVS operation Exactly one of true/complement pulldown networks will complete a path to the power supply Pulldown network will lower output voltage Ł turning on other p-type Ł turns off p-type for node which is going down vpositive feedback Modern VLSI Design: Chap3 11 of 29

12 DCVS Example Modern VLSI Design: Chap3 12 of 29

13 Topics Pseudo-nMOS gates DCVS logic Domino gates Modern VLSI Design: Chap3 13 of 29

14 Precharged logic Precharged logic uses stored charge to help evaluation Precharge node, selectively discharge it Take advantage of higher speed of n-types Requires multiple phases for evaluation Modern VLSI Design: Chap3 14 of 29

15 Domino logic Uses precharge clock to compute output in two phases: vprecharge vevaluate Not a complete logic family vcannot invert Modern VLSI Design: Chap3 15 of 29

16 Domino phases Controlled by clock φ Precharge: p-type pullup precharges the storage node v Inverter ensures that output goes low v Footer : No path to Vss while precharging Evaluate: storage node may be pulled down, so output goes up Modern VLSI Design: Chap3 16 of 29

17 Domino operation Modern VLSI Design: Chap3 17 of 29

18 Domino effect Gate outputs fall(rise)in sequence: gate 1 gate 2 gate 3 Modern VLSI Design: Chap3 18 of 29

19 Monotonicity Domino gates inputs must be monotonically increasing vglitch causes storage node to discharge Modern VLSI Design: Chap3 19 of 29

20 Output buffer Inverting buffer isolates storage node Storage node and inverter have correlated values Modern VLSI Design: Chap3 20 of 29

21 Domino buffer Output inverter is needed for two reasons: 1. Make sure that outputs start low, go high so that domino output can be connected to another domino gate Can it be avoided by using an NMOS (controlled by ø) in series with the pull-down network? (consider two cascaded gates) 2. Protects storage node from outside influence Modern VLSI Design: Chap3 21 of 29

22 Using domino logic Can rewrite logic expression using DeMorgan s Laws: v(a + b) = a b v(ab) = a + b Add inverters to network inputs/outputs as required Modern VLSI Design: Chap3 22 of 29

23 Charge-Storage Principle Node X holds charge for long periods t H : time to bring node X from V dd to 0.5 V dd C x : dynamic node capacitance = C ox WL t clk << t H for dynamic circuits to work Modern VLSI Design: Chap3 23 of 29

24 Charge-Storage Principle (Cont d) Future trends: v C x decreases; V dd decreases; I leakage increases v This implies t H decreases but so does t clk Use a keeper transistor Modern VLSI Design: Chap3 24 of 29

25 Domino and stored charge(charge sharing) Charge can be stored in source/drain connections between pulldowns Stored charge can be sufficient to affect precharge node Can be averted by precharging the internal pulldown network nodes along with the precharge node v Additional keepers Modern VLSI Design: Chap3 25 of 29

26 Charge-sharing What is the value of V 2? Solution: v Make C 1 >> C 2 v Reduce V t of the output inverter v Use a keeper/bleeder transistor v Use Multiple prechargetransistors Modern VLSI Design: Chap3 26 of 29

27 Charge sharing example Long chains of switches have intermediate nodes which may be disconnected from power supplies v So, charge sharing C ia C ab C bc Modern VLSI Design: Chap3 27 of 29

28 Charge over time time i C ia a C ab b C bc c C /2 1 1/ /2 0 3/4 1 3/ /4 0 3/ /8 1 3/8 0 3/4 C ia C ab C bc Modern VLSI Design: Chap3 28 of 29

29 Dynamic logic vs. Static Logic + Faster v Used in data-paths of high performance microprocessors - Smaller area v Smaller pullup - Extra clock signal v Consumes extra power -/+ Dynamic power depends upon probability of logic values rather than probability of a transition v Alternating output value for logic 1 - Susceptible to noise v Careful physical design required Modern VLSI Design: Chap3 29 of 29