Leakage Current Reduction in Sequential Circuits by Modifying the Scan Chains. Outline

Transcription

1 eakage Current Reduction in Sequential s by Modifying the Scan Chains Afshin Abdollahi University of Southern California Farzan Fallah Fujitsu aboratories of America Massoud Pedram University of Southern California 4 th International Symposium on QUAITY EECTRONIC DESIGN March 24-26, 23, San Jose, CA, USA Outline Introduction eakage Reduction Techniques Input Vector Control Scan Based Testing Using the Scan Chain for eakage Reduction Results

2 Introduction Decrease in Transistor Size Increase in Operation Frequency Decrease in Breakdown Voltage Increase in Chip Density Increase in Dynamic Power ow Power Design Maintaining Performance ow Supply Voltage ow Threshold Voltage I sub = K e qvds kt High eakage Current e q( VGS VT +ηvds ) nkt Power Supply Gating eakage Reduction Techniques ow Threshold High Threshold + Huge reduction in leakage Virtual V dd SEEP - Modification in CMOS technology process P Gate Gate2 Gate3 - Reduced performance IN Virtual Ground N OUT Virtual Ground SEEP - Reduced DC noise margin -ess effective as technology scales down SEEP 2

3 eakage Reduction Techniques Dual and Variable Threshold Voltages Dual Threshold CMOS High-Threshold devices on non-critical paths ow-threshold devices on critical paths Variable Threshold CMOS (VTCMOS) Dynamically change the substrate voltage to control the leakage and speed Substrate voltage higher than V dd (for P transistors) Substrate voltage lower than ground (for N transistors) - Requires triple-well technology and additional power supply - Performance penalty (delay of retrieving the substrate voltage) - ess effective with the technology scaling down Sequential s Input Flip-Flops Present State ogic Next State Output Flip-Flops Internal Flip-Flops 3

4 Input Vector Control Primary Inputs Min-eakage Vector Min-eakage Input = ogic Min-eakage Input = input input input input input input input input Minimum eakage Vector Identification Original Primary Outputs Primary Inputs Internal Signals eakage Computing ogic eakage eakage evel < Search for the minimum leakage level for which the above Boolean network is satisfiable 4

5 Input Vector Control inear Search Algorithm for Minimum eakage Start C = Trivial Upper Bound on the leakage MV = {} C = C- Generate Boolean clauses corresponding to total_leakage < C If total_leakage < C then total_leakage < C Solve the resulting satisfiability problem Stop MV = satisfying vector Yes Satisfiable? No Minimum eakage = C+ Min-eakage Vector = MV Scan Based Testing Test Data Input Data Test Steps Test Signal Test = Apply n clocks and shift in the test vector 2 Test = Apply one clock and capture the circuit response 3 Test = Apply n clocks and shift out the response in Test Test Test ogic 5

6 Using the Scan Chain for eakage Reduction Memory (n-bit shift register) Scan Chain Shifting in the MV, from a memory (n bit shift register) into the n flipflops via the ScanIn pin by setting the circuit into the test mode and applying n clocks test test Modifying the Scan Chain mode: = = Minimum eakage Vector is applied to inputs of the combinational logic Operational mode: = = Inputs directly applied to combinational logic Multiplexers are not placed on the critical paths in 2 n ogic 6

7 Adding Extra Flip-Flops for State Recovery Originally MV is stored in left Flip-Flops While changing the mode from to operation and vice versa the content of flip-flops are swapped in mode: = = MV is applied (right s) State stored in left s Operational mode: = = Inputs directly applied to combinational logic MV stored in left s ogic Timing Diagram of Control and Clock Signals Clock Clock V V 2 7

8 Single atch Sequential C C ogic ogic C C C 2 C Scan Chain Structure for Single-atch Sequential s Additional multiplexers and latches are added Different phase of clock is used For additional latches In the test mode the original and additional latches make A test chain In the normal mode inputs are directly applied in C C C ogic 8

9 Adding Extra atches and Multiplexers for State Recovery Additional multiplexers and latches are added Originally MV stored at the latches on the left While changing the mode from to operation and vice versa the content of flip-flops are swapped In the normal mode inputs are directly applied C 3 C 3 C 3 in C C C ogic Timing Diagram of Control and Clock Signals Test C C 3 V 2 V V 3 9

10 State Recovery without Extra atches Additional multiplexers and no extra latches In the normal mode inputs are directly applied While switching to mode the previous is stored at extra latches and is applied to the circuit While switching back to the operational mode the previous is retrieved via the loop 2 n Wake Up Wake Up Wake Up in C C C ogic Experimental Results eakage Reduction eakage Reduction eakage Reduction eakage Reduction S96 26% S % S28 36% S5378 9% S238 25% S382 34% S27 39% S64 23% S423 9% S386 27% S298 35% S73 3% S488 3% S4 34% S344 33% S82 33% S494 32% S5 29% S349 3% S838 33% Minimum: 6% Maximum: 39% Average: 29%

11 Delay Overhead (Proposed versus Standard method) Delay Overhead Delay Overhead Standard Our Standard Our S96 % % S % % S238 9% % S382 4% 2% S423 4% % S386 5% 2% S488 2% % S4 3% % S494 % % S5 2% % S28 5% 4% S5378 % % S27 7% 5% S64 % % S298 3% 2% S73 9% % S344 2% % S82 2% % S349 3% % S838 3% % Average Delay for Standard method: 2% Average Delay for Proposed method: % Conclusion Finding the minimum leakage vector Modifying the scan chain Applying the min-leakage vector to the circuit using the scan chain Flip-Flop circuits Single latch circuits Significant leakage saving with negligible performance penalty