Logic Circuits. A gate is a circuit element that operates on a binary signal.

Transcription

1 Logic Circuits gate is a circuit element that operates on a binary signal. Logic operations typically have three methods of description:. Equation symbol 2. Truth table 3. Circuit symbol The binary levels in logic gates are called and. When levels refer to oolean expressions they are referred to as true and false. Logic levels are T=True and F=False. inary levels are =True and =False. When levels refer to electronic voltage levels they are called high and low. Logic levels are H=High and L=Low. inary levels are =High and =Low. of 2

2 oolean Logic oolean logic is based on the oolean algebra with two operations: ND and O. = bar over a variable or expression represents the inverse value. + = oolean algebra is commutative and distributive. = + = + ( + C) = ( ) + ( C) DeMorgan s theorem links negation and the operations. = + + = 2 of 2

3 Unary Operations - Input There are two unary operations. The identity operation leaves the value unchanged. Α Α in out The inverse operation reverses the value and is called NOT. Α Α in out 3 of 2

4 Transistor Gates single FET can form an identity,... +V DD ource uffer Follower v G If v G =, v = v G If v G = V DD,, v = v G... or an inverse. +V DD Common ource Inverter D v G If v G =, v D = V DD - v G = V DD If v G = V DD,, v D = V DD - v G = 4 of 2

5 5 of 2 inary Operations - 2 Inputs There are two basic binary operations. The ND operation acts like multiplication. The O operation acts like addition. + +

6 Compound Operations The combination of NOT and ND is NND. The combination of NOT and O is NO. + + Either NND or NO gates can be used to create other logic gates. ( ) ( ) = ( + ) + ( + ) = 6 of 2

7 Electronic NND The CMO implementation of a NND can be found in the 4. +V DD 2 V out 3 4 The CMO MOFETs are connected as switches. HIGH at and turn on 3 and 4 while turning off and 2. LOW at and turn on and 2 while turning off 3 and 4. If both 3 and 4 are on then V out is at ground, otherwise either or 2 will be on pulling V out up to V DD. 7 of 2

8 Exclusive O The exclusive or is a common comound gate. The XO selects inputs that differ. = ( + ) ( ) There are a number of equivalent logical constructions for XO. = ( ) + ( ) = ( ) ( ) 8 of 2

9 Logic Types There are two common types of logic gates: TTL - Transistor-Transistor Logic and CMO - Complementary Metal-Oxide-emiconductor. Properties of TTL vs. CMO Property TTL CMO Power upply 4.75 to 5.25 V 2 to 5 V Input Current LOW sources.5 m none (static charge may damage) Input Threshold.3 V.3 V DD to.5 V DD (except HCT) Output LOW -.2 V HIGH to 4.4 V LOW - V HIGH - V DD Power Consumption considerable minimal except at high frequency Other threshold sensitive to noise high output impednace (~ Ω) 9 of 2

10 Flip Flops flip-flop can be forced into one state or the other and hold it when some inputs change. The (et-eset) flip-flop is forced into one state or another with an input to ET or EET. Negative inputs are mean that the effect is active when the signal is low. ET EET The ET and EET cannot be used simultaneously or there is an ambiguous result. ET EET of 2

11 witch Debouncer mechanical switch will bounce on its contact and provide multiple pulses. kω +5 V flip-flop is sensitive to the first bounce, but none after until it is reset. +5 V kω kω of 2

12 Triggered Flip-Flops clock can be used to control which input is used. CLOCK The extra NND gates allow the CLOCK to control whether and make it to the flip-flop. If CLOCK= the inputs to the flip-flop are disabled and stays constant. If CLOCK= the inputs are active and samples and. disadvantage to the circuit is that if or change during the clock pulse, only the final state of the flip-flop is preserved when CLOCK= again. 2 of 2

13 D-Type Flip-Flop The D-type flip-flop is identical to a clocked flip-flop, except one input is inverted to form the other input. D CLOCK The truth table shows states where the circuit retains the previous value. CLK D With only one input the indeterminate state ( ==) is avoided. D can make many transistions while CLK =, only the last level is stored when CLK =. 3 of 2

14 Edge-Triggered Flip-Flops Preceding flip-flops were level-sensistive and and active when the clock level was correct. The master-slave flip-flop is an edge-sensitive trigger. This circuit consists of two level-sensitive D-type flip-flops. D CLK During CLK=, the first flip-flop is enabled, but the second is disabled (memory only). During CLK=, the first flip-flop is disabled, but the second is enabled, so it samples what ever is held at that time on flip-flop. The output can only change exactly as CLK goes from to. This is a negative edge trigger. 4 of 2

15 Flip-Flop Timing n edge-triggered flip-flop can be built from three flip flops CLK D The timing diagram shows the positive edge triggers in the statges. CLK D of 2

16 et and Clear Inputs Most edge-triggered flip-flops come with both set and clear options that work like and from an flip-flop. D If ET=, then is forced to, and to. If CLE= (EET), then is forced to, and to. ET and CLE take effect regardless of the state of CLK. D-type flip-flops also come with ET and CLE. 6 of 2

17 JK Flip-Flops The JK flip-flop uses 2-input combinatoric logic with feedback to set the D input of flip-flop. D = ( J K) J + J K + J K J K D When both J and K are low then the output remains as it was. When either J or K alone are high then the output matches the state of J. When both J and K are high then the output switches state. J K The JK flip-flop also comes with ET and CLE in a single chip. 7 of 2

18 Dividers divider uses the negative output to toggle the output at slower rate than the input. D-type flip-flop can easily become a divide by two circuit. CLK D CLK D is always set with, so at each rising edge switches. There is no confusion at the rising edge since there is a ns propagation delay through the flipflop (74HC74), and the output needs to be stable for only 3 ns. The JK flip-flop can use the internal toggle setting to become a divide by two circuit. +5 CLK +5 J K CLK 8 of 2

19 Multistage Divider Multiple divide by two circuits can be combined to form a divide by 2 n circuit. +5 J J J J CLK K K K K D D D 2 D 3 Each JK flip-flop is set to divide the clock by 2. D is dividing the input clock by 2. D is dividing the input clock by 4. D 2 is dividing the input clock by 8. D 3 is dividing the input clock by 6. This can be extended to any arbitrary length. 9 of 2

20 Divide by 6 Truth Table C L K D D D 2 D 3 Count of 2