A Reconfigurable, Radiation Tolerant Flexible Communication Platform (FCP) S-Band Radio for Variable Orbit Space Use

Transcription

1 A Reconfigurable, Radiation Tolerant Flexible Communication Platform (FCP) S-Band Radio for Variable Orbit Space Use Michael Epperly Christopher Sauer, John Dickinson Southwest Research Institute 6220 Culebra Rd San Antonio, TX

2 Introduction Trend in spacecraft development has been away from the big flagship missions towards lower-cost, shorterdevelopment cycle spacecraft ORS CubeSats SwRI was preparing a NSF proposal for a CubeSat Mission called CHIME Imager for Coronal Mass Ejections for solar storm prediction Mission required S-band downlink

3 Introduction A critical need is evident for a flexible space transceiver, supporting multiple mission profiles and environments Current lead times on S-Band transceivers in excess of one year Do not provide any capabilities for rapid reconfiguration Southwest Research Institute initiated a R&D effort to design and develop the architecture for a reconfigurable, radiation tolerant, communication system To address the needs of a low-cost, quick turn spacecraft To ensure the high reliability and connectivity in harsh radiation environments that is characteristic of higher orbit systems.

4 Critical Elements of IR Radiation performance of RF components Support both LEO and MEO missions with part selection Identification and implementation of appropriate hardening and mitigation strategies Guaranteeing the performance of the system in a MEO radiation environment with perfomrance suitable for a mission critical application Support of multiple mission profiles Low to medium cost (depending on part selection) Rapid deployment Modular mechanical and electrical interfaces

5 Design Approach A single circuit board approach within the CubeSat 1U slice. The RF electronics populate one side RF Interface Unit (RFIU) The digital processing electronics populate opposite side Digital Processing Unit (DPU) To Antenna To SpW Router RF RF In Switch Matrix SDR Slice RF Front End RF Front End Down-Conversion Stage Up-Conversion Stage Digital Controller & Signal Processor I/Q SpW Interface RF Out Host GPS Host CLK REF System Controller/ Memory SDR I/Q Uplink / Downlink Processing To SpW Router SpW Interface Level Zero Format Memory Uplink Processing Downlink Formatting & Level Zero Collection

6 Design Approach SDR Communicates with spacecraft via SpaceWire (SpW) Also provides UART and simple sync-serial interfaces Integrates SDR with Uplink/Downlink Processing Combines RF system with command and telemetry processing Creates CCSDS V1 Source Packets and VCDUs Performs CCSDS COP-0 uplink processing Two interfaces to RF Integrated programmable RF front end Separate Rad-hard ADC and DAC for MEO

7 RFIU Block Diagram 14-6 dbm to -56 dbm -1 dbm to -51 dbm +4 dbm to -46 dbm ADC +15 dbm (2.6 V P-P square) Max -60 dbm sensitivity LPF BPF +6 dbm to -44 dbm LNA -40 dbm to -90 dbm Σ PLL LPF PLL LPF Σ 14 DAC -2 dbm Max LPF +2 dbm -5 dbm BPF -7 dbm PA +33 dbm

8 RFIU The primary target for the FCP is the S-BAND frequency range Receiver Output Frequency: Fixed 2200 to 2300 MHz Dynamic Range: 50 to -119 dbm Noise Figure: 5 db maximum Input VSWR: 1.5:1, 50 ohms Acq Tracking Range: ± 160 khz Modulation: FSK Command Data Rate:2 to 64 Kbps Command Threshold (10-7 BER): -110 dbm (max) Uplink rates up to 128Kbps CCSDS COP 0 BCH Error Detect/Correct Autonomous Command Execution independent of FSW 16 Low Level Discrete Output Pulses System Reset Transmitter Output Frequency: Fixed 2200 to 2300 MHz Output VSWR: 1.5:1, 50 ohms Phase Noise: 2 RMS (max) Modulation: BPSK, OQPSK Downlink rates up to 3Mbps Hardware based CADU formatting Autonomous Level 0 Telemetry Collection Viterbi Encoding

9 DPU Virtex-4 Ideal for rapid deployment of DSPbased designs Actel based external scrubber Prototype uses commercial parts Flight devices ID d LVDS via 25-pin Micro-D SpW interface Low-jitter 80Mhz osc.

10 FPGA SEU Mitigation Strategy Re-configurability of SRAM-based FPGA devices is the cornerstone of Software Defined Radio technology Virtex-4* and similar programmable logic devices aresusceptible to radiation effects SEU s, SET s, SEFI s Primary options: (from XAPP 987): Mitigation Technique Description Power Cycling Configuration Memory Scrubbing Triple Modular Redundancy (TMR) Redundant Devices Device is power-cycled, and its contents refreshed. Accumulated errors in the configuration memory and user logic are removed. Configuration memory is continuously re-written with correct data by external or internal logic to detect and correct SEUs in the configuration bitstream. Prevents design alterations caused by SEUs, but not functional errors. Design elements are triplicated and implemented in a voting scheme. Helps mitigate SEU impacts on the user logic. Design duplicated on multiple devices, with an external voting scheme applied on the output(s). The most effective of the mitigation techniques listed, but also the most complex & costly to implement. (**Refer to LA-UR Quinn, Heather. Presented at MAPLD 2009)

11 Mitigation Strategy For DPU, SwRI chose a combination of CM scrubbing and TMR An external scrubber was chosen Superior radiation performance* Based upon XAPP 1088 and reference design Implemented in an Actel SX32. Flight device is RT-SX32. Via SelectMAP interface Readback & scrubbing repair SEE s in the configuraton memory Prevents SEU s from accumulating Operation is not interrupted, unless SEFI s detected Avoid Block RAM configuration columns *Berg, Melanie, et al. Effectiveness of Internal vs. External SEU Scrubbing Mitigation Strategies in a Xilinx FPGA: Design, Test, and Analysis RADEC 2007 Conference Proceedings, pp

12 Mitigation Strategy Scrubber flowchart from Xilinx Application Note 1088: Power up Done=0 Pulse PROG Init=1 Load FPGA Config Data Done=1 FAIL SEFI Check Done=0 Active Partial Reconfig

13 Mitigation Strategy Current design uses Xilinx TMRTool Clock, Reset input signals are triplicated Global signals particularly critical All other inputs are registered, then triplicated Triplicated outputs converge internally before the IOB Register packed in IOB Improves timing performance Slight susceptibility to SEU/SET remains *Figure from Xilinx UG156

14 Mitigation Strategy Other possible TMR tools Mentor Precision RT Safe FSM utility Hamming Distance-3 Configurable TMR Global, Distributed, Local topographies Does not currently provide ability for selective triplication of I/O s. Clocks, resets BL-TMR (BYU) Partial TMR Searches for feedback structures Resource constrained designs

15 FPGA Design The Top-level Controller Core officiates the entire operation of FPGA. Register based Communicates directly with the SpW core Optionally apply Viterbi encoding to downlink data 2 UART ports UART0: Tx/Rx data UART1: control and configuration data. Modulator Core Performs OQPSK modulation & up-conversion of the Tx data Demodulator Core Performs down-conversion and FSK demodulation

16 Communications Modeling complete Communication modulator and demodulator algorithms were prototyped in Matlab for OQPSK and FSK signals with the following characteristics: FSK Bit Rate 2-64 kbps Frequency Shift 10 khz Intermediate Frequency 5 MHz Sampling Rate 80 MSa/s OQPSK Symbol Rate 1.5 MSym/s, Bit Rate 3 Mbps Intermediate Frequency 5 MHz Sampling Rate 60 MSa/s

17 Assembled Board

18 FCP in Lab Checkout

19 Status Prototype system built and in test Focus of testing is on optimizing the power consumption with a goal of 3.5W (without external power amplifier) Completed IF testing of OQPSK transmit Working on S-Band OQPSK transmit. Purchased sat modem for EGSE Configured for testing (IF) FSK receive testing is in process (at IF) Second IR&D effort to extend effort Goal is to verify the RF flexibility of reconfigurable RF front end Test will quickly reconfigure unit for GPS L1/L2 reception via software reconfiguration of the flexible RF front end We are looking for a ride

20 Questions