ASTRIX ASIC Microelectronics Presentation Days

Transcription

1 ASTRIX ASIC Microelectronics Presentation Days ESTEC, Noordwijk, 4 th and 5 th February 2004 Matthieu Dollon matthieu.dollon@astrium.eads.net Franck Koebel franck.koebel@astrium.eads.net Page 1 - ESA 4 th /5 th February 2004

2 Content 1. ASTRIX Product Description 2. ASTRIX ASIC Description Context and development plan Technical definition 3. ASTRIX Validation environment Demonstrator board (FEM) Xilinx board 4. Conclusion Page 2 - ESA 4 th /5 th February 2004

3 ASTRIX Product description The astrix product family is developed under ESA and CNES fundings, through Planck, Pleiades and Alphabus programs. Astrium willingness is to develop 3 astrix products able to fit LEO observation, LEO science and GEO Telecom applications, and thus, sharing the same core component: the Astrix ASIC. A dedicated «astrix product applicable documentation» has been set up for the astrix development Page 3 - ESA 4 th /5 th February 2004

4 ASTRIX Inertial Measurement Unit Each Astrix IMU is the assembly of independent gyroscopic channels Each Astrix channel consists in: Gyro Optical Harness (GOH) Fog Electronics Module (FEM): Inertial processing Optical source Power interface TM/TC interface Sagnac Interferometer Assembly (SIA) = Inertial Sensor One astrix gyroscopic channel Page 4 - ESA 4 th /5 th February 2004

5 ASTRIX Channel Functional Module Optical source Optical coupler SIA COI Optical fiber Optical detector Detection Electronic Module Processing functions Modulation Module DC/DC Converter ASIC Servitude functions Power bus Interface 1553 bus Interface Serial data Interface Stimuli Interface FEM Power buses N & R Ext synchro N & R 1553 buses N & R Serial data buses N & R Stimuli N Page 5 - ESA 4 th /5 th February 2004

6 ASTRIX ASIC Introduction Astrium and IXSEA realize the ASTRIX ASIC: ASIC for Fiber Optical Gyrometer (FOG) application Two main entities are designed: Control part corresponds to the management of servitude functions Inertial processing part corresponds to the management of gyrometer functions Page 6 - ESA 4 th /5 th February 2004

7 ASIC Technology The MG2RT technology from ATMEL is the target chosen for the ASIC The Nantes factory is the baseline. MG2RT265E is the chosen matrix, 55% gates used. ASIC packaging: MQFPF256, 256 pins 5V single voltage Page 7 - ESA 4 th /5 th February 2004

8 Context of the ASIC The process followed to design the ASIC is adapted from the official ESA ASIC development since: Two companies are involved There are confidentiality issues that restrict the content of IXSEA reports Development plan takes this into account Page 8 - ESA 4 th /5 th February 2004

9 Development plan (1) ASTRIUM IXSEA A ASIC VHDL Testbench Servitude VHDL testbench No Inertial processing test ASIC VHDL model Servitude VHDL model without In. Proc. In. Proc. as empty box Inertial processing VHDL model Inertial Processing Testbench No servitude testbench Inertial processing and optic model testbench Servitude VHDL RTL simulation In. Proc. VHDL RTL simulation FPGA synthesis B ASIC VHDL Testbench Servitude VHDL testbench Reference vectors for In. Proc. ASIC VHDL model Servitude VHDL model without In. Proc. In. Proc. as compiled RTL model 1 RTL compilation In. Proc. as Xilinx netlist In. Proc. FPGA Verification ASIC VHDL RTL simulation Step A: Each company realizes a RTL verification of its block. IXSEA validates its design on a dedicated board. Step B: ASTRIUM starts the verification of the whole ASIC. Page 9 - ESA 4 th /5 th February 2004

10 Development plan (2) ASTRIUM IXSEA Step C: Each company realizes a validation of its block with the whole ASIC as Xilinx netlist on 4 DM boards. C ASIC VHDL Testbench Servitude VHDL testbench Reference vectors for In. Proc. VHDL gate FPGA simulation ASIC VHDL model Servitude VHDL model without In. Proc. In. Proc. as FPGA netlist FPGA synthesis ASTRIX ASIC as Xilinx netlist 2 FPGA verification Inertial processing VHDL model FPGA synthesis Step D: ASTRIUM realizes the ASIC gate level design. ASIC VHDL model Servitude VHDL model without In. Proc. In. Proc. as VHDL model 3 D ASIC VHDL Testbench Servitude VHDL testbench Reference vectors for In. Proc. ASIC synthesis ASTRIX ASIC as ATMEL netlist Page 10 - ESA 4 th /5 th February 2004 VHDL gate ASIC simulation

11 ASIC functional description Control section shall interface with: Analog TM External synchronization links 1553 interface Serial interface Stimuli link 1553 and gyro clock Configuration Inertial processing section: Fog loop Anti aliasing filters Digital source power control Interface with: Detection module Modulation module Source module Page 11 - ESA 4 th /5 th February 2004

12 ASIC Control block Control section shall interface with: Analog TM periodically refreshed External synchronization link (redundant) Stimuli link: UART in reception mode only Data links: 1553 redundant buses with TM/TC specific characterization Two redundant UART at Kbaud Configuration Dating 1553 and gyro clock Page 12 - ESA 4 th /5 th February 2004

13 ASIC Inertial processing block Fiber optical gyrometer loop Several configurations Several frequencies possible Anti aliasing filtering Several configurations Digital source power control Direct command Reference point driven Status information BoardTest for debugging and production tests Page 13 - ESA 4 th /5 th February 2004

14 ASTRIX Validation environment PC Communication and test links on ASTRIX board MIL-1553B RS-422 D2a D2b Power Supply for ASTRIX(TM) G = D1 ASTRIX (TM) - Xilinx system ASTRIX Xilinx metallic socket Optical system (by IXSEA) D9 Parallel JTAG/Serial Programming Cable for Xilinx board (by XILINX or 3rd party) D5 PC Programming Software external synchronize signal generator TTL-RS422 converter D6 D3 D4 Debugging cables and switches on HE10-20 on Xilinx board (by IXSEA) Measurement equippement (scope, multimeter or analyser) on connectors HE10-20 on Xilinx board D8 D7 Page 14 - ESA 4 th /5 th February 2004

15 Page 15 - ESA 4 th /5 th February 2004 ASTRIX Demonstrator board

16 ASTRIX Xilinx board (1) ASIC FOOTPRINT QFP 256 Adaptor QFP256 to PINS FLEX 256 wires from ASIC I/Os 5Volt 5Volt from ASIC footprint external power supply for test purposes Regulators Optical power indicators 5V 3.3V Astrix/FOG board Resistors Buffers 2.5V RT address configuration by 1553 connector Oscillator 3.3V 16Mhz I/Os 3.3Volt connectors HE10-20 to observe dynamic signals PULL DOWNs for SODATA while FPGA-programming Oscillator 5V GYRO 16 Data 2 Clocks Xilinx board DIP Switches for ASTRIX configuration Clock 3.3/5 Volt I/Os 3.3Volt PROMs or JTAG Direct serial Programming Programming 64 I/Os (3.3Volt) on HE10-20 connectors for DEBUG purposes 1553 RT address test points XCV1000 BGA560-I Reserved I/Os 3.3Volt PRG Mode FPGA Page 16 - ESA 4 th /5 th February 2004

17 Page 17 - ESA 4 th /5 th February 2004 ASTRIX Xilinx board (2)

18 Conclusion Architectural design finished First integration at simulation level successful ASTRIX and Xilinx boards manufactured Integration of the two entities at board level is in progress this week ASIC VHDL will be verified on these boards Page 18 - ESA 4 th /5 th February 2004