Making the circular self-test path technique effective for real circuits

Transcription

1 See discussions, stats, and author profiles for this publication at: Making the circular self-test path technique effective for real circuits Conference Paper in IEEE International Test Conference (TC) November 1994 DOI: /TEST Source: IEEE Xplore CITATIONS 10 READS 26 3 authors: Fulvio Corno Politecnico di Torino 308 PUBLICATIONS 2,852 CITATIONS Paolo Prinetto Politecnico di Torino 383 PUBLICATIONS 2,518 CITATIONS SEE PROFILE SEE PROFILE Matteo Sonza Reorda Politecnico di Torino 525 PUBLICATIONS 5,407 CITATIONS SEE PROFILE Available from: Paolo Prinetto Retrieved on: 13 May 2016

2 Making the Circular Self-Test Path Technique Effective for Real Circuits F. Corno, P. Prinetto, M. Sonza Reorda Politecnico di Torino Dipartimento di Automatica e Informatica Torino, Italy Abstract * The paper assesses the effectiveness of the Circular Self-Test Path BIST technique from an experimental point of view and proposes an algorithm to overcome the low fault coverage that often arises when real circuits are examined. Several fault simulation experiments have been performed on the ISCAS89 benchmark set, as well as on a set of industrial circuits: in contrast to the theoretical analysis proposed in [PKKa92], a very high Fault Coverage is attained with a limited number of clock cycles, but this happens only when the circuit does not enter a loop. This danger can not be avoided even if clever strategies for Flip-Flops ordering, aimed at reducing the functional adjacency, are adopted. Instead, we suggest that loops can be avoided and fault coverage increased by carefully choosing the initial state, and we present an approach based on Binary Decision Diagrams and Symbolic Techniques to solve the problem. 1. Introduction BIST techniques are nowadays widely used for testing both whole devices and embedded portions like ROMs, RAMs, combinational chunks of logic, and FSMs. A BIST approach to sequential circuits testing has been proposed and deeply analyzed from a theoretical point of view in [PiKr89] and [PKKa92]. The approach, named Circular Self-Test Path (CSTP), is based on substituting all the Flip-Flops in the circuit with special cells, which are then connected to constitute a circular chain. In [POLB88] some experimental results are presented, which partially support the conclusions drawn in [PiKr89]. In the same paper, several heuristics are proposed to effectively implement a par- * This work has been partially supported by the ESPRIT BRA 6575 ATSEC and by the MURST 40% project Affidabilità e Diagnostica in Elettronica. Contact address: Paolo Prinetto, Dipartimento di Automatica e Informatica, Politecnico di Torino, Corso Duca degli Abruzzi 24, I Torino (Italy), Paolo.Prinetto@polito.it tial BIST approach with lower cost in terms of hardware overhead. A similar approach is described in [Stro88], where a slightly different cell is introduced to provide the possibility of performing additional operations such as connecting cells as a shift register or a feed-back register, or resetting Flip-Flops. Recently, special hardware modifications have been proposed in [AvMc93] to improve the success of BIST when applied to sequential circuits. An attracting point of CSTP is the ease of conversion of an existing circuit, and the test session not needing any higher level test protocol. [Gage93] reports an application of CSTP in an industrial environment. The main goal of this paper is to make CSTP applicable to test real synchronous sequential circuits. The problem has got a critical importance as a consequence of the wide popularity of synthesis tools in IC designs. The presence of deeply embedded FSMs of increasing size makes test pattern generation even harder. On the other side, most BIST techniques either involve high hardware overhead, as in the case of BILBO [KMZw79], or still have not been proven to be fully reliable, as for the CSTP technique. As a preliminary step, an evaluation is made, from an experimental point of view, to quantify how well the statistical conclusions drawn in [PiKr89] and [PKKa92] are verified. A critical problem is identified, namely the low state coverage due to the circuit entering a loop, which is different from the ones proposed in the literature, and a technique to overcome it is presented. The here presented results demonstrate that some of the conclusions of the analysis of [PiKr89] and [PKKa92] are not applicable to real circuits, that often contradict some assumptions at the basis of the analysis. The main problem appears to be the risk that the circuit reaches an already visited state, thus greatly limiting the number of different values generated on the inputs of the combinational part. In order to evaluate how to reduce this risk, a heuristic algorithm for ordering (and possibly inserting) Flip-Flops has been experimented, whose goal is to reduce the functional

3 Primary Inputs Combinational Logic Primary Outputs Combinational Logic a) Original Circuit b) CSTP Circuit in Test Mode Figure 1: CSTP modification technique adjacency between consecutive Flip-Flops in the chain. As the effectiveness of Flip-Flop ordering appeared to be poor, it is essential to cleverly chose the initial state of the Flip-Flops. Symbolic traversal techniques derived from formal verification are shown to fulfill this goal. Section 2 describes in greater details how the CSTP approach works; Section 3 evaluates the effects of ordering the CSTP cells, and Section 4 presents a solution for finding the optimum initial state. Some conclusions are drawn in Section CSTP The Circular Self-Test Path approach is based on adding a special cell (hereinafter denoted as CSTP cell) to every Primary Input (PI) and Primary Output (PO) of the circuit (Input and Output Flip-Flops) and transforming the existing Flip-Flops (State Flip-Flops) into CSTP cells (Figure 1). A sample CSTP cell is shown in Figure 2. It is fully transparent during normal operations, and transforms each Flip-Flop into an element of a Feed-back Shift Register while in Test Mode. In this case, the feed-back value comes from one output of the combinational logic, which in turn is fed by the output of the cell when State Flip-Flops are considered. The EXOR gate is omitted in Input Flip-Flop cells. During the Test Phase, a scan chain is thus created, connecting all the Flip-Flops in the circuit: the chain acts as a non linear feedback shift-register, due to the fact that the State and Output Flip-Flops are fed with the EXOR of the values coming from the preceding Flip-Flop in the chain and from the combinational part of the circuit. The chain thus simultaneously performs the tasks of generating patterns for the combinational part and compressing the corresponding outputs. In other words, it acts both as a Generator and a Compressor. At the end of the test session, the values in the chain constitute the signature of the circuit, and can be scanned-out to detect possible faults. Provided that patterns are randomly generated and compression is prone of aliasing effects, the solution is effective in terms of both hardware overhead and performance speed. A different CSTP cell has been proposed in [Stro88], which allows four different operations to be performed: normal operation, reset, shift, and exor between the preceeding cell s value and the data input. In order to better understand how well the scan chain performs the two tasks during a test session lasting for T clock cycles, the following parameters are significant: The number D of different states reached by the circuit, where a state is a value assumed by the Flip-Flops in the CSTP circuit; in the best case,

4 the circuit reaches a new state at each clock cycle. On the opposite, if at a given time, the circuit s state is equal to a previously reached one, then the circuit enters a loop, and the number of reached states (as well as the Fault Coverage) remains unchanged no matter the test length. The number A of activated faults, where a fault is defined as activated if it caused a value different from the good one on at least one Flip-Flop during at least one clock cycle. Due to the aliasing effect typical of compressors implemented as feed-back shift registers, A is always greater (or equal) than the number F D of faults detected at the end of the test phase. Comparing these quantities to the number of faults in the fault list, F, one obtains the aliasing-free fault coverage A / F and the attained fault coverage FC = F D / F. From the previous cell From the logic Normal/Test S MPX D D-type Flip-Flop Clock Q To the logic Figure 2: CSTP cell for the State Flip-Flops To the following cell In [KrPi89], several Observations are stated, which probabilistically define the performance of the CSTP approach. They guarantee that adopting a test running time a few times longer than the exhaustive one, the state coverage becomes independent of the initial state of the circular path. Moreover, any possible correlation between the lines feeding the path elements does not affect the state coverage; therefore, the ordering of Flip-Flops inside the path becomes negligible. In [PKKa92] the authors provided the following formula, which is able to predict the Expected Fault Coverage (EFC) of CSTP in terms of the topological parameters of the circuit: T P k+ 2 S EFC = 1 e 1 ( 1 2 ), where T is the length of the Test Sequence, P is the number of Flip-Flops in the circular path, k is the number of inputs of the combinational logic, and S is the signature length. If all the Flip-Flops in the chain are scanned-out at the end of the test session, then S = P. From the formula above, one can deduce that an acceptable fault coverage can be reached only when the number T of clock cycles is at least comparable with 2 k+1. Otherwise, the Expected Fault Coverage is very low. The above results have been obtained under the hypothesis that the configurations assumed by the Flip- Flops in the chain are equally likely and independent. Unfortunately, this assumption is never verified, as it is clear that, given an ordering of the Flip-Flops in the chain, and an initial state, each state is either reachable (with probability one), or unreachable. In other words, the probabilistic approach loses any practical meaning when considering the behavior of CSTP circuits. In order to experimentally confirm the last statement, we transformed some circuits according to the CSTP technique and performed a set of fault simulation experiments aimed at evaluating the real correctness of the above observations and formulæ. Two sets of circuits have been considered: the former is composed of the ISCAS89 circuits [BBKo89], the latter of several circuits coming from ITALTEL, the Italian Telecom Company (their characteristics are summarized in Table 1). Circuit #PIs #POs #gates #s FSM FSM FSM FSM Table 1: ITALTEL circuits For each CSTP circuit the final Fault Coverage (FC), the number of reached states D, and the percentage A/F of activated faults have been computed; all the experiments have been performed starting from the all-0s state, and last for T clock cycles; the circular path is composed by all the Input, Output and State Flip-Flops, in that order. The results for T = 5,000 are reported in Table 2. As far as the results in Table 2 are considered, several facts are worth to be noticed: The final Fault Coverage FC is influenced by the number of reached states much largely than by the Aliasing phenomenon. This is particularly critical for some circuits (shown in bold face), where D<<T because the circuit enters a loop: in these cases, the number of reached states, and

5 therefore the Fault Coverage, remain the same no matter the test length T. When a loop is not entered, then D equals T, and the Fault Coverage grows up to a value that is quite high, already after some hundreds of patterns. The growth becomes then always slower, as shown in Figure 3, which reports the Fault Coverage with respect to the number of clock cycles for the circuit S713. Several faults in the CSTP cell (e.g., the ones on the line selecting the operating mode) are not testable when the circuit is in the Test Mode. These faults can be easily covered with a short functional test to be performed while the circuit is in Normal Mode. The ratio of detected faults with respect to the number of faults that can be detected during the test phase is reported in column TFC (Testable Fault Coverage) of Table 2. Values very close to 100% are obtained in many cases, showing that a very good result can often be reached after a limited number of clock cycles. Circuit T D A/F FC TFC FSM2 5, FSM3 5, FSM4 5,000 5, FSM6 5, S208 5, S298 5,000 2, S344 5, S349 5,000 2, S382 5,000 5, S400 5,000 5, S420 5, S510 5, S526 5,000 5, S641 5,000 5, S713 5,000 5, S838 5,000 5, S1196 5,000 5, S1238 5,000 5, Ave Table 2: CSTP performance As a conclusion, the experiments show that the real problem when using the CSTP technique is how to avoid that the circuit enters a loop. Fault Coverage # of clock cycles Figure 3: Fault Coverage vs. # of clock cycles for the CSTP version of the S713 circuit Two possible solutions have been devised to tackle such a problem: ordering the Flip-Flops and finding the optimum Initial State. The two topics will be analyzed in the following Sections. 3. Flip-Flop Ordering When evaluating the CSTP technique, one immediately realizes that the approach is effective unless adjacent Flip-Flops in the chain are functionally dependent: in the worst case (unit-distance register adjacency), the functional input of one Flip-Flop directly depends on the output of the preceding one, and its input in Test Mode is thus stuck at a fixed value. This phenomenon prevents the value in one Flip-Flop to be transferred into the next one, thus breaking the chain. Not only the compaction capabilities of the chain are thus greatly reduced, but also its aptitude to generate random patterns significantly decreases. Three remedies can be adopted for this problem: finding a clever ordering of Flip-Flops in the chain, to avoid physical adjacency between functional dependent Flip-Flops; introducing dummy Flip-Flops, so that no functionally dependent Flip-Flops are adjacent in the chain; using a special CSTP cell, to eliminate the effects of functional dependency [AvMc93]. The first two solutions require determining the functional dependencies among Flip-Flops. This can be achieved resorting to the so called Dependency Graph, where vertices represent Flip-Flops, and an edge from vertex v i to vertex v j means that Flip-Flop j does not depend on Flip-Flop i. A similar data structure is de-

6 scribed in [AvMc93]. Note that the vertices corresponding to Input Flip-Flops have an edge coming from every vertex, and vertices corresponding to Output Flip-Flops have edges going to every other vertex. The dependency problem can be completely solved if a Hamiltonian Cycle (i.e., a cycle composed by all the vertices in the graph) is found in the Dependency Graph. If such a cycle does not exist, or the task is too heavy to be solved in an acceptable time, approximate solutions must be found. One possible greedy solution is described by the pseudo-code in Figure 4. When an ordering which avoids functional adjacencies cannot be found, the procedure automatically inserts dummy Flip-Flops. The Flip-Flops in the path have been ordered according to the described algorithm and a new set of fault simulation experiments has then been performed on the modified circuits; the results have been reported in Table 3. The following remarks can be made about the results of Table 3: among the 6 circuits which entered a loop with the first Flip-Flop ordering, two (S344 and S349) now correctly evolve through the whole sequence of 5,000 clock cycles without any state repetition; the other 5 (FSM2, FSM3, FSM6, S208 and S510) still enter a loop, while the number of reached states (and the Fault Coverage) changes. Unfortunately, three additional circuits (FSM4, S420, S510 and S838) now enter a loop; the average Fault Coverage decreases. As a conclusion, a Flip-Flop ordering to minimize the adjacency within the chain can be useful in some cases, but not in general. To confirm the last sentence, a further experiment has been done: the adjacency graph for circuit FSM2, was built and a Hamiltonian Path was found. Flip- Flops have been ordered accordingly, and the resulting circuit has been fault simulated: despite the fact that the ordering was the optimum one according to the functional dependency criterion, the circuit still entered a loop, and the Fault Coverage remained roughly the same. This is due to the fact that, although eliminating functional adjacency definitely increases the ability of the chain to generate random patterns and to compress the circuit responses, it has no influence on the fact that the circuit enters a loop. Moreover, the experimental results we presented show that the presence of a loop can cause the Fault Coverage to remain extremely low. Circuit T D A/F FC TFC dummy s FSM2 5, FSM3 5, FSM4 5, FSM6 5, S208 5, S298 5,000 5, S344 5,000 5, S349 5,000 5, S382 5,000 5, S400 5,000 5, S420 5, S510 5, S526 5,000 5, S641 5,000 5, S713 5,000 5, S838 5, S1196 5,000 5, S1238 5,000 5, Ave Table 3: Behavior of the CSTP technique with Flip-Flops ordering A Fault Simulation phase thus seems to be required in order to guarantee that the circuit does not enter a loop once the Flip-Flops order and the initial state are given. Special kinds of Fault Simulators (like the one described in [GMSR94]) can be used to perform such as computationally heavy task. An alternative solution for finding the optimum initial state is proposed in next Section. 4. Optimum Initial State Computation As shown in the previous sections, attaining a reasonable fault coverage is mainly determined by the effective length of the applied test pattern before the good circuit enters a loop. The fault simulation experiments we conducted show that neither an optimal Flip-Flop ordering nor the insertion of additional Flip- Flops is able to guarantee that a loop is not entered. The only possibility for enhancing fault coverage is therefore a clever choice of the initial state.

7 select a vertex i corresponding to an Input Flip-Flop; mark i; while there are unmarked vertices do { compute the set A of the unmarked vertices reachable from i; if A is empty add a dummy Flip-Flop k; else { select from A the vertex k with the min. number of incoming edges ; mark k; } i=k; } Figure 4: Pseudo-Code for the Greedy Procedure finding an optimal Flip-Flop ordering Given a promising initial state, it can be forced into the circular path in two ways, with negligible overhead in terms of area and test length: by scanning-in the corresponding value through the path; by simply resetting or presetting each Flip-Flop, provided that individual Reset and Preset signal are available for each Flip-Flop. Being the circuits to be tested synchronous, it is possible to exploit some of the recent advancements in the area of formal verification of Finite State Machines: symbolic techniques can be used to build and explore the State Graph of circuit in Test Mode. The validity of the algorithms is ensured by the following assumption, whose validity stems from the experimental analysis of the previous sections: the fault coverage of a circuit in a CSTP test session is directly related to its state coverage, i.e., to the number of different states that have been visited. Under this assumption, the symbolic algorithm aims at finding a reset state that guarantees a maximal state coverage. The problem reduces to finding the longest acyclic path in the state transition graph: the first state of that path will be chosen as the starting state during the test session. Peculiar properties of the state transition graph are exploited in order to devise an efficient algorithm. Since during test mode the evolution of a BIST circuit does not depend on any primary input value, each state has a single successor. Consequently, the sequence of states visited by the circuit has the structure shown in Figure 5. Each node in the graph represents a state of the circuit in test mode. The number of such states, taking into account the Flip-Flops in the scan cells, amounts to 2 #+#PI+#PO. States can be classified according to their position in the state transition graph: head states (dotted in figure 5, see s 0 ) are states that have no incoming transition; loop states are states belonging to some cycle of length greater than one of the graph (s 0, s 1 ); transition states (shown in thick line) are states which have at least one predecessor and do not belong to any cycle; sink states, i.e., self loops (s 2 ). A first analysis shows that good candidates as starting states are the head states. For the benchmarks at our disposal, the number of head nodes turned out to be considerable (Table 4), thus forcing us to develop highly sophisticated algorithms to deal with all of them. The behavior of the circuit starting from a head statesooner or later converges to a loop: each loop identifies a connected component in the graph, composed by the loop itself, by all the head states that converge to that loop, and by all the transition states that are visited starting from the mentioned head states. Of course, there can be some loop with no associated head node, i.e., the loop is a connected component of the graph by itself. Experimentally, we found the number of connected components to be very small (Table 4). The optimal starting state is found by maximizing the quantity length of the loop + number of transition states leading from a head state to a loop state. To solve the problem, symbolic manipulation techniques based on binary decision diagrams (BDDs) [Brya86] have been used. The exact solution proved to

8 be difficult to obtain with both traditional graph-theory algorithms [Gibb85], due to the number of total states and head states, and symbolic ones [CHJP90] [CoMa90], due to the augmented number of Flip-Flops and the EXOR gates, which reduce the regularity of the circuit. Thus, a mixed approach is adopted, where BDD computations implicitly manipulating sets of states are interleaved with traditional graph traversal algorithms, where each state is considered at a time. Circuit Head states States Loops FSM FSM4 1,409,024 8,388,608 8 FSM ,096 5 S S ,792 2,097,152 8 S298 2,498,560 8,388, Table 4: Topology of the graphs s 2 s 0 s 0 s 1 Figure 5: Typical state transition graph The algorithm considers one connected component at a time. For each connected component, the loop identifying it is first found. Then, starting from the loop and backward traversing the state graph with a symbolic breadth-first technique, all the head states are implicitly enumerated. The last head state found during the traversal is the one which guarantees the maximum test length for that connected component. Computations (Figure 6) proceed as follows: the boolean function f for the normal mode behavior is extracted from the unmodified netlist: ( t+1, PO ) = f ( t, PI ) ; the function is manipulated, building f CSTP, the one corresponding to the CSTP circuit: ( t+1, PO t+1, PI t+1 ) = = f CSTP ( t, PO t, PI t ) = = (f( t, PI ), 0) rotate( t, PO t, PI t ); the corresponding graph is symbolically traversed, considering one connected component at a time. For each connected component: a head node is selected, the corresponding loop is identified by forward traversing the graph by means of symbolic simulation, a backward-time exploration is started from the nodes composing the loop to obtain all the states in the same component. As a byproduct, one obtains the maximum acyclic path in that component. Table 5 reports for some benckmarks the number of reached states and corresponding fault coverages when starting from different initial states. Columns m 0 and FC(m 0 ) are computed with the same circuit configuration that was used in Table 2, i.e., when the Test Session is started from the all-0 state. For the subset of circuits where fault coverage is too low (shown in bold face), the symbolic algorithm was run, that computed the maximum and minimum number of states that can be reached when starting from different initial states. Due to the presence of some sink states, the minimum number of states is always 1, while the maximum one is reported in column M. Where a satisfactory fault coverage was found before the entire state graph was explored, the best found result is reported, instead of the optimum one, and is marked with the sign. Reported data, which were collected on a Sun SparcStation 2 with 32 Mbytes in less than 3 hours of CPU, show that the approach proposed in this Section is able to significantly improve the fault coverage of a CSTP circuit by avoiding premature repetition of already visited states. These results prove to be a more effective alternative to Flip-Flop ordering strategies.

9 compute the state transition function f CSTP ; HeadStates = BDD_NOT( BDD_IMAGE( f CSTP, BDD_ONE ) ) ; /* compute the head states as the states that are not the next */ /* state of any starting state */ While( HeadStates!= BDD_ZERO ) { StartState = BDD_SELECT_ONE( HeadStates ) ; /* select a head state */ TheLoop = simulate_until_a_loop_is_found( fcstp, StartState ) ; CurrentStates = TheLoop ; TestLength = BDD_COUNT_ONSET( TheLoop ) ; While( CurrentStates!= BDD_ZERO ) { PreviousStates = CurrentStates ; CurrentStates = BDD_PRE_IMAGE( fcstp, CurrentStates ) ; HeadStates = BDD_AND( HeadStates, BDD_NOT( CurrentStates ) ) ; TestLength ++ ; } save_this_result( TestLength-1, BDD_SELECT_ONE( PreviousStates ) ) ; } Figure 6: Pseudo-Code for the Procedure finding an optimal reset state Symbolic techniques are needed due to the size of the graph to be traversed. The limit of the applicability of the proposed approach is in the number of Flip- Flops: currently, circuits with up to CSTP cells can be efficiently dealt with. Bigger circuits are difficult to manage with symbolic techniques, and additional heuristics need to be developed. 5. Conclusions The CSTP approach has been evaluated from an experimental point of view. The results show that the approach can produce very good Fault Coverage figures with a limited number of clock cycles, provided that the circuit does not reach an already visited state, thus entering a loop. On the contrary, the Aliasing phenomenon, to which past literature devoted many efforts, seems not to significantly affect the final Fault Coverage. To evalutate the proposed solutions to the known problems of the approach, the effects of Flip-Flops ordering and dummy Flip-Flops insertion have been considered, and a heuristic technique has been evaluated, which can avoid the functional dependency between adjacent elements in the chain. However, the experimental results show that this approach does not represent a general solution. Circuit m 0 FC(m 0 ) M FC(M) FSM , FSM FSM4 38, FSM S S S , S S , Table 5: Reachable states As a main contribution this paper, once assessed that known techniques do not help in building real CSTP circuits, solves the problem of choosing the initial state of the circuit. A method based on formal verification techniques and Binary Decision Diagrams is proposed, which is able to find the optimum values to be loaded into the Flip-Flops in order to maximize the number of reached states. The results we gathered demonstrate that the method represents a viable solution for many circuits, as it guarantees that a large number of states can be reached. In this way the effectiveness of the CSTP approach is fully exploited.

10 6. Acknowledgements The authors wish to thank S. Barbagallo, A. Burri and D. Medina of the Italtel Design Center for the useful discussions and for providing their industrial benchmarks. 7. References [AvMc93] [BBKo89] [Brya86] L.J. Avra, E.J. McCluskey: Synthesizing for Scan Dependance in Built-In Self- Testable Designs, IEEE International Test Conference, Baltimore (MA), USA, October 1993, pp F. Brglez, D. Bryan, K. Kozminski: Combinational profiles of sequential benchmark circuits, ISCAS-89: IEEE Int. Symposium on Circuits And Systems, Portland (OR), USA, May 1989, pp R. E. Bryant: Graph-based Algorithms for Boolean Function Manipulation, IEEE Transactions on Computers, vol. C-35, No.12, December 1986, pp [CHJP90] H. Cho, G. Hachtel, S.W. Jeong, B. Plessier, E. Schwarz, F. Somenzi: ATPG Aspects of FSM Verification, ICCAD-90: IEEE International Conference on Computer Aided Design, Santa Clara, CA (USA), November 1990, pp [CoMa90] [Gage93] [Gibb85] O. Coudert, J.C. Madre: A Unified Framework for the Formal Verification of Sequential Circuits, ICCAD-90: IEEE International Conference on Computer Aided Design, Santa Clara, CA (USA), November 1990, pp R. Gage: Structured CBIST in ASICS, IEEE International Test Conference, Baltimore (MA), USA, October 1993, pp A. Gibbons: Algorithmic Graph Theory, Cambridge University Press, Cambridge (MA), USA, 1985 [GMSR94] S. Gai, P. Montessoro, M. Sonza Reorda: TORSIM: An Efficient Fault Simulator for Synchronous Sequential Circuits, IEEE European Design Automation Conference, Paris (F), February 1994, pp [KMZw79] B. Konemann, J. Mucha, G. Zwiehoff: Built-In Logic Block Observation Technique, IEEE International Test Conference, October 1979, pp [KrPi89] [PKKa92] A. Krasniewski, S. Pilarski: Circular Self- Test Path: A low-cost BIST Technique for VLSI circuits, IEEE Transactions on CAD, Vol. 8, No. 1, January 1989, pp S. Pilarski, A. Krasniewski, T. Kameda: Estimating Testing Effectiveness of the Circular Self-Test Path Technique, IEEE Transactions on CAD, Vol. 11, No. 10, October 1992, pp [POLB88] M.M. Pradhan, E.J. O Brien, S.L. Lam, J. Beausang: Circular BIST with Partial Scan, IEEE International Test Conference, 1988, pp [Stro88] C.E. Stroud: An Automated BIST Approach for General Sequential Logic Synthesis, 25th ACM/IEEE Design Automation Conference, Anaheim, USA, June 1988, pp. 3-8