LDPC-PAM12 PHY proposal for 10GBase-T. P802.3an July 04 Jose Tellado, Teranetics Katsutoshi Seki, NEC Electronics

Transcription

1 LDPC-PAM12 PHY proposal for 10GBase-T P802.3a July 04 Jose Tellado, Teraetics Katsutoshi Seki, NEC Electroics 1

2 Supporters 2

3 Overview Mai parameters of PHY proposal PAM LDPC THP Start-up ad Framig Performace Margi or Noise Immuity Trasmitter ad Receiver assumptios Implemetatio 3

4 Mai parameters of PHY proposal FEC code: LDPC(833,1024) Modulatio: 12PAM. Symbol rate: 825MHz Equalizatio: Tomliso-Harashima precodig (THP) LDPC Framig MAC I/F, MAC/PHY Cotrol 4

5 LDPC 5

6 LDPC Parameters Code Iformatio bits/symbol Required SNR for BER=1E-12 Shao boud Gap to BER =1E-12 Itrisic Latecy Symbol rate (w/o packet overhead) Hammig Distace LDPC(833,1024) PAM12 mappig 3.13bits 23.8dB (*1) 18.8dB 5dB 160sec 799MHz 12 LDPC(1723,2048) PAM12 mappig 3.18bits ~ 24dB (*2) 19.1dB ~ 5dB 320sec 786MHz 8 *1 : Ref. *2 : Estimated based o Rao's proposal ad re-mappig the code from PAM8 to PAM12 LDPC(833,1024) has comparable performace to LDPC(1723,2048) with lower latecy. 6

7 LDPC(833,1024) Performace No error see i 2.0E13 bits at SNR=23.8dB Average umber of error bits per error blocks =24.0 No error see i 2.0E13 bits at SNR=23.8dB 80% Iterval upper boud - No error floor observed up to 1E-12 BER - Required SNR=23.8dB for 1E-12 BER FER=BER/24.0*1792 UB: Upper Boud BER with 80% cofidece NF: Number of Frames =2.0E13/1792 f(x) : The probability of error free at x FER ( UB / 24*1792) f ( x) dx f ( x) dx = 0.8 f ( x) = exp( NF *log(1 x)) 7

8 THP 8

9 Beefits of THP 1. Permits strog block code such as LDPC by decouplig chael equalizatio from chael codig Strog block code is ecessary to get sufficiet margi for implemetatio losses ad reliable performace 2. Error propagatio free Avoids sub-optimal performace of DFE equalizer 3. Removes DFSE timig loop Simplifies timig closure Ref. Scott Powell et al, Multi-Vedor Agreemet o Precoder Proposal 9

10 Performace relative to um. of coef. IL Model : P802.3 Task Force Material Measured Class E model ANEXT : *Iog10(F/100) ( F < 100MHz) *Iog10(F/100) ( F >= 100MHz) BGN : -150dBm/HZ Without other impairmets FFE : 64 taps 20 coefs. are ecessary to achieve eough performace over differet chaels 10

11 Performace relative to accuracy of coef. IL Model : P802.3 Task Force Material Measured Class E model ANEXT : *Iog10(F/100) ( F < 100MHz) *Iog10(F/100) ( F >= 100MHz) BGN : -150dBm/HZ Tx Power : 10dBm(Flat PSD) FFE : 64taps DFE : 32taps Bit legths after the decimal poit = #bits 3bit THP coefficiets requires 12 bits accuracy for egligible loss 11

12 THP proposal summary Number of coef. : 20 taps Bit accuracy of coef. : 12 bits Iteroperability : HDSL2 approach Coefficiets determied at start up the fixed We have provided a mechaism for coefficiet update which may be elimiated if we have sufficiet data to prove that the update is ot required 12

13 Startup protocol 13

14 Startup sequece 14

15 PHY Cotrol State Diagram lik_cotrol=enable cofig=master* miwait timer_doe* loc_rcvr_pma_status = OK* rem_rcvr_pma_status = OK Slave Silet Start maxwait timer tx_mode <= SEND_Z PMA Traiig Start miwait timer tx_mode <= SEND_P SEND THP coef. Start miwait timer tx_mode <= SEND_T miwait timer_doe*ts_detect=ok SEND THP coef. tx_mode <= SEND_F Ed of Secod FM Frame THP coef settig Start thp_set_timer tx_mode <= SEND_Z thp_set_timer_doe PCS Traiig Start miwait timer miwait timer_doe* loc_rcvr_pcs_status = OK miwait timer_doe* loc_rcvr_pcs_status = NOT_OK tx_mode <= SEND_L PCS Lik OK Stop maxwait timer Start miwait timer tx_mode <= SEND_L cofig=master+scr_status = OK cofig=slave* miwait timer_doe* tm_detect=ok SEND THP coef. Start miwait timer tx_mode <= SEND_T miwait timer_doe*fm_detect=ok tx_mode: PCS seds sigal accordig to this variable SEND_Z: Silet SEND_P: 2PAM-PRBS for PMA Traiig SEND_T: Frame for exchagig THP coefficiets (TM/TS) SEND_F: Frame for phase3 termiatio (FM) SEND_L: LDPC Frame tm_detect idicates whether TM frame is detected or ot ts_detect idicates whether TM frame is detected or ot fm_detect idicates whether FM frame is detected or ot 15

16 PCS Lik Moitor State Diagram 16

17 PMA Traiig sigal Objective: Recover timig ad adaptive filter coefficiets Establish polarity correctio, pair swap, pair deskew Side stream scrambler: (ref IEEE ) g m (x)=1+x 13 +x 33 g s (x)=1+x 20 +x 33 17

18 PMA Traiig sigal (cot ) Geeratio of bits Sy[3:0] Sy Sy Sy Sy [0] = Scr [0] [1] = g( Sy[0]) = Scr [2] = g( Sy [1]) = Scr g( Sy [3] = g( Sy g( x) = x 3 + x 8 [2]) = Scr [3]^ Scr [8] [2])^ Sy [0] = Scr [6]^ Scr [16] [9]^ Scr [14]^ Scr [19]^ Scr [24] if ( loc _ rcvr _ [9]^ Scr [14]^ Scr [19]^ Scr [24]^ Scr [0] pma _ status else = NG) Geeratio of Trasmit symbol vector 7 if ( Sy[0] = 0) A = 7 else 7 if ( Sy[2] = 0) C = 7 else 7 if ( Sy[1] = 0) B = 7 else 7 if ( Sy[3] = 0) D = 7 else This PMA traiig sigal ca meet objectives of polarity correctio, pair swap ad pair deskew. 18

19 19 >= + < = >= + < = >= + < = >= < = else TxTM if D else TxTM if C else TxTM if B else TxTM if A 7 0) 3 4 ( 7 7 0) 2 4 ( 7 7 0) 1 4 ( 7 7 0) 4 ( 7 PAM2 mappig THP coefficiet exchage frame

20 Framig 20

21 PCS Fuctioal block 21

22 FER Moitor FER_MT_INT high_fer <=false fer_test_prity<=false UCT reset+!block_lock!parity_valid START_TIMER fer_ct <= 0 start 125us_timer fer_test_parity FER_TEST_PARITY fer_test_prity<=false parity_valid 125us_timer_doe Proposal: FER moitor istead of BER moitor usig 66B 2bits syc header FER_BAD_PARITY fer_ct ++ fer_ct<tbd* 125us_timer_doe fer_test_parity* fer_ct<tbd* 125us_timer_ot_doe fer_ct=tbd HI_FER hi_fer <= true 125us_timer_doe GOOD_FER hi_fer <= false UCT block_lock: Boollea variable that is set true whe receiver aquires LDPC frame sychroizatio. The method used to detect frame sychroizatio is vedor depedet. parity_valid:boollea variable that is set true if recieved LDPC subuit has o parity check error. 22

23 Framig ad Cotrol 64B/65B Code (based o 64B/66B Clause 49) Aliged with LDPC Frame Automatic 64B/65B code syc after required LDPC frame syc Elimiates oe syc bit (uecessary with LDPC frame syc) data code 01 -> 0 cotrol code 10 -> 1 LDPC frame payload : B blocks PHYcotrol/padbits +112 pad bits for LDPC frame aligmet PHY cotrol/padbits ope for PHY status, THP updates, CRC, LDPC subuit : 1792bits =128 4D PAM12 symbol LDPC symbol frame : 33 LDPC subuits Symbol rate: 10Gx(1792x33)/(64x800)/14 = 825MHz Symbol rate of 825MHz is easy to geerate from stadard oscillators i the rage MHz (e.g. 25, 100, 125, 150MHz) with a N/M PLL multiplicatio 23

24 Framig ad Cotrol (cot ) 4224 = 128*33 =(2^7)*33 symbol clock Power of 2 (128=2^7) block facilitates use of frequecy domai processig. 24

25 Frame aligmet parameters Frame aligmet parameters Num. of Frame aligmet symbol (FAS) bits Num. of cadidate positios Assumed BER before decodig Average reframe time (Trf) Variatio reframe time (Vrf) False I-frame time (Tff) Out-of-frame detectio time (Tof) Misframe time (Tmf) 32 bits 4224 <1E frames 0 frames 4.367E15 frames = 709 years 4.00 frames 9.537E41 frames =1.55E29 years Note 1 : Two successive good FAS cofirmatio for frame aligmet Note 2 : Four successive bad FAS cofirmatio for frame misaligmet Ref. : D. Choi, Frame aligmet i digital carrier system A tutorial, IEEE Commuicatios magazie, Feb. 1990, p47-54 PAM2 Frame aligmet ca achieve fast reframe ad egligible misframe 25

26 Frame aligmet symbol spectrum All four Frame aligmet symbols (FAS) have good Spectral behavior Spectral Null at DC ad Nyquist frequecy Low peak to average level No spectral lies FAS spectrum has 2112 (=4224/2) carriers i 412.5MHz (=825MHz/2) Assumptios Max. trasmit voltage: 2.0Vp-p No digital filter 26

27 Trasmit bit orderig 27

28 LDPC Subuit Systematic Ecodig LDPC Ecodig (systematic) TxP<0:1600> (0:first bit) iput order TxP<0>=TxL<0> TxP<1449> TxP<1460> TxP<1598>=TxL<1785> ucoded 3bits TxP<1600> coded 4bits TxC<1020> TxC<0> TxP<6>=TxL<6>=TxC<3> TxP<1455> TxP<1459> TxL<1791>=TxC<1023> TxL<0:1791> (0:first bit) outut order TxP<0:1600>:Payload Subuit TxC<0:1023>:LDPC Codeword TxL<0:1791>:LDPC Subuit : Payload : Check bits 28

29 LDPC to PAM12 mappig Based o PAM12 mappig achieved with simple tables below TA=X1*8+X2 (12PAM mappig o wire A) TB=Y1*8+Y2 (mappig wire B) TC,TD shall use tx_data_ group<7:13> i the same way as TA,TB Tx_data_group<0:2> (ucoded bits A&B) X1 Y Tx_data_group <3:4> (coded bits wire A) X Tx_data_group <5:6> (coded bits wire B) Y

30 Scrambler Objective : Maitai DC balace Scrambler polyomial: x 58 +x The PAM2 frame aligmet symbols ad LDPC check bits shall ot be scrambled. 30

31 Performace 31

32 LDPC(833,1024) Margi Largest Margi or Noise Immuity close to 800MHz Assumptios: Model 3 with AWGN=-150dBm/Hz 4dBm Tx Power (2V pk-pk at MDI) LDPC 8dB gai EcCac(60dB), NXCac(40dB), FXCac(20dB), Margi (db) PAM LDPC(833,1024) Margi 12PAM 8PAM ADC(9b), DAC(10b) Samplig Rate (MHz) ANEXT Margi SNR Margi 16PAM 12PAM 8PAM 32

33 12PAM at 825MHz (cot) 12PAM at 825MHz has largest margi Multiple presetatios cofirm largest margi close to 800MHz Broadcom~800MHz, NEC Electroics ~820MHz, Solarflare~833MHz, KeyEye~833 (ucoded 8PAM) 12PAM has lower symbol rate ~20% reductio i digital power cosumptio relative to 8PAM ~20% reductio i badwidth of aalog ad mixed sigal circuits relative to 8PAM 12PAM ca be combied efficietly with THP Allows for Framig ad MAC/PHY Cotrol overhead 33

34 Performace Margi 12PAM LDPC(833,1024) requires receiver SNR=23.8dB for BER<1E-12 ANEXT Lik Margi (Salz). Model 1&3: ~7.5dB Model 2: ~6.6dB SNR Lik Margi (Salz) Model 1&3: ~4.8dB Model 2: ~5.6dB 34

35 Trasmitter assumptios Modulatio: 12PAM FEC code: LDPC(833,1024) Symbol rate: 825MHz DAC resolutio: 10bits DAC speed: 825MHz Max trasmit lauch voltage: 2volt pk-pk at MDI port 35

36 Receiver assumptios Echo suppressio: 60dB NEXT suppressio: 40dB FEXT suppressio: 20dB ADC speed: 825MHz Ideal ADC resolutio: 9bits PAR at iput to ADC: 14dB Echo cacellatio prior to ADC: 25dB Additive Gaussia oise at receiver: -150dBm/Hz 36

37 Implemetatio 37

38 Implemetatio Complexity Digital Gates: 4M if operated at Fs This is ot a recommedatio to operate digital at Fs Power: 8W assumig 90m process Digital: ~3.5W Aalog: ~4.5W Tradeoffs possible betwee power ad gate cout 38

39 LDPC-PAM12 Proposal Summary Achieves 5-6dB of margi o approved chael models 1-4 Required to meet 10G objectives with sufficiet margi Low Itrisic latecy of ~160s Very similar parameters to multiple PHY proposals (THP, LDPC, Symbol rate ~800MHz ) 39