Automatic Repositioning Technique for Digital Cell Based Window Comparators and Implementation within Mixed-Signal DfT Schemes

Transcription

1 utomti Repositioning Tehnique for Digitl ell sed Window omprtors nd Implementtion within Mixed-Signl DfT Shemes D. De Venuto DEE- Politenio di ri, Itly, M. J. Ohletz MI Semiondutor, elgium Riò DEIS Università di ologn bstrt The possibility of using window omprtors for the on-hip evlution of signls in the nlogue iruit prt hs been demonstrted nd is shortly summrised. One of the problems is the lot-to-lot vrition of the omprtor window. n utomti window repositioning tehnique is detiled tht llows to ompenste the window shift. The omponents for the implementtion omprising referene omprtor nd the evlution omprtors re desribed long with the implementtion of the tehnique. It is shown, tht this tehnique llows the utomti lot ondition djustment of the evlution omprtors. Furthermore the tehnique n provide lot speifi informtion to n utomted test equipment tht n be doumented in the test results due to its dignosis pbility. 1. Introdution Sfety systems in eletronis re one of the key issues in highly relible pplitions, suh s rilwy, utomotive, eronutis nd other industries. esides the proess qulity ost-effetive testing is one of the prmeters to hieve this high qulity. The most ost-effetive wy of testing in terms of test time optimiztion nd lso time-to-mrket is Designfor-Testbility (DfT). Tody wide rnge of DfT tehniques exists for digitl integrted iruits (I), but only few proposls re known for nlog nd mixed-signl Is. Sine test osts n lwys be trded off ginst die re, DfT lso beomes interesting for ost sensitive produts like onsumer or utomotive mixed-signl Is. For those produts n interesting test solution onsists in heking ertin Doperting points or signl levels on ritil iruit nodes. This hek n be performed t different (test) time instnes, supply voltge onditions nd tempertures. Furthermore, the ontinuous observtion of ritil nodes n lso be used during the pplition to hieve on-line selfheking pbilities (similr like for digitl Is) [1] e.g. to flg filures to ontrol unit in sfety-ritil pplitions. In order to hek the orretness of nlogue voltges t seleted nodes omprtors re required. Different proposls hve been mde ddressing this type of DfT. In [2] the design of hekers imed t the onurrent test of nlog nd mixed-signl iruits is onsidered. In this pper the inherent redundny of the iruit to be tested ws exploited whih results in the use of ode for the nlog signls. In [3] strobed omprtor with vrible threshold is proposed, tht n be used s wveform digitizer. This solution, however, demnds high requirements in terms of bndwidth nd lok skew/jitter. nother sheme desribes very speifi pplition of on-hip nlogue differentil omprtor [4] trgeted t mesuring the dynmi performne of the differentil SRM sense mplifier. The result is ompred with n externlly pplied differentil signl. bis-progrmmble, loked, two-mode omprtor with hysteresis for mixed-signl Is is introdued in [5-6]. In this pproh the nlogue omprtor is implemented by funtionl onversion of system OTs or opertionl mplifiers (Opmp) during test mode [6], in whih different thresholds n be progrmmed vi the bising from the digitl prt. Reently simple omprtor sheme hs been presented in detil bsed on digitl gtes nd referred to s digitl window omprtor [7-9]. s it hs been desribed this type of omprtor is sensitive to the lot-to-lot vrition of the threshold voltges of the NMOS nd PMOS [9]. This pper dels with the different possibilities to stbilize the width nd position of this window utomtilly ginst hnges due to tehnologil prmeter spred. This tehnique llows to some extend to monitor the tul proess ondition. The possible insertion of those omprtors in n lredy existing sn pth is lso investigted, in order to mke the test solution esy nd flexible /03 $ IEEE

2 2. Priniple of Digitl Window omprtor s desribed in detil in [7] nd depited in fig. 1 simple digitl window omprtor n be implemented with n i- input NND, j-input NOR nd dditionlly with n EXOR gte. The trget of this DfT pproh is to implement simple on-hip evlution iruit whih only requires digitl logi gtes without the need of dditionl nlogue I/Os. NMOS fst, PMOS fst Overlp region NMOS fst, PMOS slow Input Output NMOS slow, PMOS Fig. 1 Generl Digitl Window omprtor The priniple is bsed on the ft tht the logil threshold V LT of NNDs nd NORs n be shifted in opposite diretions depending on the number of gte inputs onneted together (input) nd onneted to V DD nd ground, respetively. t lest one input of the NND nd NOR gte (b 1, b 2) must be onneted together to form the omprtor input. The required width nd position of the window dittes the number of inputs for the NND (i) nd NOR (j) nd lso how mny of those gte inputs must be onneted to V DD, ground or to the ommon omprtor input. In fig. 1 this onnetion onfigurtion is represented by the blok. Those inputs of the gtes tht re not onneted with the omprtor input re either onneted to the supply V DD (NND) or the ground (NOR). The outputs of the NND nd the NOR n be onneted to n EXOR gte to ompress the omprtor into single bit output. For digitl inputs the omprtor output (EXOR) is lwys t logilly zero. If, however, n nlogue input signl is pplied, the output of the EXOR depends on the tul level of the input signl. If the logil thresholds of the NND nd NOR re different, then there exists rnge (V LT_NND V LT_NOR) where the omprtor output () swithes to logilly one. This rnge is referred to s omprtor window. The NND nd the NOR bsilly operte s inverters with shifted logil threshold V LT depending on the W/L rtios nd the number of inputs of the NND nd the NOR onneted to V DD (NND) or (NOR). For suh n inverter onfigurtion the logil thresholds n be derived from eqution 1[9,10]: V LT + V thp + β V = 1+ β thn (Eq. 1) NMOS typ, PMOS typ Fig. 2 hrteriztion of 2-input NND/NOR window omprtor for -40 nd +150 with V thp nd V thn being the threshold voltges for the p nd n-trnsistor, respetively, V DD the supply nd β is defined s: β = Kn ( Wn / Ln) Kp ( Wp / Lp) NMOS slow, PMOS slow (Eq. 2) Note, tht if V thp = - V thn nd β=1 the logil threshold voltge beomes V DD/2. s n be seen in eqution 1 depending on β the logi threshold V LT n be moved up nd down. Thus, it n be djusted within some rnge between ground nd the supply V DD. The detils on how to build the respetive omprtors is given in [9]. 3. Window shift due to Lot-to-lot Vrition The pplibility of the omprtor onept depends on the vrition of the two properties of the omprtor window: ) the window width nd b) the window position. oth depend on the mbient temperture nd the lot-to-lot vrition of the tehnology. During the iruit design those impts re ddressed within the proess of the so-lled iruit hrteristion. This n either performed by Monte- rlo simultions or by worst se simultions ssuming orner lots. The impt of the mbient temperture is overed by temperture sweep simultions, e.g between -

3 40 nd s shown in the previous investigtions [7, 8] the impt of the tul mbient temperture n be negleted wheres the lot-to-lot vrition of the threshold voltges of the NMOS nd PMOS showed signifint impt. In fig. 2 the result of the hrteristion for n exmple omprtor is depited. Four orners nd the typil se hve been simulted hrterised by the speed of the trnsistors: 1 NMOS fst PMOS fst 2 NMOS fst PMOS slow 3 NMOS slow PMOS fst 4 NMOS slow PMOS slow 5 NMOS typil PMOS typil s n be seen from fig.2 the ombintions 2 nd 3 re the ritil ones, s in those ses the windows move out of the ommon overlp region mrked by the left nd right stright lines. The entre line indites the D level of the ssumed node under test. Note, tht this simultion lso shows the temperture impt (-50 nd +150 ). s n be seen the position of the window is not ffeted, but the width. The mount of the window shift depends on the lot-to-lot vrition nd is tehnology depend prmeter. Therefore only the hrteristion dt n identify whether or not this is problem for the pplition of the window omprtor. The trget of this pper is to investigte the possibilities to stbilise the window position if the window n move outside the overlp region. Two problems hve to be solved. First, to detet tht the position of the window hs moved for n tul lot nd seondly to ompenste this window shift. oth problems re ddressed under the ondition to keep the inrese in the omplexity of the implementtion s low s possible. The min ontributor for the lot-to-lot vrition is the threshold voltge of the PMOS nd NMOS (f. eq. 1). The vrition of the oxide thikness ross the die nd ross different lots n be negleted in omprison with the threshold vrition. In generl the mthing of the spet rtios is lso quite urte nd n lso be onsidered s less importnt (eq. 2). The impt of the mobilities µ n.p n be onsidered s seond order effet, whih only impts the βs if the µ s re deviting in opposite diretions. With respet to the lot-to-lot vrition of the threshold voltges two ses hve been investigted. The threshold voltges of the PMOS nd NMOS move: ) both by the sme perentge but opposite diretions, i.e. V thp beomes smller nd V thn lrger by the sme mount b) by the sme perentge in the sme diretion, i.e. V thp nd V thn beome lrger by the sme mount. Those onditions n be onsidered s worst se onditions. From eqution 1 it n esily be seen, tht for β lose to 1 the impt in se ) is lmost nelled out sine lwys V thp = - V thn is vlid. However, if the devitions our s desribed in se b) this is not true nymore. If in eqution1 β is inresed, V LT tends towrds V thn, while for smll vlues of β the logil threshold tends towrds V DD- V thp. Thus, ny devition in the threshold voltges diretly impts the logil threshold of the omprtor in either se ) nd b). se b), however, onstitutes the worst se of the two, sine lredy for β=1 the V LT shifts by the differene of the threshold voltges V thp - V thn if they do not mth. Simultions showed tht within the onsidered rnge of βs nd for the mximum mismth of ± 30% between the threshold voltges, the mximum reltive error for the NND mounts to ±19.4% wheres for the NOR it mounts to 13,2%. 4. Window Repositioning s shown in the previous hrteriztion of the omprtor in fig. 2 the position of the omprtor window n shift even outside the overlp region. However, in order to keep the omprtor opertion relible this shift due to the lot-lot vrition hs to be ompensted. This n be hieved by modifying the omprtor onfigurtion ordingly. This tehnique will be desribed in this prgrph. Input Fig. 3 omprtor onfigurtion for typil tehnology V(x) V(y) V(x1) V(y1) typil In fig. 3 digitl window omprtor is shown. The onfigurtion is ssumed to be the one tht mthes the window of 600mV extly round the D signl of 2,9V in se of typil tehnology with typil vlues of the V thp nd V thn. The respetive window is shown in fig. 4 (typil). If for the sme omprtor onfigurtion orner lot with Vin pfst-nslow Fig. 4 Observtion window shift due to PMOS fst-(pfst) NMOS slow (nslow)vrition.

4 PMOS_fst-NMOS_slow ours (pfst-nslow) the window is shifted by 200mV in this se. Note, tht in this se there is still n overlp region, whih onfirms tht hrteriztion is required to verify the mount of window shift. Input Fig. 5 The omprtor of fig. 3 in different onfigurtion hosen to reposition the window in se of pfst-nslow V(x) V(y) V(x2) V(y2) typil Vin To reposition the window, the tul omprtor onfigurtion n be hnged suh, tht in se of this orner lot the window is gin entered round the D signl of 2,9V. In fig. 5 the respetive onfigurtion is depited. Note, tht the onfigurtion of the inputs hve been hnged for both, the NND nd the NOR. fter the hnge of the onfigurtion now the window hs been repositioned nd is gin entered round 2,9V. Thus, if the lot is typil the onfigurtion in fig. 3 hs to be used. If, however, the prtiulr lot is orner lot of pfst-nslow the onfigurtion must be hnged to the one depited in fig. 5. s hs been desribed in [7,8] there re different onfigurtions possible to hieve the sme result nd it is up to the designer whih onfigurtion to hoose. The sme tehnique n be employed to reposition the window for the orner lot ondition pslow-nfst. One effet tht hs to be onsidered is the impt of the window width whih n be ffeted depending on the hosen onfigurtion. eside the possibility to hnge the omprtor onfigurtion the logi gtes themselves n be modified by hnging the spet rtio of the NMOS nd/or PMOS. Whether or not the window hs to be repositioned depends on the tul lot nd the mount by whih the window is shifted. s long s the shift is tolerble no repositioning is Repositioned window for pfst-nslow Fig.6 The effet of the onfigurtion shown in fig.3: the window is now positioned in the overlpping region of the window for typil prmeters required. The deision n be mde bsed upon the hrteriztion result. In generl the first ttempt is to find different omprtor onfigurtion. Only if no stisfying onfigurtion is found modifition of the spet rtios of the NMOS nd PMOS trnsistors of the logi gtes should be onsidered, sine the trget is to used gtes from stndrd librry. nother reson to modify the spet rtio insted of using nother omprtor onfigurtion n rise from the impt of the onfigurtion on the window width. 5. Implementtion of the Repositioning onept into DfT sheme In the previous prgrph the problem of the lot dependent repositioning of the window hs been solved. However, the problem to identify the tul lot ondition ws not yet ddressed. This prgrph will desribe the implementtion onept. For the implementtion three problems hve to be solved: 1 identifying the tul lot ondition 2 pplying the respetive omprtor onfigurtion 3 utomti on-hip seletion of the right onfigurtion Sine the tul lot ondition n not be known up-front, it is not possible to implement the right omprtor onfigurtion. Thus, in the first step the tul lot ondition must be deteted. efore the different omponent of will desribed, the onept will be outlined. The bsi ide is to implement speil omprtor tht detets the lot ondition by n utomti on-hip mesurement. This referene omprtor then genertes three ontrol signls for the onditions nfst-pslow, typil nd nslow-pfst. Those ontrol signls re used to utomtilly selet the right omprtor onfigurtion of the tul signl evlution omprtors. In generl the onfigurtion for the evlution omprtors ould be seleted by multiplexer network (blok in fig. 1). This however, would involve swithes in the signl pth tht ould interfere with the signl under observtion. Therefore this pper proposes nother solution where three omprtors re implemented. Eh omprtor onfigurtion is hosen suh tht its window is entred round the signl under evlution under one of the three lot onditions. One the lot ondition is deteted, the respetive evlution omprtor onfigurtion is hosen nd onneted to n EXOR-tree or sn-pth. The implementtion of the different omponents is desribed in the following in detil. 6. utomti lot ondition detetion One solution to perform n on-hip lot ondition detetion is the implementtion of speil omprtor whih is onneted to on-hip referene or vi n vilble or

5 multiplexed pin to n externl referene supplied by the utomti test equipment (TE). s long s the tul pin ount of the pkge is not exhusted this solution should be preferred. The on-hip referene should not be linked to the sme tehnology step from whih the threshold voltges of the logi gtes re depending. For exmple bnd-gp voltge or simple resistive divider ould be used. The referene omprtor omprises bsilly of three window omprtors The priniple is depited in fig. 7. It bsilly opertes like the window omprtor in fig.1 nd n be esily understood if the NNDs nd NOR re repled by simple inverters with different logil thresholds, wheres the NOR t the bottom (nfst-pslow) exhibits the lowest logil threshold nd the NND t the top exhibits the highest logil threshold (nslow-pfst). To identify whether the lot is orner lot the typil signl level is pplied (externlly or internlly). If the lot is typil then the NND nd the NOR of the bottom omprtor re zero nd the output 1 is lso zero. The EXOR output of the typil omprtor (1) is one sine the pplied referene level flls into the window of this omprtor, i.e. the level is between 2 the logil threshold of the bottom NND nd the NND of the typil omprtor. Sine the referene level in se of typil lot is below the nslow-pfst omprtor this output (1) is zero. If however the lot is either nslow-pfst or nfst-pslow this is indited by 1=1 or 1=1. The outputs 2 nd 2 re optionl to indite whether the lot is even outside the worst se orners nd ould be inluded in sn-pth to flg this ondition to the TE. The ontrol signls n now be used to selet the right omprtor onfigurtions of the other window omprtors of the I. Note, tht only one referene omprtor is needed. 7. Evlution omprtors The evlution omprtors (fig. 8) onsist of tully three omprtors with different onfigurtions. Eh onfigurtion is hosen suh, tht the window of one omprtor is entred round the signl under evlution, i.e. depending from the lot ondition nfst-pslow, typ, nslowpfst. Eh single omprtor resembles opy of the omprtor s shown in fig.1. Nslow-pfst 1 Sn-pth Nslow-pfst 1 Signl typil 1 MS- FF 1 Ref. 1 Nfst-pslow typil Fig. 8 Evlution omprtor with seletion logi for different orner lot onditions without dignosis funtion 1 Nfst-pslow 2 Fig. 7 Referene omprtor for utomti lot ondition detetion Vi the ontrol signls 1-1 one of the omprtor onfigurtions is onneted vi the seletion logi to mster-slve flip-flop whih n be prt of sn pth hin. Note, tht the seletion of the right omprtor onfigurtion is done utomtilly vi the referene omprtor s shown in fig. 7. The shemti shown in fig. 8 depits n evlution omprtor without dignosis funtion, i.e. it only indites whether the evluted signl is within or outside the window. With modifition however, n dditionl dignosis is possible. The modified evlution omprtor is shown in fig. 9.

6 Signl Nslow-pfst typil 1 1 Sn-pth MS- FF MS- FF enble the detetion of the lot ondition s well s the omprtor onfigurtion to be seleted for the prtiulr tehnologil sitution. Tble 1 summrises wht n be seen lredy from the fig It shows in ft the resulting pttern t the output of the omprtor when the smpling signl entres eh of the levels imposed t the input by the test signl hosen. In this tble, the sequene 000 t the EXOR outputs of the single evlution omprtor ell detets the respetive tehnology ondition. Thus, if t one omprtor output the pttern 000 ppers in turn lso the tul tehnology ondition is known through this kind of test. Note, tht this is synergy effet tht provides dditionl informtion bout the prtiulr lot input signl Nfst-pslow Fig. 9 Evlution omprtor with seletion logi for different orner lot onditions with dignosis funtion In this implementtion version the EXORs n be omitted s the outputs of the NNDs nd NORs re diretly evluted. s hs been desribed in [6, 7] in this onfigurtion both outputs nd re vilble nd depending on the vlues the signl level n be dignosed to be either inside the omprtor window, or beyond or below. In this implementtion the seletion logi nd the msterslve flip-flop (MS-FF) re duplited whih is ompensted by the sving of the three EXORs. 8. Test Proedure If the referene omprtor is essible vi n vilble or multiplexed pin the referene omprtor n be tested for stuk-t filures. This is performed during the pre-test phse. During this phse test signl is to be ssign to the omprtor input. In fig n exmple is shown. In this prtiulr se piee wise onstnt signl is pplied t the referene input nd then the different test response n be observed if the referene omprtor is inluded in the snpth or when onneted to n EXOR-tree. The test responses depend on the tehnologil ondition. In fig. 10 the test response for typil lot is shown, in fig. 11 for orner lot pslow-nfst nd in fig. 12 for orner lot pfst-nslow. Three phses n be distinguished. First signl prt orresponds to nfst-pslow lot ondition, the seond phse the input signl is zero nd ll omprtor outputs re zero s well. Finlly the third phse orresponds to nslowpfst ondition. Smpling the output signls t suitble frequeny different ptterns will be detet whih in turn will nslow-pfst nfst-pslow 5. Typil SEL> 0s 0.5us 1.0us 1.5us 2.0us In order to bring the test result both from the referene omprtor s well s from the evlution omprtors t lest one output pin must be vilble. This pin n be Time Fig. 10 Test response for typil lot ondition SEL> input signl nslow-pfst nfst-pslow typil 0s 0.5us 1.0us 1.5us 2.0us Time Fig. 11 Test response for pslow-nfst lot ondition SEL> input signl nslow-pfst nfst-pslow typil 0s 0.5us 1.0us 1.5us 2.0us Time Fig. 12 Test response for pfst-nslow lot ondition Tb. 1 logil responses of evlution omprtors to test input EXOR OUTPUT Typil lot pslow-nfst lot nslow-pfst lot typ nfst-pslow nslow-pfst

7 multiplexed digitl pin. If n input pin is vilble the test s desribed bove n be performed. This pin however, must be n nlogue input pin, whih ould lso be multiplexed. The red-out of the test responses n either be done vi n EXOR-tree or vi sn-pth. For eh evlution omprtor one mster-slve flip-flop is required if no signl level dignosis is required. If the dignosis is requested two MS-FFs re neessry. In the ltter se the EXORs for eh of the omprtors n be omitted. urrently the whole implementtion onept is under refinement to further sme gtes nd mke the implementtion more robust nd more effiient. 9. onlusion simple DfT-sheme for mixed-signl Is is desribed tht uses digitl window omprtors to observe the D levels on nlogue iruit nodes. Two omprtors hve been desribed: referene omprtor to detet the lot ondition nd to utomtilly selet on-hip the orret onfigurtion of evlution omprtors nd seondly n dptive evlution omprtor sheme. The ltter one omprises of three different onfigurtions of digitl window omprtors. Eh is designed to fit the signl under evlution for n tul orner lot ondition. Vi three internlly nd utomtilly generted ontrol signls the tul evlution omprtor n be seleted. The evlution omprtors n either be used with or without dignosis pbility to detet the rnge of the signl under evlution. To bring the test result off-hip one digitl pin is required tht n lso be multiplexed if no digitl pin is vilble. The omprtor outputs n be onneted to n EXOR-tree or inluded in sn-pth. In se of required dignosis two mster-slve flip-flops re required per evlution omprtor. Is no dignosis required one mster-slve flipflop is suffiient. If the output of the referene omprtor is lso inluded in the EXOR-tree or sn-pth the lot ondition n be brought off-hip nd thus, n be stored in the result file of the utomted test equipment for lter trtbility. For the implementtion of the omprtor nd the seletion logi only few digitl stndrd or dedited logi gtes re required. It ws shown tht the limittions from the lot-to-lot vrition of the threshold voltges of the P- nd NMOS n be overome. The desribed tehnique llows to reposition the omprtor window to mth the signl under investigtion lso in the presene of window shifts due to lotto-lot vrition. The solutions re bsed on the possibility to shift the observtion window of the omprtor by hnging the inputs onnetions or by modifying the spet rtios of the NMOS nd/or PMOS trnsistors. In prtiulr the bility to ompenste the threshold vritions of the NMOS nd PMOS in se of devitions in opposite diretions i.e. the ondition pfst-nslow, nslow-pfst hs been investigted. It ws shown tht during the pre-test phse the tul lot ondition n be identified. urrently the implementtion onept is under refinement to hieve inresed robustness nd lower gte ount for the implementtion. 10. Referenes [1]. Metr, M. Fvlli, P. Olivo,. Riò On-line Detetion of ridging nd Dely Fults in Funtionl loks of MOS Self- heking iruits}, IEEE Trns. on omputer ided Design, vol. 16, p.770, [2] V. Kolrik, S. Mir, M. Lubszewski nd. ourtois. nlogue hekers with bsolute nd reltive tolernes. IEEE Trnstions on omputer-ided Design of Integrted iruits nd Systems, 14(5): , My [3] K. Loftstrom, Erly pture for oundry Sn Timing Mesurements, pro. IT, pp , 1996 nd Systems, 14(5): , My [4] R. D. dms, E. S. ooley, P. R. Hnsen, Self-Test iruit for Evluting Memory Sense-mplifier Signls, pro. IT, pp , [5] D. De Venuto, M. J. Ohletz, is-progrmmble Hrdwre Reonfigurtion for On-hip Test Response Evlution, IEEE pro. IMSTW 2000, June 21-23, Montpellier, Frne pp , [6] D. De Venuto, M.J. Ohletz: On-hip test for Mixed-signl SIs using two-mode omprtors with bis-progrmmble referene voltges, on Journl of Eletroni Testing (JETT) vol. 17 n. 3/4, June/ugust 2001, pp , Kluwer demi Publisher US.. [7] D. De Venuto, M. J. Ohletz,. Riò, On-hip Signl Level Evlution for Mixed-Signl Is using Digitl Window omprtors, Pro. IEEE ETW01, 29 My - 1 June 2001, Stokholm, Sweden, pp , [8] D. De Venuto, M. Ohletz,. Riò: Digitl window omprtor for mixed-signl I s design for testbility, on Journl of Eletroni Testing (JETT) Jnury vol. 18 n.2, pril 2002, pp , Kluwer demi Publisher US. [9] D. De Venuto, M. J. Ohletz,. Riò, Testing of nlogue iruits vi (Stndrd) Digitl Gtes, Pro. of IEEE 3rd Interntionl Symposium on Qulity Eletroni Design (ISQED 2002), pp , Mrh 18 20, 2002 Sn Jose,, US [10] N. H. E. Weste, K. Eshrghin, Priniples of MOS VLSI Design, ddison-wesley Publishing ompny, ISN , pp , 1994.