Hierarchical Reversible Logic Synthesis Using LUTs

Transcription

1 Hierrhil Reversile Logi Synthesis Using LUTs Mthis Soeken Mrtin Roetteler Nthn Wiee Giovnni De Miheli Integrted Systems Lortory, EPFL, Lusnne, Switzerlnd Mirosoft Reserh, Redmond, WA, USA ABSTRACT Tody s rpid dvnes in the physil implementtion of quntum omputers demnd for slle synthesis methods in order to mp prtil logi designs to quntum rhitetures. We present synthesis lgorithm for quntum omputing sed on k-lut networks, whih n e derived from Verilog netlists using stte-ofthe-rt nd off-the-shelf mpping lgorithms. We demonstrte the effetiveness of our method in utomtilly synthesizing severl floting point networks up to doule preision. As mny quntum lgorithms trget sientifi simultion pplitions, they n mke rih use of floting point rithmeti omponents. But due to the lk of quntum iruit desriptions for those omponents, it is not possile to find relisti ost estimtion for the lgorithms. Our synthesized enhmrks provide ost estimtes tht llow quntum lgorithm designers to provide the first omplete ost estimtes for host of quntum lgorithms. This is n essentil step towrds the gol of understnding whih quntum lgorithms will e prtil in the first genertions of quntum omputers. INTRODUCTION Reent progress in frition mkes the prtil pplition of quntum omputers tngile prospet [, 9, 6]. However, s quntum omputers sle up to tkle prolems in omputtionl hemistry, mhine lerning, nd ryptnlysis, design utomtion will e neessry to fully leverge the power of this emerging omputtionl model. A mjor prolem fing quntum omputing is the inility of existing hnd rfted pprohes to generte networks for sientifi opertions tht require resonle numer of quntum its nd gtes. As n exmple, the quntum liner systems lgorithm requires s few s (logil) quntum its to enode mtrix inversion prolem [8, 5]. However, in prior pprohes the reiprol step in the lultion n require in exess of 5 quntum its whih mens tht rithmeti my dominte the memory requirements (i.e., numer of quits) of tht lgorithm [3]. Similrly, reent quntum hemistry simultion lgorithms n provide improved sling over the est known methods ut t the prie of requiring the moleulr integrls tht define the prolem to e omputed []. While floting point ddition ws studied efore [6, ], t present networks do not exist for more omplex floting point opertions suh s exponentil, reiprol squre root, multiplition, nd squring. Without the ility to utomtilly generte Permission to mke digitl or hrd opies of ll or prt of this work for personl or lssroom use is grnted without fee provided tht opies re not mde or distriuted for profit or ommeril dvntge nd tht opies er this notie nd the full ittion on the first pge. Copyrights for omponents of this work owned y others thn ACM must e honored. Astrting with redit is permitted. To opy otherwise, or repulish, to post on servers or to redistriute to lists, requires prior speifi permission nd/or fee. Request permissions from permissions@m.org. DAC 7, Austin, TX, USA 7 ACM /7/6... $5. DOI:.5/ iruits for these opertions it will e nerly impossile tsk to estimte the full osts of suh lgorithms let lone verify tht the underlying iruitry is orret. It hs reently een shown [8] tht hierrhil reversile logi synthesis methods sed on logi network representtions re le to synthesize lrge rithmeti designs. The underlying ide is to mp sunetworks into reversile networks. If the sunetworks re smll enough, one n use less slle funtionl reversile synthesis methods tht re sed on Boolen stisfiility [], truth tles [], or deision digrms [3]. However, logi networks differ quite signifintly from reversile logi networks when onsidering their struture. This is one of the min disdvntges of urrently known hierrhil synthesis methods. As one exmple, when using reversile iruits in quntum omputers, ll outputs must either ompute primry input vlue, primry output vlue, or onstnt they nnot expose n intermedite result to n output line, whih is referred to s grge output. Stte-of-the-rt lgorithms suh s the pproh presented in [8] do not expliitly onsider tehniques to unompute vlues suh tht there re no grge outputs. In order to use the iruit in quntum omputer, one needs to pply tehnique lled Bennett trik [5], whih requires to doule the numer of gtes nd dd one dditionl iruit line for eh primry output. In this pper we present hierrhil synthesis pproh sed on k-fesile Boolen logi networks. These re logi networks in whih every gte hs t most k inputs. These re often lso referred to s k-lut (lookup tle) networks. We show tht there is oneto-one onnetion etween k-input LUT in logi network nd reversile single-trget gte with k ontrol lines in reversile network. A single-trget gte hs ontrol funtion nd single trget line, tht is inverted if nd only if the ontrol funtion evlutes to. Eh single-trget gte n e synthesized into quntum iruit using tehniques suh s exlusive-sum-of-produt (ESOP) deomposition [3]. As first step, our synthesis pproh n quikly derive skeleton for the reversile network tht is only sed on single-trget gtes. In this skeleton, the numer of required dditionl lines is lredy finl, nd lso it is gurnteed tht it hs no grge outputs. In the seond step, eh single-trget gte is synthesized using seprte lgorithm. It is possile to prllelize the seond step. We used our lgorithm to find reversile logi networks for severl floting point rithmeti networks up to doule preision. From these networks we n derive ost estimtes for their use in quntum lgorithms. This hs een missing informtion in mny proposed lgorithms, nd rithmeti omputtion hs often not een expliitly tken into ount. Our ost estimtes show tht this is misleding s for some lgorithms the rithmeti omputtion ounts for the dominnt ost.

2 DAC 7, June 8, 7, Austin, TX, USA M. Soeken et l. y y y s s s x x x 6 x 7 x 9 x 8 x x x () () () Figure : A -fesile network with inputs, 3 outputs, nd 3 gtes PRELIMINARIES. Some Nottion A digrph G = (V, A) is lled simple, if A V V, i.e., there n e t most one r etween two verties for eh diretion. We refer to d (v) = #{w (w,v) A} nd d + (v) = #{w (v,w) A} s in-degree nd out-degree of v. We use [n] s the short hnd for {,..., n}.. Boolen Logi Networks A Boolen logi network is simple digrph whose verties re primry inputs, primry outputs, nd gtes nd whose rs onnet gtes to inputs, outputs, nd other gtes. Formlly, Boolen logi network N = (V, A, F ) onsists of simple digrph (V, A) nd funtion mpping F. It hs verties V = X Y G for primry inputs X, primry outputs Y, nd gtes G. We hve d (x) = for ll x X nd d + (y) = for ll y Y. Ars A (X G G Y ) onnet primry inputs nd gtes to other gtes nd primry outputs. Eh gte д G relizes Boolen funtion F (д) : B d (д) B. Finlly, we ll network k-fesile if d (д) k for ll д G. Sometimes k-fesile networks re referred to s k-lut networks (LUT mens lookup-tle) nd LUT mpping (see, e.g., [7, 9,, 7]) refers to fmily of lgorithms tht otin k-fesile networks, e.g., from homogeneous logi representtions suh s And-inverter grphs (AIGs, [8]) or Mjority-inverter grphs (MIGs, []). Exmple.. Fig. shows -fesile network of the enhmrk m85 otined using ABC [6]. It hs inputs, 3 outputs, nd 3 gtes. The gte funtions re not shown ut it n esily e heked tht eh gte hs t most inputs..3 Reversile Logi Networks A reversile logi network relizes reversile funtion, whih mkes it very different from onventionl logi networks. Reversile networks re sde of reversile gtes nd the most generl gte we onsider in this pper is the single-trget gte. A single-trget gte T ({x,..., x k }, x k+ ) hs ontrol lines x,..., x k, trget line x k+, nd ontrol funtion : B k B. It relizes the reversile funtion f : B k+ B k+ with f : x i x i for i k nd f : x k+ x k+ (x,..., x k ). All reversile funtions n e relized y sdes of single-trget gtes []. We use the opertor for ontention of gtes. Exmple.. Fig. () shows reversile iruit tht relizes full dder using two single-trget gtes, one for eh output. Two dditionl lines, lled nill nd initilized with, re dded to Figure : Reversile iruit for full dder using () singletrget gtes, () 3 Toffoli gtes nd 3 CNOT gtes, nd () Toffoli gte nd 6 CNOT gtes. the network to store the result of the outputs. All inputs re kept s output.. Mpping to Quntum Ciruits The most ommonly used pproh to implement quntum iruits is to onstrut lssil reversile iruit with multiple-ontrolled Toffoli gtes nd mp these into sequene of Clifford gtes nd T gtes. A multiple-ontrolled Toffoli gte is speil single-trget gte in whih the ontrol funtion is (tutology) or n e expressed in terms of single produt term. One n lwys deompose single-trget gte T ({x,..., x k }, x k+ ) into sde of Toffoli gtes T (X, x k+ ) T (X, x k+ ) T l (X l, x k+ ), () where = l, eh i is produt term or, nd X i {x,..., x k } is the support of i. This deomposition of is lso referred to s ESOP deomposition. If = x i, we refer to T ({x i }, x k+ ) s CNOT gte. Exmple.3. Fig. () shows the full dder iruit from the previous exmple in terms of Toffoli gtes. Eh single-trget gte is expressed in terms of 3 Toffoli gtes. Positive nd negtive ontrol lines of the Toffoli gtes re drwn s solid nd white dots, respetively. Fig. () relizes the sme output funtion, leit with Toffoli gte. Quntum iruits re desried in terms of smll lirry of gtes tht intert with one or two quits. One of the most frequently onsidered lirries is lled the so-lled Clifford+T gte lirry tht onsists of the reversile CNOT gte, the Hdmrd gte, nd the T gte. The T -gte is suffiiently expensive in most pprohes to fult tolernt quntum omputing [3] tht it is ustomry to neglet ll other gtes when osting quntum lgorithm. Severl works from the literture desrie how to mp reversile gtes into Clifford+T gtes (see, e.g., [, 3, ]). Note tht iruits exist tht only require T gtes to pply Toffoli up to phse rottion on the trget [7]. While the ltter iruits n often e used in ple of stndrd Toffoli gte, they nnot lwys e used in this fshion. As suh, we fous on the 7 T -gte networks in our synthesis lgorithms. Consequently, our osts ould e pessimisti y ftor of s muh s 7/. Improvements to the deomposition of multiple-ontrolled Toffoli gtes into Clifford+T iruits hve n immedite positive effet on our proposed synthesis method.

3 Hierrhil Reversile Logi Synthesis Using LUTs DAC 7, June 8, 7, Austin, TX, USA y y 6 upper ound lower ound 3 5 dditionl lines x x x 3 () Order:,, 3,, 5 5 x x x () LUT network x x x y y x x x 5 () Order:,,, 5, 3 Figure 3: Simple LUT network to illustrte order heuristis (dshed lines in the single-trget gtes men tht the line is not input to the gte) 3 GENERAL IDEA AND MOTIVATION This setion illustrtes the generl ide on how to mp LUT networks into reversile iruits. For this purpose, tke look t the LUT network in Fig. 3(). The network onsists of 5 inputs x,..., nd 5 LUTs with nmes to 5. It hs two outputs, y nd y, whih funtions re omputed y LUT 3 nd LUT 5, respetively. A strightforwrd wy of trnslting the LUT into reversile iruit is y using one single-trget gte for eh LUT in topologil order. The trget of eh single-trget gte is -initilized new nill line. The reversile iruit in Fig. 3() up to the fifth gte results when pplying suh proedure. With these five gtes, the outputs y nd y re relized t line 8 nd of the reversile iruit. But fter these first five gtes, the reversile iruit hs grge outputs on lines 6, 7, nd 9 tht ompute the funtions of the inner LUTs of the network. The iruit must e free of grge outputs in order to e implemented on quntum omputer. This is euse the result of the lultion is entngled with the intermedite results nd so they nnot e disrded nd reyled without dmging the results they re entngled with [5]. We n unompute the intermedite results y re-pplying the single-trget gtes for the LUTs in reverse topologil order. This disentngles the quits, reverting them ll to onstnt s. In Fig. 3() the lst 3 gtes unompute intermedite results t lines 6, 7, nd 9. Bsed on this oservtion we derive the following lemm. Lemm 3.. When relizing LUT network with u gtes y reversile iruit tht uses single-trget gtes for eh LUT, we need t most u nill lines. But we n do etter. One we hve omputed primry output, we n unompute LUTs tht re not used ny longer y other outputs. The unomputed lines restore tht n e used insted of reting new nill. In the exmple of Fig. 3, we n first ompute output y nd then unompute LUTs nd, s they re not in the logi one of output y. The freed nill n e used for 3 x x x y y LUT size k Figure : The plot shows the upper nd lower ound on the numer of dditionl lines when synthesizing 6-it floting point dder from LUT network with LUT size k =,..., 3 the single-trget gte relizing LUT 3. This oservtion leds to lemm providing lower ound. Lemm 3.. Given LUT network with m outputs, let l e the mximum one size over ll outputs. When relizing the LUT network y reversile iruit tht uses single-trget gtes for eh LUT, we need t lest l nill lines. Tht is, we strt y synthesizing iruit for the output with the mximum one. Let s ssume tht this one ontins l LUTs. They n e synthesized using l single-trget gtes. From these l gtes, l gtes n e unomputed (ll exept the LUT omputing the output), nd therefore restores l lines whih hold onstnt vlue. We n esily see tht the ext numer of required lines my e it lrger, sine ll output vlues need to e kept. Further, we my wnt to mke use of logi shring nd use t most two single-trget gtes for eh LUT in the network. The role of the LUT size. As n e seen from the previous disussion, the numer of dditionl lines roughly orresponds to the numer of LUTs. Hene, we re interested in logi synthesis lgorithms tht minimize the numer of LUTs. Severl lgorithms n e found in the literture [7, 9,, 7]. In lssil logi synthesis the numer of LUT-inputs k needs to e seleted ording to some trget rhiteture. For exmple in FPGA mpping, its vlue is typilly 6 or 7. But for our lgorithm, we n use k s prmeter tht trdes off the numer of quits to the numer of T gtes: If k is smll, one needs mny LUTs to relize the funtion, ut the smll numer of inputs lso limits the numer of ontrol lines in the Toffoli gtes otined from ESOP-sed synthesis. And when k is lrge, one needs fewer LUTs ut the resulting Toffoli gtes re lrger nd therefore require more T gtes. Further, sine for lrger k the LUT funtions re getting more omplex, the runtime potentilly inreses s ESOP deomposition is eoming more diffiult. To illustrte the influene of the LUT size we performed the following experiment, illustrted in Fig.. We pplied re-oriented LUT mpping using ABC s [6] ommnd if -K k - for k =,..., 3 to 6-it floting point dder. The lue line ( ) shows the upper ound ording to Lemm 3. nd the red line (+) shows the lower ound ording to Lemm 3.. First, it n e noted tht the ounds re very lose to eh other. The reson n e tht the tehnology mpping lgorithm is effiient in finding shred logi. Seond, it

4 DAC 7, June 8, 7, Austin, TX, USA M. Soeken et l. n e seen tht for smll vlues of k, up to k = 6, the numer of dditionl lines n e redued signifintly. Afterwrds, one gins smller enefit from inresing the ut size. However, for k = 3 nd k = 3, the numer of lines n gin e signifintly redued. In ft, for k = 3, eh output n e represented y single LUT sine the dder hs 3 inputs. IMPLEMENTATION The outer struture of the synthesis lgorithm is simple. It tkes s input Boolen logi network N = (V, A, F ), nd outputs numer of lines l of the reversile iruit, nd sequene S of opertions. The lgorithms mnges mp m : G {,...,l} tht keeps trk of whih LUT results re omputed y whih lines. The opertions re PI(x, i) with n input x X nd line i [l]. This ssigns the input x to line i in the iruit. PO(y, i) with n output y Y nd line i [l]. This ssigns the output y to line i in the iruit. COMP(д, i) with gte д G nd line i [l]. This pplies single-trget gte T F (д) ({m(j) j fnin(д)}, i) nd sets m(д) i. UCOMP(д, i) with gte д G nd line i [l]. This ehves s COMP(д, i) ut sets m(д). Exmple.. The synthesis sequene to produe the iruit in Fig. 3() is PI(x, ),..., PI(, 5), COMP(, 6), COMP(, 7), COMP(3, 8), COMP(, 9), COMP(5, ), UCOMP(, 9), UCOMP(, 7), UCOMP(, 6), PO(y, 8), PO(y, ) Algorithm desries in detil how the synthesis sequene S is otined. The lgorithm keeps trk of the urrent numer of lines l, freed lines in stk C, nd LUT-to-line mpping m (lines 3). Also we hve referene ounter r (д) for eh LUT д tht llows us to hek when д n e unomputed. In line 5 nd, input nd output opertions re dded to S. In etween, in lines 6 3, opertions for omputing nd unomputing gtes re determined. Eh gte д is visited in topologil order. First, the gte д is omputed nd -initilized line is requested. Either there is one in C or we get new line y inrementing l. After COMP opertion for д is dded to S, we try to unompute the hildren reursively y lling unompute_hildren. In tht funtion, first the referene ounter is deremented for eh hild д. If tht leds to referene ount of, i.e., no other gte needs the omputed vlue of д, we unompute д nd dd the restored line to the stk C. With given topologil order of LUTs, the time omplexity of Algorithm is liner in the numer of LUTs. For the topologil order we first ompute the one for eh primry output nd order them y size in desending order. We perform topologil sort using depth-first serh for eh one nd do not inlude duplites when we visit eh one. 5 EXPERIMENTAL EVALUATION In the following we refer to our proposed lgorithm s LUT-sed Hierrhil Reversile Synthesis (LHRS). We hve implemented the lgorithm s ommnd lhrs on top of the reversile logi synthesis frmework RevKit [3]. All experiments hve een rried The soure ode n e found t githu.om/msoeken/irkit Input :Logi network N = (V = X Y G, A, F ) Output :Synthesis sequene S, numer of lines l set l ; initilize empty stk C; 3 initilize empty mp m; for д G do set r (д) d + (д); 5 for x X do dd PI(x, i) to S, set l l + ; 6 for д G in topologil order do 7 set t request_onstnt(c, l ); 8 dd COMP(д, t ) to S; 9 set m(д) t; if d + (д) = nd : y Y suh tht (д, y) A then unompute_hildren(g); end 3 end for y Y do dd PO(y, m(д)) to S suh tht (д, y) A; 5 return S, l; 6 funtion request_onstnt(c, l ) 7 if C is not empty then 8 return C.pop(); 9 else set l l + ; return l; end 3 funtion unompute_hildren(д, C) for д fnin(д) G do 5 set r (д ) r (д ) ; 6 if r (д ) = then 7 dd UCOMP(д, m(д )) to S; 8 C.push(m(д )); 9 unompute_hildren(д, C); 3 end 3 end Algorithm : Otining synthesis sequene out on n Intel Xeon CPU E5-68 v3 t.5 GHz with 6 GB of min memory running Linux. nd g 5.. More detils to the enhmrks of the pper nd further enhmrks n e found t quntumfpl.sttionq.om. As enhmrks we used Verilog netlists of severl rithmeti floting point designs in hlf (6-it), single (3-it), nd doule (6-it) preision. For synthesis ll Verilog files were trnslted into AIGs nd optimized for size using ABC s resyn sript. As seline we ompre our results to the stte-of-the-rt hierrhil reversile logi synthesis lgorithm presented in [8], referred to s CBS. CBS prtitions n AIG into sunetworks whih re then emedded into reversile funtions nd synthesized using symoli reversile synthesis lgorithms [9]. The size of the sunetworks n e ontrolled with threshold prmeter t. In our experiments we set t to, whih results in similr numer of dditionl lines ompred to LHRS with LUT size k = 6. It is importnt to note tht CBS does not unompute results nd produes grge outputs. The reported numers re sed on the iruits with grge lines, ut one n use the Bennett trik [5] to unompute ll grge lines. This trik requires to dd one nill for eh output nd doule the numer of T gtes. For CBS we report the numer of quits, n upper ound on the numer of T gtes ording to [], nd the runtime in seonds.

5 Hierrhil Reversile Logi Synthesis Using LUTs DAC 7, June 8, 7, Austin, TX, USA Tle : Experimentl results Benhmrk CBS [8] k = 6 mx k est k quits T gtes runtime LUTs quits T gtes runtime k LUTs quits T gtes runtime k LUTs quits T gtes runtime dd dd dd mp mp mp div div div exp exp invsqrt invsqrt invsqrt ln ln ln log log log mult mult mult reip reip reip sinos sinos squre squre squre sqrt sqrt sqrt su su su For LHRS, we used ABC s ommnd if -K k - to otin n re-optimized LUT network. Eh LUT is deomposed into multiple-ontrolled Toffoli gtes using ESOP-sed synthesis on ESOP expressions otined using ABC s ommnd &exorism [3]. We report sttistis out the resulting quntum iruits for three different LUT sizes. First, we report k = 6, s this is usully the LUT size t whih very lrge LUT ount redutions stop (see lso Fig. ). Seond, we report mximum k, lled mx k. We stop the synthesis either if we hve suessfully found reversile network sed on network with LUT size k = or we hit timeout limit of 5 dys. For lrge k, generting n initil ESOP over from LUT nd optimizing the over using exorism eomes the ottlenek. Consequently, the runtime typilly inreses when inresing k. By generting severl quntum iruits for different LUT sizes k, we otin set of Preto-optiml solutions. From these one n pik fvorle solution tht mthes onstrints, e.g., imposed y given rhiteture or quntum lgorithm. To illustrte this, we hve plotted the numer of quits nd T gtes for eh k for the 6-it dder in Fig. 5. As n exmple for piking est trdeoff, we hose the lrgest k efore the reltive inrese in T gtes is quintupled. In the exmple, of the dder, this sweet spot is k =, nd we refer to it s est k. We list these numers for ll enhmrks in the lst five olumns in the tle. Note tht for ll enhmrks with 6 inputs (exp-6, invsqrt-6, ln- 6, log-6, reip-6, sinos-6, squre-6, nd sqrt-6), the mximum nd est k is k = 6, euse then eh output is represented y extly one LUT nd the resulting networks do not need ny dditionl line to store temporry results. All single-trget gtes hve een mpped to Toffoli gtes using ESOP deomposition with exorism [3].

6 DAC 7, June 8, 7, Austin, TX, USA M. Soeken et l LUT size k quits T gtes Figure 5: The plot shows ll quntum iruit sttistis for the enhmrk dd-6 for LUT sizes k = 3,...,. The est LUT size n e found t. It n e seen tht LHRS finds quntum iruits with muh etter quits/t gtes trdeoff. Further, LHRS llows for etter seletion of results y using the LUT size s prmeter. One strong dvntge is tht in LHRS one n quikly otin skeleton for the finl iruit in terms of single-trget gtes tht lredy hs the finl numer of quits. If this numer mthes the design onstrints, one n strt the omputtionl more hllenging tsk of finding good quntum iruits for eh LUT funtion. Here, severl synthesis psses my e possile in order to optimize the result. Also postsynthesis optimiztion tehniques likely help to signfintly redue the numer of T gtes. 6 CONCLUSION We hve provided new LUT sed pproh to reversile iruit synthesis tht outperforms existing stte-of-the-rt hierrhil methods suh s CBS nd unlike suh pprohes provide networks tht re diretly pplile to quntum omputing. The enhmrks tht we provide give wht is t present the most omplete list of osts for elementry funtions for sientifi omputing. Aprt from simply showing improvements, these enhmrks provide ost estimtes tht llow quntum lgorithm designers to provide the first omplete ost estimtes for host of quntum lgorithms. This is n essentil step towrds the gol of understnding whih quntum lgorithms will e prtil in the first genertions of quntum omputers. While our work provides meningful step towrds mking funtion synthesis inexpensive for quntum omputing, onsiderle work remins. Two next steps re eminent. First, signifint ost improvements n e otined when using n ESOP deomposition tht tkes the T gtes of the orresponding Toffoli gtes into ount. Current ESOP deomposition optimizes with respet to the numer of produt terms, whih orresponds to the numer of Toffoli gtes without onsidering their different omplexities. Seond, LUT mpping lgorithm tht lnes the size of the output ones insted of the overll LUT ount n led to smller numer of quits. Aknowledgment. All iruits in this pper were drwn with the qpi tool []. This reserh ws supported y H-ERC-- ADG CyerCre, the Swiss Ntionl Siene Foundtion (-698 MAJesty), nd the ICT COST Ation IC5. REFERENCES [] N. Adessied, M. Amy, M. Soeken, nd R. Drehsler. Tehnology mpping of reversile iruits to Clifford+T quntum iruits. In ISMVL, pges 5 55, 6. [] L. G. Amrù, P. Gillrdon, nd G. De Miheli. Mjority-inverter grph: A new prdigm for logi optimiztion. IEEE TCAD, 35(5):86 89, 6. [3] M. Amy, D. Mslov, M. Mos, nd M. Roetteler. A meet-in-the-middle lgorithm for fst synthesis of depth-optiml quntum iruits. IEEE TCAD, 3(6):88 83, 3. [] R. Bush, D. W. Berry, I. D. Kivlihn, A. Y. Wei, P. J. Love, nd A. Aspuru- Guzik. Exponentilly more preise quntum simultion of fermions in seond quntiztion. New Journl of Physis, 8(3):333, 6. [5] C. H. Bennett. Logil reversiility of omputtion. IBM Jrnl. of Reserh nd Development, 7:55 53, 973. [6] R. K. Bryton nd A. Mishhenko. ABC: n demi industril-strength verifition tool. In Computer Aided Verifition, pges,. [7] D. Chen nd J. Cong. DAOmp: depth-optiml re optimiztion mpping lgorithm for FPGA designs. In Int Conf on CAD, pges ,. [8] B. D. Clder, B. C. Jos, nd C. R. Sprouse. Preonditioned quntum liner system lgorithm. Physil review letters, (5):55, 3. [9] J. Cong nd Y. Ding. FlowMp: n optiml tehnology mpping lgorithm for dely optimiztion in lookup-tle sed FPGA designs. IEEE TCAD, 3():, 99. [] A. De Vos nd Y. Vn Rentergem. Young sugroups for reversile omputers. Adv. Mth. Comm., ():83, 8. [] S. Denth, N. M. Linke, C. Figgtt, K. A. Lndsmn, K. Wright, nd C. Monroe. Demonstrtion of smll progrmmle quntum omputer with tomi quits. Nture, 536:63 66, 6. [] T. Drper nd S. Kutin. q pi : Creting quntum iruit digrms in TikZ. githu.om/qpi/qpi, 6. [3] K. Fzel, M. A. Thornton, nd J. E. Rize. ESOP-sed Toffoli gte sde genertion. In Pifi Rim Conferene on Communitions, Computers nd Signl Proessing, pges 6 9, 7. [] D. Große, R. Wille, G. W. Duek, nd R. Drehsler. Ext multiple-ontrol Toffoli network synthesis with SAT tehniques. IEEE TCAD, 8(5):73 75, 9. [5] A. W. Hrrow, A. Hssidim, nd S. Lloyd. Quntum lgorithm for liner systems of equtions. Physil review letters, 3(5):55, 9. [6] A. V. Himnshu Thpliyl, Hmid R. Arni. Comined integer nd floting point multiplition rhiteture (CIFM) for FPGAs nd its reversile logi implementtion. rxiv.org/s/s/69. [7] C. Jones. Low-overhed onstrutions for the fult-tolernt Toffoli gte. Physil Review A, 87():38, 3. [8] A. Kuehlmnn, V. Pruthi, F. Krohm, nd M. K. Gni. Roust oolen resoning for equivlene heking nd funtionl property verifition. IEEE TCAD, ():377 39,. [9] E. A. Mrtinez, C. A. Mushik, P. Shindler, D. Nigg, A. Erhrd, M. Heyl, P. Huke, M. Dlmonte, T. Monz, P. Zoller, nd R. Bltt. Rel-time dynmis of lttie guge theories with few-quit quntum omputer. Nture, 53:56 59, 6. [] D. Mslov. Advntges of using reltive-phse Toffoli gtes with n pplition to multiple ontrol Toffoli optimiztion. Phys. Rev. X, 93:3, 6. [] D. M. Miller, D. Mslov, nd G. W. Duek. A trnsformtion sed lgorithm for reversile logi synthesis. In DAC, pges 38 33, 3. [] A. Mishhenko, S. Cho, S. Chtterjee, nd R. K. Bryton. Comintionl nd sequentil mpping with priority uts. In Int Conf on CAD, pges 35 36, 7. [3] A. Mishhenko nd M. Perkowski. Fst heuristi minimiztion of exlusive sum-of-produts. In Int Reed-Muller Workshop,. [] T. D. Nguyen nd R. V. Meter. A resoure-effiient design for reversile floting point dder in quntum omputing. JETC, ():3: 3:8,. [5] M. A. Nielsen nd I. L. Chung. Quntum omputtion nd quntum informtion. Cmridge university press,. [6] P. J. J. O Mlley et l. Slle quntum simultion of moleulr energies. Phys. Rev. X, 6:37, 6. [7] S. Ry, A. Mishhenko, N. Eén, R. K. Bryton, S. Jng, nd C. Chen. Mpping into LUT strutures. In DATE, pges ,. [8] M. Soeken nd A. Chttopdhyy. Unloking effiieny nd slility of reversile logi synthesis using onventionl logi synthesis. In DAC, pges 9: 9:6, 6. [9] M. Soeken, G. W. Duek, nd D. M. Miller. A fst symoli trnsformtion sed lgorithm for reversile logi synthesis. In Reversile Computtion, pges 37 3, 6. [3] M. Soeken, S. Frehse, R. Wille, nd R. Drehsler. RevKit: A toolkit for reversile iruit design. Multiple-Vlued Logi nd Soft Computing, 8():55 65,. [3] M. Soeken, R. Wille, nd R. Drehsler. Hierrhil synthesis of reversile iruits using positive nd negtive Dvio deomposition. In Int Design nd Test Workshop, pges 3 8,. [3] N. Wiee nd M. Roetteler. Quntum rithmeti nd numeril nlysis using Repet-Until-Suess iruits. rxiv:6..