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1 Politenio i Torino Porto Institutionl Repository [Proeeing] Single-Event Upset nlysis n Protetion in High Spee Ciruits riginl Cittion: Hosseiny M., Lofti-Kmrn P., i Ntle G., i Crlo S., enso., Prinetto P. (26). Single- Event Upset nlysis n Protetion in High Spee Ciruits. In: IEEE th Europen Test Symposium (ETS), Southmpton (UK), 2-24 My 26. pp vilility: This version is ville t : sine: Jnury 27 Pulisher: IEEE Computer Soiety Pulishe version: I:.9/ETS.26.4 Terms of use: This rtile is me ville uner terms n onitions pplile to pen ess Poliy rtile ("Puli - ll rights reserve"), s esrie t html Porto, the institutionl repository of the Politenio i Torino, is provie y the University Lirry n the IT-Servies. The im is to enle open ess to ll the worl. Plese shre with us how this ess enefits you. Your story mtters. (rtile egins on next pge)

2 Single-Event Upset nlysis n Protetion in High Spee Ciruits Mohmm Hosseiny, Pejmn Lotfi-Kmrn, Giorgio i Ntle, Stefno i Crlo, lfreo enso, Polo Prinetto University of Tehrn, Irn. Politenio i Torino, Itly. {mohmm, plotfi}@.ee.ut..ir {giorgio.intle, stefno.irlo, lfreo.enso, polo.prinetto}@polito.it strt The effet of Single-Event Trnsients (s) (t omintionl noe of esign) on the system reliility is eoming ig onern for ICs mnufture using vne tehnologies. n t noe of omintionl prt my use trnsient pulse t the input of flip-flop n onsequently is lthe in the flip-flop n genertes soft-error. When n onjoine with trnsition t noe long ritil pth of the omintionl prt of esign, trnsient ely fult my our t the input of flip-flop. n the other hn, inresing pipeline epth n using low power tehniques suh s multi-level power supply, n multi-threshol trnsistor onvert lmost ll pths in iruit to ritil ones. Thus, stuying the ehvior of the in these kins of iruits nees speil ttention. This pper stuies the ynmi ehvior of iruit with mssive ritil pths in the presene of n. We lso propose novel flip-flop rhiteture to mitigte the effets of suh s in omintionl iruits. Furthermore, the propose rhiteture n tolernt Single Event Upset (SEU) use y prtile strike on the internl noes of flip-flop.. Introution Rition-inue soft errors pose mjor hllenge to the esign of memories n logi iruits in nnometer tehnologies. Neutron ritions from osmi rys or lph prtiles from pkging mterils re ommon uses of soft errors in the noes of iruit. These ritions generte onentrte ursts of exess hrges t rnom lotions in semionutor sustrte. These hrges my e ollete y p-n juntion resulting in urrent pulse of very short urtion in the signl vlue, usully terme Single-Event Upset (SEU). n SEU ours in the hol stte of memory ell or in flip-flop n uses soft error when the ontent of the storge element is flippe. Furthermore, n SEU my our in n internl noe of omintionl iruit n susequently e propgte to storge element n e lthe there. In this se, it is usully lle Single Event Trnsient (). Comintionl iruits hve nturl rrier to propgting s to their output. When n ours t n internl noe of logi iruit, there re three msking ftors tht hve impt on the : logil msking, temporl msking, n eletril msking []. In spite of these three msking mehnisms, n with enough mplitue my pper in the smpling winow of flip-flop in the iruit n n e lthe in the flip-flop. To eliminte erroneous results ue to this erroneously lthe t, lthes shoul protet themselves ginst these errors. s proess tehnology sles elow nnometers, stuies inite high-ensity, low-ost, high-performne integrte iruits, hrterize y high operting frequenies, low voltge levels, n smll noise mrgins will e inresingly suseptile to s n this will result in uneptle soft error filure rtes even in minstrem ommeril pplitions [], [2]. Severl reserhes stuy the soft-error use y prtile strike in the omintionl n sequentil prts of iruit. Some works propose lgorithms to estimte iruit vulnerility to n SEU/ wheres, the other works propose evie n iruit tehniques to protet iruit ginst the SEU/. Mohnrm [3] proposes omprehensive tehnique for simultion of trnsients use y s in omintionl logi iruits. se upon liner RC moels of gtes, the propose tehnique integrtes lose-form moel for omputtion of the -inue trnsient t the site of prtile strike with propgtion moels for the trnsients long funtionlly sensitize pth. Gill, et l. [4] introue n pproh for omputing soft error suseptiility of noes in lrge CMS iruits t the trnsistor level. Zho, et l. [6] propose noise impt nlysis methoology se on Noise Proility ensity Funtion (NPF) trnsformtion tehnique to evlute the iruit vulnerility to SEU. Krishnmohn, et l. [5] propose n error-msking esign tehnique for stti CMS omintionl iruits tht exploits the inherent temporl reunny (timing slk) of logi signls to inrese soft-error roustness. euse logi signls on the ritil pths o not hve resonle timing slk, this metho is not pplile to lthes in ritil pths of iruit whose ehvior in the event of n hs gret impt on the funtionlity of the iruit. lmost ll of these works stuy the n its impts on stey stte voltge levels. However, ynmi ehvior of signl in the presene of n shoul e stuie. When n is onjoine with trnsition (ynmi ehvior) on vlue of noe long ritil pth of the Proeeings of the Eleventh IEEE Europen Test Symposium (ETS 6) /6 $2. 26 IEEE

3 omintionl prt of esign, trnsient ely fult my our t the input of flip-flop. This pper stuies the ynmi ehvior of signls in iruit with mssive ritil pths in the presene of n. Note tht, exmining the histogrm of the ritil-pth elys for typil igitl lok revels tht only few pths re ritil or ner ritil n tht mny pth hve muh shorter elys [8]. ut, using some high spee n low power tehniques inreses the numer of ritil pths in the iruit. The pipeline epth is inresing to 5 or 2 in orer to ommote the spee inrese. Toy levels of logi in the ritil pth is more ommon n this numer is expete to e eresing further [9]. This eresing numers of gtes in the pipeline stges results in n inresing numer of ritil pths in the iruit. n the other hn, using multiple voltge supply [8], ynmi Voltge Sling (VS) [], n multiple threshol voltge trnsistor [8], some of the mjor low power tehniques, onvert lmost ll pths in the omintionl prt of the iruit to ritil ones. When trnsition t the internl noe long ritil pth synhronizes with n use y prtile strike, trnsient ely fult my e generte. When this trnsient ely fult ppers t the input of storge ell, it n e lthe in the storge element s soft error. We stuy the effet of in the ritil pths of iruit. We show tht prtile strike t noe on ritil pth my pper s n erroneous vlue t the input of flipflop in two shpes: trnsient pulse voltge, or trnsient ely fult. It shoul e note tht, eletril msking mehnism whih n ttenute trnsient pulse hs very low effet on trnsient ely. Furthermore, we propose new flip-flop rhiteture se on the lok gting tehniques to etet n orret the n SEU in iruit. The rest of this pper is orgnize s follows. The next setion introues the trnsient fult moel tht is use in this pper. Setion 3 esries the effet of n on voltge level of signls. The effet of n on ritil pth is expline in Setion 4. Setion 5 explins protetion mehnism n new flip-flop rhiteture to etet n orret the n SEU in igitl iruit. Setion 6 emonstrtes experimentl results. Finlly, onlusions re ppere in the lst setion. 2. Trnsient Fult Moel When high-energy neutrons (presente in terrestril osmi ritions) or lph prtiles (tht originte from impurities in the pkging mterils) strike sensitive noe in the CMS iruit, they generte ense lol trk of itionl eletron-hole pirs in the sustrte. In the se of CMS iruits, sensitive noe in the semionutor is the rin of the FF-trnsistors [4]. This itionl hrge is ollete y the rin of n FF trnsistor n urrent spike is ppere. The urrent spike n e represente t the evie level y urrent soure. Messenger [7] moels this trnsient urrent s oule exponentil injetion urrent: I inj ( t ) = Q e t τ e t τ 2 ( ) τ τ 2 where Q is the hrge (positive or negtive) eposite s result of the prtile strike, τ is the olletion timeonstnt of the juntion, n τ 2 is the ion-trk estlishment time-onstnt. In the rest of the pper, we will use this urrent moel. Using the pieewise liner pility of moeling signls in HSPICE, this pper moels this oule exponentil trnsient pulse urrent with pieewise liner signl to generte some experimentl results. Krnik, et l. [] show tht n SEU lsts out ps for.6um tehnology. In this pper, the mximum with of this τ. trnsient urrent pulse is shown y mx 3. Propgting n long pth Consier 2-input NN gte. The effet of prtile strike on NN gte is shown in Figure. When inputs n re t logi vlues n, respetively, trnsistors P n N2 re in their FF-stte, so their rins (i.e., noes p n n) re suseptile to prtile strike. The urrent soure I inj of Figure -II moels the effet of the prtile tht strikes the sensitive noe n. Figure -III n - IV show two ifferent effets on the output voltge. If the two inputs n re stle t logi vlues n, respetively, then trnsient pulse will pper on the output noe. If the input hnges uring the prtile strike, then n erly ege will our t the output noe. n erly ege my use soft-error in the ownstrem storge ells tht re on pth with propgtion ely less thn τ mx. Thus, if the propgtion ely of the pth is greter thn τ mx the erly ege nnot generte soft error. Noe n,p re sensetive (I) Truth tle of NN P2 N n N2 (II) Prtile hit to noe n P2 N n N2 Iinj (V) Prtile hit to noe p P p P p < τ mx (III) Trnsient pulse Iinj < τ mx (IV) Erly ege <τ mx (VI) Lte ege Figure Effet of trnsient urrent on the output voltge of NN gte Figure -V n -VI show the se of prtile tht hits the sensitive noe p. In this se, extr hrges in the noe p n inrese the ely of the NN gte while the input hnges uring the prtile strike (i.e., lte ege is ourre). If suh ely ours on ritil pth of the esign, it my use soft-error in the iruit. lte ege is lso lle trnsient ely. Proeeings of the Eleventh IEEE Europen Test Symposium (ETS 6) /6 $2. 26 IEEE

4 n the other hn, trnsient pulse use y prtile strike my e hnge when it propgtes long pth in the iruit. propgting trnsient pulse long pth my e mske, ttenute n propgte, onverte to n erly ege or lte ege, or even onverte to ynmi hzr. Figure 2 shows the five ifferent effets of trnsient pulse voltge generte t noe long its propgtion pth. If trnsient pulse rehes n input of gte (e.g., 2- input R gte), ut the other input is in the ontrolling stte (e.g., for R), the trnsient pulse will e ompletely mske n the output will e unhnge. Therefore, this will not use soft error (Figure 2-I). If trnsient pulse rehes n input of gte (e.g., 2-input R gte), ut the other input is in the non-ontrolling stte (e.g., for R gte), euse of the nwith limittion of the gte, n ttenute trnsient pulse will pper t the output of the gte (Figure 2-II). If trnsient pulse rehes n input of gte (e.g., R), while the other input hs trnsition, the trnsient pulse my e ttenute (Figure 2-III), onverte to n erly ege (Figure 2-IV), onverte to lte ege (i.e., ely, Figure 2-V), or onverte to ynmi hzr (Figure 2-VI). ynmi hzr onversion ttenutes the trnsient pulse with n inrese the hne of the eletril msking. Thus, we o not onsier this effet in the rest of the pper (I) Mske (II) ttenute n Propgte (III) ttenute n Propgte (IV) Erly ege (V) Lte ege Figure 2 propgtion mehnisms (VI) ynmi Hzr The effet of propgte trnsient pulse hs een stuie in severl works [3][4]. The erly n lte ege effets my hve erroneous effets on shortest n ritil pths of the iruit, respetively, s ely fult, whih next setion els with these issues. 4. Sensitive pths In this setion, we etermine the pths in whih erly n lte eges my le to soft error. First, we efine some terminologies tht re useful to etermine these sensitive pths. efinition : smpling winow (t sw ) is the time tht is oune y the setup time (t su ) n hol time (t h ) roun the tive lok ege of flip-flop (Figure 3-I). Lemm : n results in soft error if it ppers in the smpling winow of flip-flop. efinition 2: n erly ege sensitive pth is pth in whih n erly ege use y n my results in soft error. efinition 3: trnsient ely (lte ege) sensitive pth is pth in whih trnsient ely my le to soft error. therwise, the pth is lle trnsient ely insensitive. In other wors, trnsient ely never uses soft error in trnsient ely insensitive pth. efinition 4: -setup time (t s ) is the time tht the t input of storge ell must e vli efore the smpling winow so tht ny trnsient ely (lte ege) on the input of the storge ell nnot e lthe in the storge ell (Figure 3-I). CLCK t s t su t h t SW t h CLCK t s t SW t (T -t s -t su ) (I) (II) Figure 3 -setup time n -hol time Lemm 2: The -setup time is equl toτ mx (i.e., the mximum with of ). efinition 5: -hol time (t h ) is the time tht the t input of storge ell must remin stle fter the smpling winow so tht ny erly ege on the input of the storge ell nnot e lthe in the storge ell (Figure 3- I). Lemm 3: pth with propgtion ely less thn τ mx + t h is n erly ege sensitive pth. Lemm 4: pth is trnsient ely sensitive if its propgtion ely (t ) is greter thn T ( t s + t su ), where T is the perio of the lok (i.e., t > T ( ts + tsu )). In the next setion, we propose protetion mehnisms n orresponing flip-flop rhitetures to etet n orret the trnsient pulse, erly ege, n lte ege (trnsient ely) tht le to soft error in the flip-flop. 5. Protetion Mehnism To protet iruit ginst the erroneous erly ege, it is enough to inrese the propgtion of the shortest pth of the iruit toτ mx + th. This minimum-pth ely n e relize y ing uffers to shortest pths uring logi synthesis. Therefore, this proess introues ertin mount of power n re overhe. However, in some esign methoologies using multi-level voltge supply or multi threshol voltge logi n e use to gurntee this minimum pth ely suh tht the power onsumption ereses. In the sequel, we will nlyze smpling mehnism to protet flip-flop ginst trnsient pulse n trnsient ely in the omintionl prts of the iruit. For this purpose, we first investigte the possile fulty signls t the t input of the flip-flop tht my use soft error. Figure 4 shows ll the possile fulty signls t the input of flip-flop tht n rete n erroneous t in the flipflop. Signls of Figure 4- n - my our t the input of ll types of flip-flops in the esign (those t the en of trnsient ely sensitive pth n those t the en of other Proeeings of the Eleventh IEEE Europen Test Symposium (ETS 6) /6 $2. 26 IEEE

5 pths). Signls of Figure 4- n - my our only t the input of flip-flops tht re t the en of trnsient ely sensitive pth. protetion mehnism shoul etet these erroneous signls n orret the lthing vlue in the flip-flops with minimum re, time, n power overhe on the norml opertion of the iruit. () () () () < τ mx < τ mx <τ mx <τ mx Figure 4 Possile erroneous signls use y t the input of flip-flop In the sequel, we propose two -tolernt flip-flops for trnsient ely sensitive pths n trnsient ely insensitive pths of the esign. The propose rhitetures etet n orret the trnsient pulse n trnsient ely fult t the input of the flip-flop. Furthermore, for ompleteness of the protetion the propose rhitetures n lso protet flip-flops ginst possile SEU in the internl noes of the flip-flops. 5. Multiple smpling protetion metho Three-smpling sheme is onventionl pproh to etet the erroneous pulse t the input of flip-flop ([5]n []). Figure 5 shows three-smpling sheme to etet trnsient pulse. CLK n re the lok n t inputs of the flip-flop, respetively. Using three smples,, n, three-smpling sheme etets n orrets possile trnsient pulse on. To gurntee the orretness of this lgorithm, the time intervl etween eh two onseutive smples shoul e greter thn the mximum with of the trnsient pulse (i.e., Δ τ mx ). The first smple is lthe t Δ ( > τ mx ) time efore the rising ege of the lok. The seon smple is lthe t the rising ege of the lok. Finlly, the thir smple is lthe t Δ ( >τ mx ) fter the rising ege of the lok. In this sheme, will e selete s the efult output. If there is isrepny etween the first two smples, the thir smple (i.g., ) will e selete s the output. The first smple is lle voter smple, the seon smple is lle min smple, n the thir smple is lle riter smple. The mximum timing penlty of this metho in the presene of trnsient pulse is Δ. CLK Δ Δ (I) Trnsient Pulse (III) etetion n Corretion Logi Figure 5 Three-smpling sheme to etet n orret trnsient pulse Figure 6 shows the smpling metho to etet n orret trnsient pulse n ely. Using the three smples, Figure 6-III shows the logi to etet n orret the SEU t the input of flip-flop. lthough, this three smpling metho etet n orret the trnsient pulse n ely, it is sensitive to trnsient pulse tht my our while the thir vlue is smple. (I) Trnsient Pulse (II) Trnsient ely (III) etetion n Corretion Logi Figure 6 Three-smpling sheme to etet n orret trnsient pulse n trnsient ely fult Figure 7-I shows the filure se of the three-smpling sheme. se on the etetor n orretor logi of Figure 6-III, inste of the orret logi vlue the erroneous logi vlue is lthe in the vitim flip-flop. In this se, forth smple with Δ > τ mx ely fter the thir smple n solve the issue (Figure 7-II). Figure 7-III shows the etetor n orretor logi. In this iruit, the efult vlue is the min smple (i.e., smple). If trnsient pulse or ely is etete uring the smpling winow of the flipflop, the thir smple is selete n lthe in the flip-flop. The mximum timing penlty of this metho is 2 Δ. (I) Filure in TSM (II) Four Smpling (III) etetion n Corretion Logi Figure 7 Four-smpling sheme Note tht, in this se, new orret rising ege use y shortest pth to this vitim flip-flop shoul not interfere with the trnsient ely. therwise, the fourth smple my use n inorret vlue lthe in the flip-flop; so, in this se, -hol time shoul e greter thn 2 Δ (i.e., t h > 2 Δ ). In the next setion, we propose two rhitetures to implement the propose smpling methoologies. Proeeings of the Eleventh IEEE Europen Test Symposium (ETS 6) /6 $2. 26 IEEE

6 5.2 Propose struture n rhiteturl or iruit tehnique for implementing the propose smpling methos shoul onsier the following esign issues: n SEU tolernt: It shoul implement the three or four smpling metho to eliminte ll possile or SEU in the omintionl n sequentil prts. Power, time, n re overhe: euse the rre ourrene of SEU/, the propose tehniques n strutures introue low power, time n re overhe in the norml opertion of the iruit. Prmeter vritions: Prmeter vritions (use y lol or glol proess vrition, or environmentl effets) in eep-sumiron esign my unertin the ely in esign. Furthermore, these vritions my e t epenent. In other wors, these vritions my revel their worst-se impt on iruit performne only uner ertin t sequene. Thus, fining the sensitive pths eome iffiult uner these unertinly. Furthermore, s result of the proess n of the environmentl vritions, the lok signl my hve oth skew (sptil vrition) n jitter (temporl vrition). The orretness of the propose struture in present of these issues shoul e gurntee. For the ske of riefly n lrity, this pper fouses on the first two issues. However, some short solutions re propose for the other issues. 5.3 /SEU tolernt flip-flop Reusing the present test strutures (e.g., sn flip-flops) in iruit to ope with n SEU issues my e promising tehnique to propose n optimum (low power, time, n re overhe) /SEU tolernt struture. Using sn lthes in prllel with system lthes is eoming n effiient wy to hnle ifferent prolems uring test n eug of iruit ([2] n [3]). Shrifi, et l. [2] propose seletive trigger sn rhiteture me of two prts (system prt n test prt) to reue the test t volume n test ynmi power onsumption. Kuppuswmy, et l. [3] propose miroproessor full hol-sn rhiteture tht omprises two istint iruits: system flip-flop n sn portion. This rhiteture is implemente in the 9nm Intel Pentium 4 proessor. Using the sn portion of these types of flip-flops, we implement the propose smpling methos to otin softerror tolernt flip-flop. Reusing sn prt flip-flop n using lok gting tehnique, Figure 8-I shows our propose rhiteture to etet trnsient pulse t the input of the flip-flop. The flipflop rhiteture onsists of three prts: system, sn, n protetion portions. Protetion portion onsists of three gtes (n XR, n N, n n inviter) n ely genertor. The loking sheme of the propose rhiteture is se on the pulse-flip-flops [8] n the loking signls re shown in Figure 9-I. Using ely genertor, the propose rhiteture smples the first two smples of Figure 5-I, simultneously (Figure 9-II). If there is isrepny etween smples n the thir smple (i.e., ) is lthe s the output of the flip-flop. _ely 4 C4 4 C4 C Lth L Lth PH2 C Lth L Lth PH2 6 2 C2 6 3 C3 6 2 C2 6 3 C3 Lth L Lth PH Lth L Lth PH Sn portion System flip-flop (I) For trnsient ely insensitive pths Sn portion Protetion portion Protetion portion System flip-flop (II) For trnsient ely sensitive pths Figure 8 SEU/-Tolernt flip-flops When there is not ny t the input of the flip-flop, this flip-flop n lso tolerte n SEU in its internl noes uring its hol time, if the three smples,, n re ientil. To gurntee this equlity, t h shoul e grter thn τ mx. euse one noe my e upset, ny it-flip on or is orrete y noe. Furthermore, ny it-flip on noe oes not hnge the output of the flip-flop. This flipflop n e use on the trnsient ely insensitive pths. Figure 8-II shows our propose rhiteture to etet trnsient pulse n ely t the input of the flip-flop on the trnsient ely sensitive pth. The flip-flop rhiteture onsists of three prts: system, sn, n protetion portions. Protetion portion onsists of seven gtes n ely genertor. The loking sheme of the propose rhiteture is se on the pulse-flip-flops [8] n loking signls re shown in Figure 9-II, -III. Using ely genertor, the propose rhiteture smples the first two smples of Figure 7-II, simultneously (Figure 9-II, -III)). If there is isrepny etween smples n the thir smple (i.e., ) is lthe s the output of the flip-flop. In S Q S Q Proeeings of the Eleventh IEEE Europen Test Symposium (ETS 6) /6 $2. 26 IEEE

7 ition, smple is lso lthe s the finl output if there is trnsient ely t the t input. This rhiteture n lso tolerte n SEU t its internl noe if t h > 2 Δ. The onition t h > 2 Δ, whih gurntees the etetion, is ompsse y onsiering minimum-pth length onstrint uring the esign proess. This minimumpth length n e relize y ing uffers to the shortest pth uring logi synthesis. Therefore, this proess introues ertin mount of power n re overhe. _ely 2Δ _ely 2Δ _ely (I) Trnsient pulse (II) Trnsient ely (III) Trnsient pulse Figure 9 Clok n t signls 6. Experimentl Results We hve implemente C++ progrm to etet the numer of flip-flops tht re fe y trnsient ely (lte ege) sensitive pths n erly ege sensitive pths. Tle shows some experimentl results otine y running the progrm on seven ISCS89 enhmrk iruits. We hve simulte these iruits y using, inputs. The ely of pths is ompute se on these inputs. The power onsumption is otine y omputing the numer of trnsitions in the iruits uring simultion. Tle verhes of the propose flip-flop Ciruit s298 s344 # LESP FF * 2.4% 53.3% # LESP_EESP FF * 5% re verhe 2.3% 23.5% s % 8% 2.7% 7.3% s526 9.% 9.8%.% s96 5.5% 8.3% 2.6% s % 3.% 4.5% s % % 2.6% 3.% * LESP FF = Flip-Flops on Lte Ege Sensitive Pths ** LESP_EESP FF = LESP Flip-Flops on Erly Ege Sensitive Pths 2Δ Power verhe 9.8% 7.5% The seon olumn of Tle shows the perentge of flip-flops tht re fe y trnsient ely fult sensitive pths. Column 3 shows the perentge of flip-flops of trnsient ely fult sensitive pth tht re lso on erly ege sensitive pths. The re overhe ue to pplying the propose flip-flop rhiteture is shown in Column 4. Finlly, the lst olumn shows the power overhe use y using flip-flop rhiteture in the norml opertion. Note tht, the power overhe onsists of the numer of extr trnsitions in the protetion n sn portions. The flip-flop rhiteture of Figure 8-(II) n etet types of ely fults tht re less thnτ mx. Thus the propose rhiteture n lso e use in n online ely testing senrio. This multipurpose testing of the propose rhiteture n justify its re overhe on some enhmrk iruits. 7. Conlusions This pper onsiers logi iruits with mny ritil pths; n stuies the effet of single event trnsient () use y prtile strike on the noes long the ritil pths. This pper shows three ifferent erroneous effets of n t the input of flip-flip: trnsient pulse, n erly ege n lte ege (trnsient ely). The pper lso proposes two flip-flop rhitetures to etet n orret these erroneous effets. Referenes [] T. Krnik, P. Hzuh, n J. Ptel, Chrteriztion of soft errors use y single event upsets in CMS proesses, IEEE Trns. epenility n Seure Computing, Vol., No. 2, 24, pp [2] S. Mitr, T. Krnik, N. Seifert, n M. Zhng, Logi soft errors in su-65nm tehnologies esign n C hllenges, 42n esign utomtion Conferene, C 5, 25, pp [3] K. Mohnrm, Simultion of trnsients use y singleevent upsets in omintionl logi, Interntionl Test Conferene (ITC 5), Nov. 25, pp [4]. S. Gill, C. Pphristou, F. G. Wolff, n N. Seifert, Noe sensitivity nlysis for soft errors in CMS logi, Interntionl Test Conferene (ITC 5), 25, pp [5] S. Krishnmohn, n N. R. Mhptr, high-effiieny tehnique for reuing soft errors in stti CMS iruits, Pro. IEEE Inter. Conf. Computer esign (ICC 4), t. 24, pp [6] C. Zho, X. i, n S. ey, stti noise impt nlysis methoology for evluting trnsient error effets in igitl VLSI iruits, Interntionl Test Conferene (ITC 5), Nov. 25, pp [7] G. C. Messenger, Colletion of hrge on juntion noes from ion trks, IEEE Trns. Nul. Si., 982, pp [8] J. M. Rey,. Chnrksn, n. Nikoli, igitl Integrte Ciruits, Person Eution, In. Upper Sle River, New Jersey 7458, 23. [9] V. G. klozij, Cloking in Multi-GHz Environment, in Pro. 23 r Inter. Conf. on Miroeletronis (MIEL 2), My 22, pp [] T. ur, T. Pering,. Strtkos, n R. roersen, ynmi voltge sle miroproessor system, in Pro. IEEE Int. Soli-Stte Ciruits Conf., 2, pp []. G. Mvis, n P. H. Eton, Soft error rte mitigtion tehniques for moern miroiruits, IEEE Pro. nnul Reliility Physis Sym., 24, pp [2] S. Shrifi, M. Hosseiny, n Zinlein Nvi, Reuing Power, Time n t Volume in SoC Testing Using Seletive Trigger Sn rhiteture, Interntionl Symposium on efet n Fult Tolerne in VLSI Systems (FT 23), 23,, pp [3] R. Kuppuswmy, P. esrosier,. Felthm, R. Sheikh, n P. Thikrn, Full hol-sn system in miroproessors: Cost/enefit nlysis, Intel Tehnology Journl, Vol. 8, No., Fe. 24; e/. Proeeings of the Eleventh IEEE Europen Test Symposium (ETS 6) /6 $2. 26 IEEE