ECE 545 Digital System Design with VHDL Lecture 1. Digital Logic Refresher Part B Sequential Logic Building Blocks

Transcription

1 ECE 545 igital System esign with VHL Lecture igital Logic Refresher Part B Sequential Logic Building Blocks

2 Lecture Roadmap Sequential Logic Sequential Logic Building Blocks Flip-Flops, Latches Registers, Shift Registers Counters RAM 2

3 Textbook References Sequential Logic Review Stephen Brown and Zvonko Vranesic, Fundamentals of igital Logic with VHL esign, 2 nd or 3 rd Edition Chapter 7 Flip-flops, Registers, Counters, and a Simple Processors ( , only) OR your undergraduate digital logic textbook (chapters on sequential logic) 3

4 Sequential Logic Building Blocks some slides modified from: Brown and Vranesic, Fundamentals of igital Logic with VHL esign, 2 nd Edition S. andamudi, Fundamentals of Computer Organization and esign 4

5 Introduction to Sequential Logic Output depends on current as well as past inputs epends on the history Have memory property Sequential circuit consists of Combinational circuit Feedback circuit Past input is encoded into a set of state variables Uses feedback (to feed the state variables) Simple feedback Uses flip flops 5

6 Introduction (cont d) Main components of a typical synchronous sequential circuit (synchronous = uses a clock to keep circuits in lock step) INPUT PRESENT STATE S(t) COMBINATIONAL LOGIC STATE-HOLING ELEMENTS (i.e. FLIP-FLOPS) OUTPUT NEXT STATE S(t+) CLOCK 6

7 State-Holding Memory Elements Latch versus Flip Flop Latches are level-sensitive: whenever clock is high, latch is transparent Flip-flops are edge-sensitive: data passes through (i.e. data is sampled) only on a rising (or falling) edge of the clock Latches cheaper to implement than flip-flops Flip-flops are easier to design with than latches In this course, primarily use flip-flops 7

8 Latch vs. Flip-Flop Latch transparent when clock is high Samples on rising edge of clock 8

9 Flip-Flop with Asynchronous Preset and Clear (a) Circuit Preset Clear (b) Graphical symbol Bubble on the symbol means active-low When preset =, preset to When preset =, do nothing When clear =, clear to When clear =, do nothing Preset and Clear also known as Set and Reset respectively In this circuit, preset and clear are asynchronous changes immediately when preset or clear are active, regardless of clock 9

10 Flip-Flop with Synchronous Clear Clear Clock CLEAR (asynchronous clear) (synchronous clear) Asynchronous active-low clear: immediately clears to Synchronous active-low clear: clears to on rising-edge of clock

11 Register (3) (3) (2) (2) 4 4 () () () () Clock In typical nomenclature, a register is a name for a collection of flip-flops used to hold a bus

12 Shift Register Sin 3 2 Clk (a) Circuit Clk Sin SHIFT REGISTER t Sin 3 2 = t t 2 t 3 t 4 t 5 t 6 t 7 (b) A sample sequence 2

13 Parallel Access Shift Register Parallel output 3 2 clock serial_in parallel_in 4 SHIFT REGISTER 4 output shift/load Serial input Shift/Load Parallel input Clock 3

14 Synchronous Up Counter enable load 2 3 carry 2 3 clock Enable (synchronous): when high enables the counter, when low counter holds its value Load (synchronous) : when load =, load the desired value into the counter Output carry: indicates when the counter rolls over 3 downto, 3 downto is how to interpret MSB to LSB 4

15 Random Access Memory (RAM) More efficient than registers for storing large amounts of data Can read and write to RAM Addressable memory SRAM dimensions are: (number of words) x (bits per word) SRAM Address is m bits, data is n bits 2 m x n-bit RAM Example: address is 5 bits, data is 8 bits 32 x 8-bit RAM Write Enable (WE) When set writing takes place at the next rising edge of the clock n m IN AR WE RAM OUT n 5

16 ual-port RAM Two sets of input ports {INA, ARA, WEA} {INB, ARB, WEB} n INA OUTA n Two corresponding outputs OUTA OUTB m ARA WEA One memory matrix n INB RAM OUTB n Possible operations: Read from two memory locations Write to two different memory locations Read from a memory location and write to a memory location (different or the same) m ARB WEB 6