# LATCHES & FLIP-FLOP. Chapter 7

Size: px
Start display at page:

## Transcription

1 LATCHES & FLIP-FLOP Chapter 7

2 INTRODUCTION Latch and flip flops are categorized as bistable devices which have two stable states,called SET and RESET. They can retain either of this states indefinitely making them useful for storage devices. The main difference between between latches and flip flops is in the method used for changing their states.

3 LATCHES The output of a latch depends on its current inputs and on its previous output and its change of state can happen at any time when its inputs change S-R (Set-Reset) Latch Gated S-R Latch Gated D Latch

4 FLIP FLOPS The output of a flip-flop also depends on current inputs and its previous output but the change of state occurs at specific times determined by a clock input Edge-Triggered Flip-Flop (S-R, J-K, D) Asynchronous Inputs

5 S-R LATCH

6 S-R LATCH

7 NEGATIVE-OR EQUIVALENT OF THE NAND GATE S -R LATCH SET state 0 When /R is LOW and /S is HIGH 1 0 Q is LOW and this Condition We call it RESET state 1

8 Example: Determine the waveform that will be observed on the Q output. Assume that Q is initially LOW

9 THE GATED S-R LATCH A gated latch requires an Enable input, EN (G is also used to designated an enable input). The S and R inputs control the state to which the latch will go when a HIGH level is applied to the EN input. The latch will not change until EN is HIGH. Initially RESET

10 TRUTH TABLE FOR GATED S-R LATCH S R EN Q Q Q Q Hold Q Q Hold Q Q Hold Q Q Hold Q Q Hold Set Reset not allowed

11 THE GATED D LATCH Only has one input in addition to EN. This input is called the D (data) input. -When the D input is HIGH and the EN input is HIGH, the latch will SET. -When the D input is LOW and EN is HIGH, the latch will RESET. -Another way, the output Q follows the input D when EN is HIGH Initially RESET

12 EDGE-TRIGGERED FLIP-FLOPS Edge-triggered S-R flip-flop Edge-triggered D flip-flop Edge-triggered J-K flip-flop

13 EDGE-TRIGGERED FLIP-FLOP LOGIC SYMBOLS (TOP: POSITIVE EDGE-TRIGGERED; BOTTOM: NEGATIVE EDGE- TRIGGERED).

14 Clock Signals & Synchronous Sequential Circuits 1 Clock signal 0 Rising edges of the clock (Positive-edge triggered) Falling edges of the clock (Negative-edge triggered) Clock Cycle Time A clock signal is a periodic square wave that indefinitely switches values from 0 to 1 and 1 to 0 at fixed intervals.

15 THE EDGE-TRIGGERED S-R FLIP- FLOP The S and R inputs of the S-R flip-flop are called synchronous input because data on these inputs are transferred to the flip-flop s output only on the triggering edge of the clock pulse. Operation

16 OPERATION OF A POSITIVE EDGE- TRIGGERED S-R FLIP-FLOP Example

17 Example: Determine the Q and Q output waveforms of the flip-flop (Assume is initially RESET)

18 Exercise: Determine the Q and Q output waveforms of the flip-flop (Assume is initially RESET) and it is a negative edge-triggered device

19 THE EDGE-TRIGGERED D FLIP-FLOP The D flip-flop is useful when a single data bit (1 or 0) is to be stored. Example

20 Example: Determine the Q output waveform if the flip-flop starts out RESET Try This: Determine the Q output for the D flip-flop if the D input is inverted

22 THE EDGE-TRIGGERED J-K FLIP- FLOP The J-K flip-flop is versatile and is widely used type of flip-flop. The difference is that he J-K flip-flop has no invalid state as does the S-R flip-flop. Example

23 Example: Determine the Q output, assuming that the flip-flop is initially RESET

24 Exercise: Determine the Q output, starting in the RESET state.

25 ASYNCHRONOUS PRESET AND CLEAR INPUTS The state of the flip-flop independent of the clock. The asynchronous inputs override the synchronous inputs. Active-LOW preset and clear inputs

26 Truth table of J-K flip-flop with Asynchronous inputs PRE CLR Q 0 0 INVALID (SET) (RESET) 1 1 SYNCRONOUS(clocked operation) These preset and clear inputs must both be kept HIGH for synchronous operation. When the PRE and the CLR inputs are used inputs J and K have no effect on the operation of the flip-flop. To use the flip-flop with synchronous inputs J-K, the PRE and the CLR inputs are set to logic 1. Setting PRE and the CLR to logic 0 is not allowed.

27 Example: Determine the Q output for the inputs shown in the timing diagram. Q is initially LOW. SET Toggle RESET

28 Exercise: Interchange the /PRE and /CLR waveforms, what will the Q output look like?

29 FLIP-FLOP APPLICATIONS Parallel Data Storage Frequency Division Counting

30 PARALLEL DATA STORAGE A common requirement in digital systems is to store several bits of data from parallel lines simultaneously in a group of flip-flops.

31 FREQUENCY DIVISION 2 n : n is number of flip-flops. Example: 2 flip-flop will divided frequency by 4 (2 2 )

32 Example: Develop the f out waveform for the circuit below when the 8 khz square wave input is applied to the clock input of flip-flop A

33 COUNTING The Q output of flip flop A clocks flip flop B. If Q A is taken as the least significant bit, a 2 bit sequenced is produced as the flip flop clocked. The binary sequence repeats every 4 clock pulses.

34 EXAMPLE Determine the output waveform in relation to the clock for Q A,Q B and Q C in the circuit below and show the binary sequence represented by these waveform.

### EMT 125 Digital Electronic Principles I CHAPTER 6 : FLIP-FLOP

EMT 125 Digital Electronic Principles I CHAPTER 6 : FLIP-FLOP 1 Chapter Overview Latches Gated Latches Edge-triggered flip-flops Master-slave flip-flops Flip-flop operating characteristics Flip-flop applications

### EKT 121/4 ELEKTRONIK DIGIT 1

EKT 121/4 ELEKTRONIK DIGIT 1 Kolej Universiti Kejuruteraan Utara Malaysia Bistable Storage Devices and Related Devices Introduction Latches and flip-flops are the basic single-bit memory elements used

### Name Of The Experiment: Sequential circuit design Latch, Flip-flop and Registers

EEE 304 Experiment No. 07 Name Of The Experiment: Sequential circuit design Latch, Flip-flop and Registers Important: Submit your Prelab at the beginning of the lab. Prelab 1: Construct a S-R Latch and

### CHAPTER 1 LATCHES & FLIP-FLOPS

CHAPTER 1 LATCHES & FLIP-FLOPS 1 Outcome After learning this chapter, student should be able to; Recognize the difference between latches and flipflops Analyze the operation of the flip flop Draw the output

### EET2411 DIGITAL ELECTRONICS

5-8 Clocked D Flip-FlopFlop One data input. The output changes to the value of the input at either the positive going or negative going clock trigger. May be implemented with a J-K FF by tying the J input

### Digital Circuits ECS 371

igital Circuits ECS 371 r. Prapun Suksompong prapun@siit.tu.ac.th Lecture 17 Office Hours: BK 3601-7 Monday 9:00-10:30, 1:30-3:30 Tuesday 10:30-11:30 1 Announcement Reading Assignment: Chapter 7: 7-1,

### Rangkaian Sekuensial. Flip-flop

Rangkaian Sekuensial Rangkaian Sekuensial Flip-flop Combinational versus Sequential Functions Logic functions are categorized as being either combinational (sometimes referred to as combinatorial) or sequential.

### Digital Fundamentals. Lab 5 Latches & Flip-Flops CETT Name: Date:

Richland College School of Engineering & Technology Rev. 0 B. Donham Rev. 1 (7/2003) J. Horne Rev. 2 (1/2008) J. Bradbury Rev. 3 (7/2015) J. Bradbury Digital Fundamentals CETT 1425 Lab 5 Latches & Flip-Flops

### Digital Fundamentals: A Systems Approach

Digital Fundamentals: A Systems Approach Latches, Flip-Flops, and Timers Chapter 6 Traffic Signal Control Traffic Signal Control: State Diagram Traffic Signal Control: Block Diagram Traffic Signal Control:

### Digital Systems Laboratory 3 Counters & Registers Time 4 hours

Digital Systems Laboratory 3 Counters & Registers Time 4 hours Aim: To investigate the counters and registers constructed from flip-flops. Introduction: In the previous module, you have learnt D, S-R,

### Introduction. NAND Gate Latch. Digital Logic Design 1 FLIP-FLOP. Digital Logic Design 1

2007 Introduction BK TP.HCM FLIP-FLOP So far we have seen Combinational Logic The output(s) depends only on the current values of the input variables Here we will look at Sequential Logic circuits The

### (CSC-3501) Lecture 7 (07 Feb 2008) Seung-Jong Park (Jay) CSC S.J. Park. Announcement

Seung-Jong Park (Jay) http://www.csc.lsu.edu/~sjpark Computer Architecture (CSC-3501) Lecture 7 (07 Feb 2008) 1 Announcement 2 1 Combinational vs. Sequential Logic Combinational Logic Memoryless Outputs

### YEDITEPE UNIVERSITY DEPARTMENT OF COMPUTER ENGINEERING. EXPERIMENT VIII: FLIP-FLOPS, COUNTERS 2014 Fall

YEDITEPE UNIVERSITY DEPARTMENT OF COMPUTER ENGINEERING EXPERIMENT VIII: FLIP-FLOPS, COUNTERS 2014 Fall Objective: - Dealing with the operation of simple sequential devices. Learning invalid condition in

### 5: Sequential Logic Latches & Flip-flops

5: Sequential Logic Latches & Flip-flops Introduction Memory Elements Pulse-Triggered Latch S-R Latch Gated S-R Latch Gated D Latch Edge-Triggered Flip-flops S-R Flip-flop D Flip-flop J-K Flip-flop T Flip-flop

### Digital Fundamentals

igital Fundamentals Tenth Edition Floyd Chapter 7 Modified by Yuttapong Jiraraksopakun Floyd, igital Fundamentals, 10 th 2008 Pearson Education ENE, KMUTT ed 2009 Summary Latches A latch is a temporary

### Experiment 8 Introduction to Latches and Flip-Flops and registers

Experiment 8 Introduction to Latches and Flip-Flops and registers Introduction: The logic circuits that have been used until now were combinational logic circuits since the output of the device depends

### The outputs are formed by a combinational logic function of the inputs to the circuit or the values stored in the flip-flops (or both).

1 The outputs are formed by a combinational logic function of the inputs to the circuit or the values stored in the flip-flops (or both). The value that is stored in a flip-flop when the clock pulse occurs

### RS flip-flop using NOR gate

RS flip-flop using NOR gate Triggering and triggering methods Triggering : Applying train of pulses, to set or reset the memory cell is known as Triggering. Triggering methods:- There are basically two

### RS flip-flop using NOR gate

RS flip-flop using NOR gate Triggering and triggering methods Triggering : Applying train of pulses, to set or reset the memory cell is known as Triggering. Triggering methods:- There are basically two

### Logic Design. Flip Flops, Registers and Counters

Logic Design Flip Flops, Registers and Counters Introduction Combinational circuits: value of each output depends only on the values of inputs Sequential Circuits: values of outputs depend on inputs and

### Review of Flip-Flop. Divya Aggarwal. Student, Department of Physics and Astro-Physics, University of Delhi, New Delhi. their state.

pp. 4-9 Krishi Sanskriti Publications http://www.krishisanskriti.org/jbaer.html Review of Flip-Flop Divya Aggarwal Student, Department of Physics and Astro-Physics, University of Delhi, New Delhi Abstract:

### Chapter 6. Flip-Flops and Simple Flip-Flop Applications

Chapter 6 Flip-Flops and Simple Flip-Flop Applications Basic bistable element It is a circuit having two stable conditions (states). It can be used to store binary symbols. J. C. Huang, 2004 Digital Logic

### SEQUENTIAL LOGIC. Satish Chandra Assistant Professor Department of Physics P P N College, Kanpur

SEQUENTIAL LOGIC Satish Chandra Assistant Professor Department of Physics P P N College, Kanpur www.satish0402.weebly.com OSCILLATORS Oscillators is an amplifier which derives its input from output. Oscillators

### Chapter. Synchronous Sequential Circuits

Chapter 5 Synchronous Sequential Circuits Logic Circuits- Review Logic Circuits 2 Combinational Circuits Consists of logic gates whose outputs are determined from the current combination of inputs. Performs

### The NOR latch is similar to the NAND latch

5-2 NOR Gate Latch The NOR latch is similar to the NAND latch except that the Q and Q outputs are reversed. The set and clear inputs are active high, that is, the output will change when the input is pulsed

### Engr354: Digital Logic Circuits

Engr354: igital Circuits Chapter 7 Sequential Elements r. Curtis Nelson Sequential Elements In this chapter you will learn about: circuits that can store information; Basic cells, latches, and flip-flops;

### Asynchronous (Ripple) Counters

Circuits for counting events are frequently used in computers and other digital systems. Since a counter circuit must remember its past states, it has to possess memory. The chapter about flip-flops introduced

### Other Flip-Flops. Lecture 27 1

Other Flip-Flops Other types of flip-flops can be constructed by using the D flip-flop and external logic. Two flip-flops less widely used in the design of digital systems are the JK and T flip-flops.

### Unit 11. Latches and Flip-Flops

Unit 11 Latches and Flip-Flops 1 Combinational Circuits A combinational circuit consists of logic gates whose outputs, at any time, are determined by combining the values of the inputs. For n input variables,

### CHW 261: Logic Design

CHW 26: Logic Design Instructors: Prof. Hala Zayed Dr. Ahmed Shalaby http://www.bu.edu.eg/staff/halazayed4 http://bu.edu.eg/staff/ahmedshalaby4# Slide Digital Fundamentals CHAPTER 7 Latches, Flip-Flops

### UNIT-3: SEQUENTIAL LOGIC CIRCUITS

UNIT-3: SEQUENTIAL LOGIC CIRCUITS STRUCTURE 3. Objectives 3. Introduction 3.2 Sequential Logic Circuits 3.2. NAND Latch 3.2.2 RS Flip-Flop 3.2.3 D Flip-Flop 3.2.4 JK Flip-Flop 3.2.5 Edge Triggered RS Flip-Flop

### Digital Logic Design Sequential Circuits. Dr. Basem ElHalawany

Digital Logic Design Sequential Circuits Dr. Basem ElHalawany Combinational vs Sequential inputs X Combinational Circuits outputs Z A combinational circuit: At any time, outputs depends only on inputs

### ELCT201: DIGITAL LOGIC DESIGN

ELCT201: DIGITAL LOGIC DESIGN Dr. Eng. Haitham Omran, haitham.omran@guc.edu.eg Dr. Eng. Wassim Alexan, wassim.joseph@guc.edu.eg Lecture 7 Following the slides of Dr. Ahmed H. Madian محرم 1439 ه Winter

### Introduction. Serial In - Serial Out Shift Registers (SISO)

Introduction Shift registers are a type of sequential logic circuit, mainly for storage of digital data. They are a group of flip-flops connected in a chain so that the output from one flip-flop becomes

### Chapter 5 Flip-Flops and Related Devices

Chapter 5 Flip-Flops and Related Devices Chapter 5 Objectives Selected areas covered in this chapter: Constructing/analyzing operation of latch flip-flops made from NAND or NOR gates. Differences of synchronous/asynchronous

### ECE 341. Lecture # 2

ECE 341 Lecture # 2 Instructor: Zeshan Chishti zeshan@pdx.edu October 1, 2014 Portland State University Announcements Course website reminder: http://www.ece.pdx.edu/~zeshan/ece341.htm Homework 1: Will

### Introduction to Sequential Circuits

Introduction to Sequential Circuits COE 202 Digital Logic Design Dr. Muhamed Mudawar King Fahd University of Petroleum and Minerals Presentation Outline Introduction to Sequential Circuits Synchronous

### Lecture 8: Sequential Logic

Lecture 8: Sequential Logic Last lecture discussed how we can use digital electronics to do combinatorial logic we designed circuits that gave an immediate output when presented with a given set of inputs

### Sequential Logic and Clocked Circuits

Sequential Logic and Clocked Circuits Clock or Timing Device Input Variables State or Memory Element Combinational Logic Elements From combinational logic, we move on to sequential logic. Sequential logic

### Flip-Flops and Related Devices. Wen-Hung Liao, Ph.D. 4/11/2001

Flip-Flops and Related Devices Wen-Hung Liao, Ph.D. 4/11/2001 Objectives Recognize the various IEEE/ANSI flip-flop symbols. Use state transition diagrams to describe counter operation. Use flip-flops in

### Logic Gates, Timers, Flip-Flops & Counters. Subhasish Chandra Assistant Professor Department of Physics Institute of Forensic Science, Nagpur

Logic Gates, Timers, Flip-Flops & Counters Subhasish Chandra Assistant Professor Department of Physics Institute of Forensic Science, Nagpur Logic Gates Transistor NOT Gate Let I C be the collector current.

### FLIP-FLOPS AND RELATED DEVICES

C H A P T E R 5 FLIP-FLOPS AND RELATED DEVICES OUTLINE 5- NAND Gate Latch 5-2 NOR Gate Latch 5-3 Troubleshooting Case Study 5-4 Digital Pulses 5-5 Clock Signals and Clocked Flip-Flops 5-6 Clocked S-R Flip-Flop

### ELCT201: DIGITAL LOGIC DESIGN

ELCT201: DIGITAL LOGIC DESIGN Dr. Eng. Haitham Omran, haitham.omran@guc.edu.eg Dr. Eng. Wassim Alexan, wassim.joseph@guc.edu.eg Lecture 6 Following the slides of Dr. Ahmed H. Madian ذو الحجة 1438 ه Winter

### Figure 30.1a Timing diagram of the divide by 60 minutes/seconds counter

Digital Clock The timing diagram figure 30.1a shows the time interval t 6 to t 11 and t 19 to t 21. At time interval t 9 the units counter counts to 1001 (9) which is the terminal count of the 74x160 decade

### Chapter 4. Logic Design

Chapter 4 Logic Design 4.1 Introduction. In previous Chapter we studied gates and combinational circuits, which made by gates (AND, OR, NOT etc.). That can be represented by circuit diagram, truth table

### Chapter 11 Latches and Flip-Flops

Chapter 11 Latches and Flip-Flops SKEE1223 igital Electronics Mun im/arif/izam FKE, Universiti Teknologi Malaysia ecember 8, 2015 Types of Logic Circuits Combinational logic: Output depends solely on the

### IT T35 Digital system desigm y - ii /s - iii

UNIT - III Sequential Logic I Sequential circuits: latches flip flops analysis of clocked sequential circuits state reduction and assignments Registers and Counters: Registers shift registers ripple counters

### D Latch (Transparent Latch)

D Latch (Transparent Latch) -One way to eliminate the undesirable condition of the indeterminate state in the SR latch is to ensure that inputs S and R are never equal to 1 at the same time. This is done

### Digital Logic Design I

Digital Logic Design I Synchronous Sequential Logic Mustafa Kemal Uyguroğlu Sequential Circuits Asynchronous Inputs Combinational Circuit Memory Elements Outputs Synchronous Inputs Combinational Circuit

### A clock is a free-running signal with a cycle time. A clock may be either high or low, and alternates between the two states.

Clocks A clock is a free-running signal with a cycle time. A clock may be either high or low, and alternates between the two states. 1 The length of time the clock is high before changing states is its

### Sequential Logic Circuits

Sequential Logic Circuits By Dr. M. Hebaishy Digital Logic Design Ch- Rem.!) Types of Logic Circuits Combinational Logic Memoryless Outputs determined by current values of inputs Sequential Logic Has memory

### PGT104 Digital Electronics. PGT104 Digital Electronics

1 Part 5 Latches, Flip-flop and Timers isclaimer: Most of the contents (if not all) are extracted from resources available for igital Fundamentals 10 th Edition 2 Latches A latch is a temporary storage

### Synchronous Sequential Logic

Synchronous Sequential Logic -A Sequential Circuit consists of a combinational circuit to which storage elements are connected to form a feedback path. The storage elements are devices capable of storing

### Flip-Flops and Sequential Circuit Design

Flip-Flops and Sequential Circuit Design ECE 52 Summer 29 Reading ssignment Brown and Vranesic 7 Flip-Flops, Registers, Counters and a Simple Processor 7.5 T Flip-Flop 7.5. Configurable Flip-Flops 7.6

### CHAPTER 6 COUNTERS & REGISTERS

CHAPTER 6 COUNTERS & REGISTERS 6.1 Asynchronous Counter 6.2 Synchronous Counter 6.3 State Machine 6.4 Basic Shift Register 6.5 Serial In/Serial Out Shift Register 6.6 Serial In/Parallel Out Shift Register

### PRE J. Figure 25.1a J-K flip-flop with Asynchronous Preset and Clear inputs

Asynchronous Preset and Clear Inputs The S-R, J-K and D inputs are known as synchronous inputs because the outputs change when appropriate input values are applied at the inputs and a clock signal is applied

### Exercise 2: D-Type Flip-Flop

Flip-Flops Digital Logic Fundamentals Exercise 2: D-Type Flip-Flop EXERCISE OBJECTIVE When you have completed this exercise, you will be able to determine the characteristics of a D-type results with an

### ASYNCHRONOUS COUNTER CIRCUITS

ASYNCHRONOUS COUNTER CIRCUITS Asynchronous counters do not have a common clock that controls all the Hipflop stages. The control clock is input into the first stage, or the LSB stage of the counter. The

### DIGITAL ELECTRONICS MCQs

DIGITAL ELECTRONICS MCQs 1. A 8-bit serial in / parallel out shift register contains the value 8, clock signal(s) will be required to shift the value completely out of the register. A. 1 B. 2 C. 4 D. 8

### COSC 243. Sequential Logic. COSC 243 (Computer Architecture) Lecture 5 - Sequential Logic 1

COC 243 equential Logic COC 243 (Computer Architecture) Lecture 5 - equential Logic 1 Overview Last Lecture This Lecture equential logic circuits ource: Chapter 11 (10 th edition) Next Lecture Computer

### Chapter 8 Sequential Circuits

Philadelphia University Faculty of Information Technology Department of Computer Science Computer Logic Design By 1 Chapter 8 Sequential Circuits 1 Classification of Combinational Logic 3 Sequential circuits

### 3 Flip-Flops. The latch is a logic block that has 2 stable states (0) or (1). The RS latch can be forced to hold a 1 when the Set line is asserted.

3 Flip-Flops Flip-flops and latches are digital memory circuits that can remain in the state in which they were set even after the input signals have been removed. This means that the circuits have a memory

### CHAPTER 4: Logic Circuits

CHAPTER 4: Logic Circuits II. Sequential Circuits Combinational circuits o The outputs depend only on the current input values o It uses only logic gates, decoders, multiplexers, ALUs Sequential circuits

### More on Flip-Flops Digital Design and Computer Architecture: ARM Edition 2015 Chapter 3 <98> 98

More on Flip-Flops Digital Design and Computer Architecture: ARM Edition 2015 Chapter 3 98 Review: Bit Storage SR latch S (set) Q R (reset) Level-sensitive SR latch S S1 C R R1 Q D C S R D latch Q

### Flip-Flops. Because of this the state of the latch may keep changing in circuits with feedback as long as the clock pulse remains active.

Flip-Flops Objectives The objectives of this lesson are to study: 1. Latches versus Flip-Flops 2. Master-Slave Flip-Flops 3. Timing Analysis of Master-Slave Flip-Flops 4. Different Types of Master-Slave

### INTRODUCTION TO SEQUENTIAL CIRCUITS

NOTE: Explanation Refer Class Notes Digital Circuits(15EECC203) INTRODUCTION TO SEQUENTIAL CIRCUITS by Nagaraj Vannal, Asst.Professor, School of Electronics Engineering, K.L.E. Technological University,

### Digital Fundamentals: A Systems Approach

Digital Fundamentals: A Systems Approach Counters Chapter 8 A System: Digital Clock Digital Clock: Counter Logic Diagram Digital Clock: Hours Counter & Decoders Finite State Machines Moore machine: One

### Counters

Counters A counter is the most versatile and useful subsystems in the digital system. A counter driven by a clock can be used to count the number of clock cycles. Since clock pulses occur at known intervals,

### Review of digital electronics. Storage units Sequential circuits Counters Shifters

Review of digital electronics Storage units Sequential circuits ounters Shifters ounting in Binary A counter can form the same pattern of 0 s and 1 s with logic levels. The first stage in the counter represents

### Digital Circuit And Logic Design I. Lecture 8

Digital Circuit And Logic Design I Lecture 8 Outline Sequential Logic Design Principles (1) 1. Introduction 2. Latch and Flip-flops 3. Clocked Synchronous State-Machine Analysis Panupong Sornkhom, 2005/2

### Digital Circuit And Logic Design I

Digital Circuit And Logic Design I Lecture 8 Outline Sequential Logic Design Principles (1) 1. Introduction 2. Latch and Flip-flops 3. Clocked Synchronous State-Machine Panupong Sornkhom, 2005/2 2 1 Sequential

### Name: Date: Suggested Reading Chapter 7, Digital Systems, Principals and Applications; Tocci

Richland College Engineering Technology Rev. 0 B. Donham Rev. 1 (7/2003) J. Horne Rev. 2 (1/2008) J. Bradbury Digital Fundamentals CETT 1425 Lab 7 Asynchronous Ripple Counters Name: Date: Objectives: To

### COMP2611: Computer Organization. Introduction to Digital Logic

1 COMP2611: Computer Organization Sequential Logic Time 2 Till now, we have essentially ignored the issue of time. We assume digital circuits: Perform their computations instantaneously Stateless: once

### Final Exam review: chapter 4 and 5. Supplement 3 and 4

Final Exam review: chapter 4 and 5. Supplement 3 and 4 1. A new type of synchronous flip-flop has the following characteristic table. Find the corresponding excitation table with don t cares used as much

### Slide Set 7. for ENEL 353 Fall Steve Norman, PhD, PEng. Electrical & Computer Engineering Schulich School of Engineering University of Calgary

Slide Set 7 for ENEL 353 Fall 216 Steve Norman, PhD, PEng Electrical & Computer Engineering Schulich School of Engineering University of Calgary Fall Term, 216 SN s ENEL 353 Fall 216 Slide Set 7 slide

### COE 202: Digital Logic Design Sequential Circuits Part 1. Dr. Ahmad Almulhem ahmadsm AT kfupm Phone: Office:

COE 202: Digital Logic Design Sequential Circuits Part 1 Dr. Ahmad Almulhem Email: ahmadsm AT kfupm Phone: 860-7554 Office: 22-324 Objectives Sequential Circuits Memory Elements Latches Flip-Flops Combinational

### UNIVERSITI TEKNOLOGI MALAYSIA

SULIT Faculty of Computing UNIVERSITI TEKNOLOGI MALAYSIA FINAL EXAMINATION SEMESTER I, 2016 / 2017 SUBJECT CODE : SUBJECT NAME : SECTION : TIME : DATE/DAY : VENUES : INSTRUCTIONS : Answer all questions

### Chapter 5 Sequential Circuits

Logic and Computer Design Fundamentals Chapter 5 Sequential Circuits Part 2 Sequential Circuit Design Charles Kime & Thomas Kaminski 28 Pearson Education, Inc. (Hyperlinks are active in View Show mode)

### To design a sequential logic circuit using D-Flip-flop. To implement the designed circuit.

6.1 Objectives To design a sequential logic circuit using D-Flip-flop. To implement the designed circuit. 6.2 Sequential Logic So far we have implemented digital circuits whose outputs depend only on its

### Digital Networks and Systems Laboratory 2 Basic Digital Building Blocks Time 4 hours

Digital Networks and Systems Laboratory 2 Basic Digital Building Blocks Time 4 hours Aim To investigate the basic digital circuit building blocks constructed from combinatorial logic or dedicated Integrated

### Counter dan Register

Counter dan Register Introduction Circuits for counting events are frequently used in computers and other digital systems. Since a counter circuit must remember its past states, it has to possess memory.

### MC9211 Computer Organization

MC9211 Computer Organization Unit 2 : Combinational and Sequential Circuits Lesson2 : Sequential Circuits (KSB) (MCA) (2009-12/ODD) (2009-10/1 A&B) Coverage Lesson2 Outlines the formal procedures for the

### Computer Science 324 Computer Architecture Mount Holyoke College Fall Topic Notes: Sequential Circuits

Computer Science 324 Computer Architecture Mount Holyoke College Fall 2007 opic Notes: Sequential Circuits Let s think about how life can be bad for a circuit. Edge Detection Consider this one: What is

### Sequential Logic. E&CE 223 Digital Circuits and Systems (A. Kennings) Page 1

Sequential Logic E&CE 223 igital Circuits and Systems (A. Kennings) Page 1 Sequential Circuits Have considered only combinational circuits in which circuit outputs are determined entirely by current circuit

### CHAPTER 4: Logic Circuits

CHAPTER 4: Logic Circuits II. Sequential Circuits Combinational circuits o The outputs depend only on the current input values o It uses only logic gates, decoders, multiplexers, ALUs Sequential circuits

### Experiment # 9. Clock generator circuits & Counters. Digital Design LAB

Digital Design LAB Islamic University Gaza Engineering Faculty Department of Computer Engineering Fall 2012 ECOM 2112: Digital Design LAB Eng: Ahmed M. Ayash Experiment # 9 Clock generator circuits & Counters

### AIM: To study and verify the truth table of logic gates

EXPERIMENT: 1- LOGIC GATES AIM: To study and verify the truth table of logic gates LEARNING OBJECTIVE: Identify various Logic gates and their output. COMPONENTS REQUIRED: KL-31001 Digital Logic Lab( Main

### 6. Sequential Logic Flip-Flops

ection 6. equential Logic Flip-Flops Page of 5 6. equential Logic Flip-Flops ombinatorial components: their output values are computed entirely from their present input values. equential components: their

### ELE2120 Digital Circuits and Systems. Tutorial Note 7

ELE2120 Digital Circuits and Systems Tutorial Note 7 Outline 1. Sequential Circuit 2. Gated SR Latch 3. Gated D-latch 4. Edge-Triggered D Flip-Flop 5. Asynchronous and Synchronous reset Sequential Circuit

### DIGITAL SYSTEM FUNDAMENTALS (ECE421) DIGITAL ELECTRONICS FUNDAMENTAL (ECE422) LATCHES and FLIP-FLOPS

COURSE / CODE DIGITAL SYSTEM FUNDAMENTALS (ECE421) DIGITAL ELECTRONICS FUNDAMENTAL (ECE422) LATCHES and FLIP-FLOPS In the same way that logic gates are the building blocks of combinatorial circuits, latches

### VTU NOTES QUESTION PAPERS NEWS RESULTS FORUMS Registers

Registers Registers are a very important digital building block. A data register is used to store binary information appearing at the output of an encoding matrix.shift registers are a type of sequential

### Introduction to Microprocessor & Digital Logic

ME262 Introduction to Microprocessor & Digital Logic (Sequential Logic) Summer 2 Sequential Logic Definition The output(s) of a sequential circuit depends d on the current and past states of the inputs,

### Sequential Digital Design. Laboratory Manual. Experiment #3. Flip Flop Storage Elements

The Islamic University of Gaza Engineering Faculty Department of Computer Engineering Spring 2018 ECOM 2022 Khaleel I. Shaheen Sequential Digital Design Laboratory Manual Experiment #3 Flip Flop Storage

### CHAPTER1: Digital Logic Circuits

CS224: Computer Organization S.KHABET CHAPTER1: Digital Logic Circuits 1 Sequential Circuits Introduction Composed of a combinational circuit to which the memory elements are connected to form a feedback

### Sequential circuits. Same input can produce different output. Logic circuit. William Sandqvist

Sequential circuits Same input can produce different output Logic circuit If the same input may produce different output signal, we have a sequential logic circuit. It must then have an internal memory

### DIGITAL CIRCUIT COMBINATORIAL LOGIC

DIGITAL CIRCUIT COMBINATORIAL LOGIC Logic levels: one zero true false high low CMOS logic levels: 1 => 0.7 V DD 0.4 V DD = noise margin 0 =< 0.3 V DD Positive logic: high = 1 = true low = 0 = false Negative

### CS302 - Digital Logic Design FAQs By

CS302 - Digital Logic Design FAQs By For BCD numbers that add up to an invalid BCD number or generate a carry the number 6 (0110) is added to the invalid number, why? These binary numbers are not allowed

### Digital Fundamentals 11/2/2017. Summary. Summary. Floyd. Chapter 7. Latches

igital Fundamentals Tenth Edition Floyd hapter 7 2009 Pearson Education, Upper 2008 Pearson Saddle iver, Education N 07458. All ights eserved A latch is a temporary storage device that has two stable states