LATCHES & FLIPFLOP. Chapter 7


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1 LATCHES & FLIPFLOP Chapter 7
2 INTRODUCTION Latch and flip flops are categorized as bistable devices which have two stable states,called SET and RESET. They can retain either of this states indefinitely making them useful for storage devices. The main difference between between latches and flip flops is in the method used for changing their states.
3 LATCHES The output of a latch depends on its current inputs and on its previous output and its change of state can happen at any time when its inputs change SR (SetReset) Latch Gated SR Latch Gated D Latch
4 FLIP FLOPS The output of a flipflop also depends on current inputs and its previous output but the change of state occurs at specific times determined by a clock input EdgeTriggered FlipFlop (SR, JK, D) Asynchronous Inputs
5 SR LATCH
6 SR LATCH
7 NEGATIVEOR EQUIVALENT OF THE NAND GATE S R LATCH SET state 0 When /R is LOW and /S is HIGH 1 0 Q is LOW and this Condition We call it RESET state 1
8 Example: Determine the waveform that will be observed on the Q output. Assume that Q is initially LOW
9 THE GATED SR LATCH A gated latch requires an Enable input, EN (G is also used to designated an enable input). The S and R inputs control the state to which the latch will go when a HIGH level is applied to the EN input. The latch will not change until EN is HIGH. Initially RESET
10 TRUTH TABLE FOR GATED SR LATCH S R EN Q Q Q Q Hold Q Q Hold Q Q Hold Q Q Hold Q Q Hold Set Reset not allowed
11 THE GATED D LATCH Only has one input in addition to EN. This input is called the D (data) input. When the D input is HIGH and the EN input is HIGH, the latch will SET. When the D input is LOW and EN is HIGH, the latch will RESET. Another way, the output Q follows the input D when EN is HIGH Initially RESET
12 EDGETRIGGERED FLIPFLOPS Edgetriggered SR flipflop Edgetriggered D flipflop Edgetriggered JK flipflop
13 EDGETRIGGERED FLIPFLOP LOGIC SYMBOLS (TOP: POSITIVE EDGETRIGGERED; BOTTOM: NEGATIVE EDGE TRIGGERED).
14 Clock Signals & Synchronous Sequential Circuits 1 Clock signal 0 Rising edges of the clock (Positiveedge triggered) Falling edges of the clock (Negativeedge triggered) Clock Cycle Time A clock signal is a periodic square wave that indefinitely switches values from 0 to 1 and 1 to 0 at fixed intervals.
15 THE EDGETRIGGERED SR FLIP FLOP The S and R inputs of the SR flipflop are called synchronous input because data on these inputs are transferred to the flipflop s output only on the triggering edge of the clock pulse. Operation
16 OPERATION OF A POSITIVE EDGE TRIGGERED SR FLIPFLOP Example
17 Example: Determine the Q and Q output waveforms of the flipflop (Assume is initially RESET)
18 Exercise: Determine the Q and Q output waveforms of the flipflop (Assume is initially RESET) and it is a negative edgetriggered device
19 THE EDGETRIGGERED D FLIPFLOP The D flipflop is useful when a single data bit (1 or 0) is to be stored. Example
20 Example: Determine the Q output waveform if the flipflop starts out RESET Try This: Determine the Q output for the D flipflop if the D input is inverted
21 Answer for related question
22 THE EDGETRIGGERED JK FLIP FLOP The JK flipflop is versatile and is widely used type of flipflop. The difference is that he JK flipflop has no invalid state as does the SR flipflop. Example
23 Example: Determine the Q output, assuming that the flipflop is initially RESET
24 Exercise: Determine the Q output, starting in the RESET state.
25 ASYNCHRONOUS PRESET AND CLEAR INPUTS The state of the flipflop independent of the clock. The asynchronous inputs override the synchronous inputs. ActiveLOW preset and clear inputs
26 Truth table of JK flipflop with Asynchronous inputs PRE CLR Q 0 0 INVALID (SET) (RESET) 1 1 SYNCRONOUS(clocked operation) These preset and clear inputs must both be kept HIGH for synchronous operation. When the PRE and the CLR inputs are used inputs J and K have no effect on the operation of the flipflop. To use the flipflop with synchronous inputs JK, the PRE and the CLR inputs are set to logic 1. Setting PRE and the CLR to logic 0 is not allowed.
27 Example: Determine the Q output for the inputs shown in the timing diagram. Q is initially LOW. SET Toggle RESET
28 Exercise: Interchange the /PRE and /CLR waveforms, what will the Q output look like?
29 FLIPFLOP APPLICATIONS Parallel Data Storage Frequency Division Counting
30 PARALLEL DATA STORAGE A common requirement in digital systems is to store several bits of data from parallel lines simultaneously in a group of flipflops.
31 FREQUENCY DIVISION 2 n : n is number of flipflops. Example: 2 flipflop will divided frequency by 4 (2 2 )
32 Example: Develop the f out waveform for the circuit below when the 8 khz square wave input is applied to the clock input of flipflop A
33 COUNTING The Q output of flip flop A clocks flip flop B. If Q A is taken as the least significant bit, a 2 bit sequenced is produced as the flip flop clocked. The binary sequence repeats every 4 clock pulses.
34 EXAMPLE Determine the output waveform in relation to the clock for Q A,Q B and Q C in the circuit below and show the binary sequence represented by these waveform.
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