The Project & Digital Video. Today. The Project (1) EECS150 Fall Lab Lecture #7. Arjun Singh

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1 The Project & Digital Video EECS150 Fall Lab Lecture #7 Arjun Singh Adopted from slides designed by Greg Gibeling and Chris Fletcher 10/10/2008 EECS150 Lab Lecture #7 1 Today Project Introduction Good Design (Part 2) Interfaces and Handshaking Video Encoder Digital Video ITU-R BT.601/ITU-R BT.656 Video Encoder I 2 C Bus More Information 10/10/2008 EECS150 Lab Lecture #7 2 The Project (1) Digital Storage Oscilloscope Display audio as waveforms Stream audio from network audio or from a microphone Store audio stream Playback audio stream Trigger and freeze under different conditions Extra Credit A major part of this project Will augment checkpoints 3, 4 and 5 10/10/2008 EECS150 Lab Lecture #7 3 1

2 The Project (2) Checkpoints Require more design work than labs We re not telling you exactly what to do Part of your project Design them well Test them thoroughly! Don t lose your code Require more time 10/8/2004 EECS150 Lab Lecture #6 4 The Project (3) Checkpoint Roadmap Video Encoder SDRAM in Simulation SDRAM in Hardware + SDRAM Arbiter Waveform Generator + OScope features AC97 Audio Extra Credit Check calendar page and project spec for dates 10/10/2008 EECS150 Lab Lecture #7 5 Interfaces & Handshaking (1) Connect two modules with just wires No combinational logic Unidirectional Data-flow Source Sink 10/10/2008 EECS150 Lab Lecture #7 6 2

3 Interfaces & Handshaking (2) Handshaking Signals Valid (from Source) Ready (from Sink) Don t rely on timing assumptions 10/10/2008 EECS150 Lab Lecture #7 7 Interfaces & Handshaking (3) Data Transfer Synchronous When Ready and Valid are both high 10/10/2008 EECS150 Lab Lecture #7 8 Checkpoint #1: Video Encoder Video Encoder Sets up NTSC framing Blanking, SAV, EAV Request Data & Display it Test ROM Video Line & Pair Address 32b NTSC Video (No Blanking) Video Encoder 8b NTSC Video (Complete) ADV7194 Outgoing Video (S-Video Out Cable) Monitor 10/10/2008 EECS150 Lab Lecture #7 9 3

4 Digital Video (1) Pixel Array A digital image is represented by a matrix of pixels which include color information. Frames Motion is created by flashing a series of still frames SIF, 82 Kpx Video, 300 Kpx PC/Mac, 1 2 Mpx High-Definition Television (HDTV), 1 Mpx Workstation, 1 Mpx High-Definition Television (HDTV), 2 Mpx /10/2008 EECS150 Lab Lecture #7 10 Digital Video (2) Scanning Images are generated on the screen by scanning pixel lines, left to right, top to bottom Early CRTs required time to get from the end of a line to the beginning of the next. Therefore each line of video consists of active video portion and a horizontal blanking interval To reduce flicker, each frame is divided into two fields: odd and even 10/10/2008 EECS150 Lab Lecture #7 11 Digital Video (3) Colors Usually represented as red, green and blue In the digital domain we could transmit 8bits each for RGB. Transition from B&W Didn t want to break old TVs Added separate color or Chroma signals Y: Luma (Black and White) Cr: Chroma Red (New color signal) Cb: Chroma Blue (New color signal) 10/10/2008 EECS150 Lab Lecture #7 12 4

5 Digital Video (4) Chroma Subsampling Human eye is sensitive to Luma more than Chroma RGB 4:4:4 Y C R C B 4:4:4 4:2:2 (ITU-601) 4:2:0 (MPEG-1) 4:2:0 (MPEG-2) R 0 R 2 R 1 R 3 Y 2 Y 3 Y 2 Y 3 Y 2 Y 3 Y 2 Y 3 G 0 G 2 G 1 G 3 C B C B C B C B C B 0-1 C B 2-3 C B 0-3 C B 0-3 B 0 B 2 B 1 B 3 C R C R C R C R C R 0-1 C R 0-1 C R 0-3 C R /10/2008 EECS150 Lab Lecture #7 13 Administrative Info (1) Project Partners Talk to us ASAP if you don t have one SVN Repositories Chris will give introduction next Tuesday, 3:30-5:00pm (his OH time) Introduction will be audio-cast (Audio-cast guaranteed this time) 10/10/2008 EECS150 Lab Lecture #7 14 Administrative Info (2) Design Reviews Grading You have it or you don t Bring diagrams Schematic On a napkin Bubble-and-arc Block Diagrams NO VERILOG 10/10/2008 EECS150 Lab Lecture #7 15 5

6 C B 359 Y 718 C R 359 Y 719 C B 0 C R 0 C B 359 Y 718 C R 359 Y 719 C B 360 Y 720 C R 360 Y 721 C B 368(366) Y 736(732) C R 368(366) Y 855(861) C B 428(431) Y 856(862) C R 428(431) Y 857(863) C B 0 C R 0 NO DESIGN NO HELP 10/10/2008 EECS150 Lab Lecture #7 16 ITU-R BT.601 Formerly, CCIR-601. Designed for digitizing broadcast NTSC National Television System Committee Variations: 4:2:0 Chroma Subsampling PAL (European) version Component streaming: line i: C B Y C R Y C B Y C R Y line i+1: C B Y C R Y C B Y C R Y Effective Bits/Pixel: 4 components / 2 pixels = 32/2 = 16 bits/pixel Active Frame Size Frame Rate Scan Chroma subsampling Bits per component Effective bits/pixel 720 x /sec Interlaced 4:2:2 2:1 in X only Coincedent /10/2008 EECS150 Lab Lecture #7 17 ITU-R BT.656 (1) Details Pixels/Line: 858 Lines/Frame:525 Frames/S: Pixels/S: 13.5M Active Pixels/Line: 720 Lines/Frame:487 Blanking SAV/EAV: 4B/4B Black filler Luminance data, Y Chrominance data, C R Chrominance data, C B Last sample of digital active line Sample data for O H instant First sample of digital active line ( 732) (863) ( 366) ( 366) 0 1 Replaced by timing reference signal End of active video FIGURE 1 Composition of interface data stream Replaced by digital blanking data Timing reference signals Replaced by timing reference signal Start of active video Note 1 Sample identification numbers in parentheses are for 625-line systems where these differ from those for 525-line systems. (See also Recommendation ITU-R BT.803.) 10/10/2008 EECS150 Lab Lecture #7 18 D01 6

7 ITU-R BT.656 (2) Odd Field (262 Lines) Total: 262 Lines 16 Vertical Blanking 244 Active 2 Vertical Blanking Even Field Total: 263 Lines 17 Vertical Blanking 243 Active 3 Vertical Blanking 10/10/2008 EECS150 Lab Lecture #7 19 ITU-R BT.656 (3) P9 P8 P7 P6 P5 P4 P3 P2 1 b1 1 b1 1 b1 1 b1 1 b1 1 b1 1 b1 1 b1 1 b0 1 b0 1 b0 1 b0 1 b0 1 b0 1 b0 1 b0 1 b0 1 b0 1 b0 1 b0 1 b0 1 b0 1 b0 1 b0 1 b1 F V H E[3] E[2] E[1] E[0] F: Field Select (0: Odd, 1: Even) V: Vertical Blanking Flag H: EAV/SAV Flag (0: SAV, 1: EAV) E[3]=V^H, E[2]=F^H, E[1]=F^V, E[0]=F^V^H 10/10/2008 EECS150 Lab Lecture #7 20 Video Encoder (1) Analog Devices ADV7194 Supports ITU-R BT.601/656 S-Video and Composite Outputs I 2 C Control (We will give this to you) 10/10/2008 EECS150 Lab Lecture #7 21 7

8 Video Encoder (2) Signal Width Dir Description VE_P 10 O Outoing NTSC Video (Use {Data, 2 b00}) VE_SCLK 1 O I 2 C Clock (For Initialization) VE_SDA 1 O I 2 C Data (For Initialization) VE_PAL_NTSC 1 O PAL/NTSC Mode Select (Always 1 b0) VE_RESET_B_ 1 O Active low reset (~Reset) VE_HSYNC_B_ 1 O Manual Control (Always 1 b1) VE_VSYNC_B_ 1 O Manual Control (Always 1 b1) VE_BLANK_B_ 1 O Manual Control (Always 1 b1) VE_SCRESET 1 O Manual Control (Always 1 b0) VE_CLKIN 1 O Clock (27MHz, Just send Clock) 10/10/2008 EECS150 Lab Lecture #7 22 Video Encoder (3) Signal Width Dir Description Clock 1 I Clock input (27MHz) Reset 1 I Reset input Data 32 I Requested Data from ROM DataValid 1 I Data is valid this cycle DataReady 1 O The Video Encoder is ready to receive more data. If DataReady and DataValid are both high, the VideoEncoder should latch in Data on the next rising edge. AddressLine 9 O Line of Video ({Line[7:0], Field}) The ROM will return a pixel pair from this line. AddressPair 9 O Pair of Pixels. The line will return data for this pixel pair. AddressValid 1 O AddressLine and AddressPair are valid this cycle. AddressReady 1 I The sink connected to AddressLine/AddressPair is ready to receive those signals. 10/10/2008 EECS150 Lab Lecture #7 23 Video Encoder (4) General Video Encoder Block Diagram Test ROM Address Lines AddressReady AddressValid 32b NTSC Video (No Blanking) Address Counter Data Clip Address Counter H FSM V FSM Blank Control 32b Clipped YCrYCb (0x10 Data 0xF0) I 2 C Done Blank Gen (Mux) I 2 C Control IOReg I2C Clock & data I2C Clock & data 10b NTSC Video (Complete) ADV7194 Outgoing Video (S-Video Out Cable) Monitor VideoEncoder 10/10/2008 EECS150 Lab Lecture #7 24 8

9 Video Encoder (5) Basic Design Stream EAV, Blank, SAV, Active Lines Generate EAV/SAV/Blank using a mux Register output data (Timing reasons) Request Incoming Data Request it the cycle before you need it Must be clipped Minimum data is 0x10 Maximum data is 0xF0 Otherwise it will appear to be blanking signals 10/10/2008 EECS150 Lab Lecture #7 25 Video Encoder (6) Testing Test thoroughly Simulation is difficult with test ROM Try using values which count, so you can see it Design your testbench early Perhaps one partner should design the module, one should design the testbench Ensure that you test corner cases First and last lines Off-by-one errors in counters 10/10/2008 EECS150 Lab Lecture #7 26 I 2 C ADV7194 Initialization using I 2 C Requires only 2 wires Serial Data (Bidirectional) Clock (Driven by master) Runs at up to 400kHz Bidirectional Communication Given to you Complicated to get right Hard to debug 10/10/2008 EECS150 Lab Lecture #7 27 9

10 I 2 C (2) Physical Protocol Data Open collector bidirectional bus Driven by sender Clock Open collector unidirectional bus Driven by master May be pulled low to stall transmission Bidirectional Open Collector Bus Endpoint A Endpoint B 10kΩ Pullup 10kΩ Pullup DIn Enable DOut DIn Enable DOut 10/10/2008 EECS150 Lab Lecture #7 28 I 2 C (3) Protocol Start Condition Address Address Acknowledge Data Transfer Data Acknowledge Stop Condition 10/10/2008 EECS150 Lab Lecture #7 29 I 2 C (4) Arbitration Anyone can drive bus at any time No central arbiter No short circuits (Impossible in open collector) Decentralized Arbitration Check data bus against value you re sending Mismatch means someone else is transmitting So let them finish, and then try again Inherently gives preferences to accesses with more 1 b1s in them 10/10/2008 EECS150 Lab Lecture #

11 More Information Checkpoint Writeup Documents Page of the Website Video in a Nutshell ADV7194 Datasheet Complete ADV7194 reference ITU-R BT.656 & ITU-R BT.601 Standards Complete video standards I 2 C Bus Specification READ THE DATASHEETS! 10/10/2008 EECS150 Lab Lecture #