The Waveform Generator. Today. PAR Timing Reports (1) EECS150 Fall Lab Lecture #10. Chris Fletcher

Transcription

1 The Waveform Generator EECS150 Fall Lab Lecture #10 Chris Fletcher Adopted from slides designed by Chris Fletcher and Ilia Lebedev Today PAR Timing Reports Administrative Info The Waveform Generator Requirements Interfaces Extra Credit From our Sandbox to Yours Oscilloscope Features Firmware Miscellaneous Goodies PAR Timing Reports (1) Purpose Determine clock Slack Find where the critical path occurs PAR and Your Project No real clock problems yet Extra credit might lead to riding the clock Text Generation 1

2 PAR Timing Reports (2) Dealing with timing issues 1. Detecting a timing problem 2. See your exact clock slack 3. Finding your critical path 4. Nuking your critical path PAR Timing Reports (3) Step 1: Detecting the Problem Run Synthesis Watch PAR scroll by This is when PAR Done! appears PAR Report Resource Allocation Starting Placer Starting Router Timing Constraints PAR Timing Reports (4) A Normal Router Report A BAD Router Report 2

3 PAR Timing Reports (5) Having a bad critical path Increases PAR time Sometimes causes PAR to fail Makes your circuit completely unpredictable Corner case: ( ) trail to 0 Design initially wasn t meeting timing PAR fixed the problem Investigate when this happens You have a semi-serious timing problem PAR Timing Reports (6) Step 2: Find exact clock slack Bottom of PAR report ing slack reports Positive slack is good Negative slack Unpredictable circuits Be watchful! PAR might pass with negative slack PAR Timing Reports (7) Step 3: Find your critical path Use the Synplify Pro Technology Schematic Top toolbar: click Show Critical Path : 3

4 PAR Timing Reports (8) Step 4: NUKE your critical path Find module corresponding to critical path Refactor Verilog Pipeline design Remove Software operators * / If you don t know what it will synthesize to, don t write it in Verilog Administrative Info (1) Midterm 2 When: Tuesday, November 4 th During lecture: 2pm Where: 125 Cory Policy: Open notes, open book Midterm 2 Review Monday, November 3 rd Same place as always BYOQ Administrative Info (2) Project Due today: SDRAM Simulation Due Next Friday: Arbiter + Video Introduced today: Waveform Viewer Extra Credit is up! 4

5 Checkpoint 4 (1) Waveform Video Generator Up until now, we did all the design work for you. Now it s your turn. Much of this checkpoint is your design effort. Checkpoint 4 (2) Mode Input from switches Write Record Some Control Logic Waveform Source Write Write Arbiter Something Video Encoder Checkpoint 4 (3) Waveform Source generates data CP 5 will replace with a source of audio is recorded (Arbiter + SDRAM) Just like a GIGANTIC (256M) FIFO! is read out as needed is converted to a video stream How? Video Encoder displays the video. 5

6 Checkpoint 4 (4) What your system will be able to do: Record the output of the source Display the output on the screen in realtime Pause recording Examine recorded waveform Scroll forwards and backwards through saved waveform The Something Block (1) Takes a stream of values Outputs a video stream of a wave You will need to generate video on demand It would help to have a faster, smaller memory System Architects call this a Cache Look at RAM.v Hint Really. Look at RAM.v The Something Block (2) Displays a part of the waveform Draws one sample per pixel pair Displays data starting Frame of Video at Caching helps at at + N 6

7 The Something Block (3) Your output will look like: Be creative! Use colors! Did anyone say gradient? The Something Block (4) How you get there is entirely up to you Use good design Don t code if you don t have a circuit diagram! You won t need a state machine Make it look nice this is where it will show. Something Waveform source Done for you. Connects to the Arbiter Creates waveform data Multiple modes or patterns generated

8 Arbiter And SDRAM Should have this by now (was CP2, CP3) If not, we will provide a blackboxed solution. If you could not finish CP3, move on and finish after your project is done. Write Write Arbiter Control logic User interactions are handled here This can be a state machine This module will read user input Buttons Switches And control your data path Counter & Record are control signals Video Encoder This was your CP1 assignment. Should provide an interface to connect to 2 FIFOs Yes, DATA has a FIFO interface too If your VE does not work: Move on and finish after CP5 Use our blackboxed solution for now 8

9 Useful Hints (1) Don t bother using things like Debouncer.v on the button inputs We don t care about precise scrolling Look at the SVN Library folder closely Many useful modules Look at RAM.v Useful Hints (2) How many ports does RAM.v have? How can you use multi-port memory to your advantage? Waveform data is a set of values over time Video is a set of X,Y color values In a waveform, time is X and the value is Y. Checkpoint 4 Checkoff This checkpoint will be checked off visually We will look at what it does and how Talk to your GSIs! We are happy to help you with the design process Part of your grade will be the quality of your design 9

10 Extra Credit (1) Specification Online! October 26 th November 26 th Due with final check-off For more logistics the spec (see the website) Extra Credit (2) Think Design, not Display Extra Credit graded on design Ask yourself Was it well designed? Did it work reliably? Did it do something interesting? Flashing Colors!= good design (not necessarily anyway) Extra Credit (3) Extra Credit Options Oscilloscope Features Firmware Special Challenges Pick what you like No restrictions on selection Options will be added to the list as we think of them 10