A. Chatterjee, Georgia Tech

Transcription

1 VALIDATION, TESTING AND TUNING OF MIXED-SIGNAL/RF CIRCUITS AND SYSTEMS: A MACHINE LEARNING ASSISTED APPROACH A. Chatterjee, Georgia Tech GRAs: S. Deyati, B. Muldrey, S.Akbay, V. Natarajan, R. Senguttuvan, S. Sen, R. Voorakaranam, S. Cherubal, P. Variyam, S. Chakrabarti, D. Han and X. Wang Ack: SRC, Intel Corp, NSF and MARCO-DARPA 1

2 Background: Mixed-Signal/RF Systems Pre silicon design validation Post-manufacture testing and tuning Machine learning Post-silicon validation 2

3 State of the Art in Test: Mixed-Signal SoCs Specification Tests Each test requires a different setup Total testing time ATE complexity Load board complexity Test cost up 30%- 45% * Fabrication 25% Test 45% V offset I bias Noise Z in Gain BW I short Datasheet Test#1 Test#N Start Initialization Setup Instruments Stimulus Wait Measure Setup Instruments Stimulus Wait Measure Design 30% * R. Tummala, Fundamentals of Microsystems Packaging, Stop 3

4 NH 346C Standard Specification Tests PSA - E4440A GPIB (d) Custom Automation Software written In Agilent VEE PSG - E4438C VNA 8720ES GPIB GPIB GPIB-to-USB 82357A 541 ICs 13 specifications 7 test setups SG 8657ES Power Supplies (b) Relay board LO Filter NI-DAQ 14 relay controls (c) Relay driver board (a) Socket Interface Board Custom designed Socket Board Relay Board Relay Driver Board Control Software 8-bit control 4

5 Key Issues: Manufacturing test time: Relay settling time (ms) >> actual test time (usec)! Test multiple specs. Built-in test of complex specifications: Difficult to place test instruments and circuitry onchip for multiple specifications! Post-manufacture and field performance tuning: Tune multiple specs while minimizing power? Need to tune devices without extended test costs.

6 Alternate Tests: Key Principles The mapping S=f(M) is derived using nonlinear regression (multiple adaptive regression splines: MARS)

7 Signature Test Methodology Signal generator Pass/Fail decision Test specification values Transient/AC/ DC test stimulus DUT Regression models for transforming to test specifications Analog test responses from test points: sampling and digitization Defect filter

8 Test Stimulus Generation Test Stimulus Circuit-under-test C1 m1 m2 m3 R1 R2 Measurements S2 o o d s = S-S* Optimize x(t) Process statistics DC Gain Bandwidth Specifications S1 Test Generation: Maximize statistical correlation between measurements and specifications

9 Stimulus Search Best fitness value in a generation Mean fitness value in a generation RF Freq & Power Budget Engineer Discrete Freq & Amp. Divide Space Into Ranges 125M 1 135M 145M 146M MHz 3 166M 155M 167M 156M M 176M 188M 177M 6 Ranges 7 197M 209M 198M Genetic Algorithm 208M M 218M 230M 219M M 250 MHz 250M Migration Search Time Required Decades Years Months Weeks Days Generations 9

10 >3X test time reduction TI Precision Opamp

11 Alternate Test: Performance

12 Capability Study (Guardbands) For most specs, identical or better guardbands resulted

13 Hysteretic Buck Converter 100 chips (LM3485) SW1 and SW2 in positions 2 for proposed test and position 1 for conventional test

14 Signature-BIST: Overview Test Stimulus RF to lowfrequency conversion Test Response Ref: Variyam, Chatterjee, TCAD 2000

15 Optimized Diagnostic Tests Orthogonal tones Non-orthogonal tones Time domain test stimulus

16 Signature Based Model Parameter Estimation Ability to diagnose parameters of embedded modules!

17 Tuning: Learning Driven Tuning Architecture Supervised Learning Ability to tune for multiple specs using single data acquisition Ability to perform near optimal tuning Minimal on-chip hardware overhead

18 Learning driven tuning algorithms DUT RF out DSP processor V DD L o C c RF out Test Stimulus Ibias Feature extractor Spec. prediction Digital control Optimization V bias_lna RF in Lg Ls M2 M1 RF sensor Need accurate learning algorithms! RF Sensor Test Output

19 Learning driven tuning algorithms Self-healing LNA! 70% to 99% yield improvement

20 Experimental Results: Full Receiver Nominal Specs Gain IIP2 IIP3 Nominal 42.5 db dbm Lower bound 41.5 db dbm Upper bound 43.5 db dbm One-Instance (P1) Gain IIP2 IIP3 Before dBm - 8dBm -6 dbm After possible knob combinations (P1) for yield recovery Power conscious knob combination (P1) : W Converged Knob combination (P1) : W

21 Post-Silicon Challenges Models for design bugs are not known a-priori and must be detected, learned and diagnosis Need to automate generation of bug models using learning algorithms Diagnosed bugs must eventually be mapped to physical design parameters 21

22 Model Tuning

23 Test Stimulus Generation for Exposing Design Bugs Test setup Best stimulus

24 System Level Bug Learning Sparse Weiner learning kernel

25 Experimental Results: Maxim MAX2242 RF PA Captures hysteresis and memory effects automatically

26 Diagnosis of Static Design Bugs

27 PLL Experiments - System stimulated by summing LP signal at VCO input - System observed immediately prior to summing

28 PLL Experiment: Buggy VCO Output

29 Questions? 29