Broken Scan Chains Routinely Debugged with New Optical Technique
|
|
|
- Julius O’Connor’
- 5 years ago
- Views:
Transcription
![1 (at pin)] Presenters Logo V](/docs-images/89/100742397/images/1-8.jpg "ol g e- Broken Scan Chains")
1 t a m V OSCILLOSCOPE Design file: MSFT DIFF CLOCK WITH TERMINATORREV2.FFS Designer: Microsoft HyperLynx V8.0 Comment: 650MHz at clk input, J10, fixture attached Time (ps) Date: Wednesday Mar. 3, 2010 Time: 14:16:09 V [U3.1 (at pin)] Presenters Logo V ol g e- Broken Scan Chains Routinely Debugged with New Optical Technique C. Kardach, DCG Systems Inc. cathy_kardach@dcgsystems.com
2 Overview Status of LVI based scan chain debug LVx Architecture Scan chain map generation Fabless/foundry chain debug workflow Review: 40 nm stuck at case study Current work: transition failures Silicon Valley Test Conference
3 t a m V OSCILLOSCOPE Design file: MSFT DIFF CLOCK WITH TERMINATORREV2.FFS Designer: Microsoft HyperLynx V8.0 Comment: 650MHz at clk input, J10, fixture attached Time (ps) Date: Wednesday Mar. 3, 2010 Time: 14:16:09 V [U3.1 (at pin)] Presenters Logo V ol g e- Status of LVI-based scan chain debug
4 Status of LVI based chain debug Proof of concept on 40nm packaged parts (NVIDIA, 2010) 3 die for PFA; defect found on all 3 Yield ramp on 28nm packaged parts (NVIDIA, 2011) 47 die analyzed with LVI/LVP and sent for PFA To date PFA on 34 die and only 3 missed defect PFA success rate >90% Silicon Valley Test Conference
5 t a m V OSCILLOSCOPE Design file: MSFT DIFF CLOCK WITH TERMINATORREV2.FFS Designer: Microsoft HyperLynx V8.0 Comment: 650MHz at clk input, J10, fixture attached Time (ps) Date: Wednesday Mar. 3, 2010 Time: 14:16:09 V [U3.1 (at pin)] Presenters Logo V ol g e- LVx Architecture
6 LVI 1 Laser voltage imaging Spectrum Analyzer target frequency RF Component LVI target frequency photodetector RF amplifier DC Component 1 DCG patents granted LSM (reflected) image Silicon Valley Test Conference
7 LVP Laser voltage probing Timing tool in software GUI LVI image can be used for optimal probe placement Trigger digital scope RF Component LSM (reflected) image photodetector RF amplifier DC Component Silicon Valley Test Conference
8 CAD to LSM to LVI registration Diffusion layers used for LSM to CAD alignment LVI & LSM images acquired simultaneously for 1 pixel accuracy LSM image with diffusion overlay LVI image with same overlay Silicon Valley Test Conference
9 Load cell bounding boxes Accurate overlay of scan flop bounding boxes critical Cell bounding boxes generated by design house using LEF/DEF LVI image with same overlay Silicon Valley Test Conference
10 t a m V OSCILLOSCOPE Design file: MSFT DIFF CLOCK WITH TERMINATORREV2.FFS Designer: Microsoft HyperLynx V8.0 Comment: 650MHz at clk input, J10, fixture attached Time (ps) Date: Wednesday Mar. 3, 2010 Time: 14:16:09 V [U3.1 (at pin)] Presenters Logo V ol g e- Scan chain map generation
11 LEF/DEF in the chip design flow LEF Library Exchange Format DEF Design Exchange Format Silicon Valley Test Conference
12 LEF/DEF Basics LEF is a library of cell types and their pins A Y CK D Q QN INVX3 NAND4X4 DFFX2 DEF contains the cell placements and routing and annotation Silicon Valley Test Conference
13 Flop names are translated GDS viewer Silicon Valley Test Conference
14 t a m V OSCILLOSCOPE Design file: MSFT DIFF CLOCK WITH TERMINATORREV2.FFS Designer: Microsoft HyperLynx V8.0 Comment: 650MHz at clk input, J10, fixture attached Time (ps) Date: Wednesday Mar. 3, 2010 Time: 14:16:09 V [U3.1 (at pin)] Presenters Logo V ol g e- Fabless/foundry chain debug workflow
15 Fabless/foundry chain debug ATE identify No logic test chain fail? Yes ATE data log broken chain STIL file for chain generate physical map chain map LEF/DEF Foundry Design House Silicon Valley Test Conference
16 t a m V OSCILLOSCOPE Design file: MSFT DIFF CLOCK WITH TERMINATORREV2.FFS Designer: Microsoft HyperLynx V8.0 Comment: 650MHz at clk input, J10, fixture attached Time (ps) Date: Wednesday Mar. 3, 2010 Time: 14:16:09 V [U3.1 (at pin)] Presenters Logo V ol g e- 40 nm stuck-at case study
17 Case Study Introduction Chip is 40nm CMOS Graphics Processor Unit (GPU) The failure was identified on a production compressed shift pattern pattern through chain and looped Scan clock = 11 MHz Scan data = ¼ scan clock = 2.75 MHz Binary search on LVI data and clock images Silicon Valley Test Conference
18 Final images on 40nm case study data freq LVI signal degrades in #49 clock freq All flops have clock signal, even data-starved flops Silicon Valley Test Conference
19 Trace fan out in GDS 10 um 7.5 um Silicon Valley Test Conference
20 t a m V OSCILLOSCOPE Design file: MSFT DIFF CLOCK WITH TERMINATORREV2.FFS Designer: Microsoft HyperLynx V8.0 Comment: 650MHz at clk input, J10, fixture attached Time (ps) Date: Wednesday Mar. 3, 2010 Time: 14:16:09 V [U3.1 (at pin)] Presenters Logo V ol g e- Using LVx to debug transition failures >
21 2 nd harmonic finds transition failures Spectrum for input pattern of (50% duty cycle) Signal at data frequency No signal at 2 nd harmonic (2x data freq) Only odd harmonics are present at 50% duty cycle Spectrum for output (fail) pattern of (non- 50% duty cycle) Signal at data frequency Signal at 2 nd harmonic Even harmonics appear at non- 50% duty cycle Silicon Valley Test Conference
22 Transition failure debug strategy Probe scan chain output with LVP to verify the pattern has changed to Tune the spectrum analyzer to the 2 nd harmonic of the data frequency Continue binary search using LVI to find transition from dark flop (good) to bright flop (bad) Silicon Valley Test Conference
23 Transition failure method: results NVIDIA debugged 7 transition failures using LVx Transition failure case study to be presented at ISTFA 2011 in San Jose, CA: S Kasapi, W Lo, J Liao, B Cory, H Marks, Advanced scan chain failure analysis using laser modulation mapping and continuous wave probing. Silicon Valley Test Conference
24 Conclusion LVI based scan chain debug: highly successful in driving yield at 28nm Fabless/foundry data exchange: easily adoptable, based on open formats (LEF/DEF and GDS) LVI in 2011: moved beyond stuck at failures Broken Scan chain debug: transformed from very difficult to very easy due to LVx methodology Silicon Valley Test Conference
25 Acknowledgements Dr. Steven Kasapi invented modulation mapping, and now at NVIDIA has proven its effectiveness for scan chain fault isolation Dr. Joy Liao has been a key facilitator at NVIDIA in transitioning methodology to foundry yield operations Special thanks to NVIDIA managers that invested time and capital to make this technology a viable yield driver: Bruce Cory, DFx Manager, NVIDIA Howard Marks, Silicon FA Lab Manager, NVIDIA Silicon Valley Test Conference
Scan. This is a sample of the first 15 pages of the Scan chapter.
Scan This is a sample of the first 15 pages of the Scan chapter. Note: The book is NOT Pinted in color. Objectives: This section provides: An overview of Scan An introduction to Test Sequences and Test
Lecture 17: Introduction to Design For Testability (DFT) & Manufacturing Test
Lecture 17: Introduction to Design For Testability (DFT) & Manufacturing Test Mark McDermott Electrical and Computer Engineering The University of Texas at Austin Agenda Introduction to testing Logical
At-speed testing made easy
At-speed testing made easy By Bruce Swanson and Michelle Lange, EEdesign.com Jun 03, 2004 (5:00 PM EDT) URL: http://www.eedesign.com/article/showarticle.jhtml?articleid=21401421 Today's chip designs are
UNIT IV CMOS TESTING. EC2354_Unit IV 1
UNIT IV CMOS TESTING EC2354_Unit IV 1 Outline Testing Logic Verification Silicon Debug Manufacturing Test Fault Models Observability and Controllability Design for Test Scan BIST Boundary Scan EC2354_Unit
Through Silicon Via Testing Known Good Die (KGD) or Probably Good Die (PGD) Doug Lefever Advantest
Through Silicon Via Testing Known Good Die (KGD) or Probably Good Die (PGD) Doug Lefever Advantest Single Die Fab Yield will drive Cost Equation. Yield of the device to be stacked 100% 90% 80% Yield of
Unit V Design for Testability
Unit V Design for Testability Outline Testing Logic Verification Silicon Debug Manufacturing Test Fault Models Observability and Controllability Design for Test Scan BIST Boundary Scan Slide 2 Testing
Using on-chip Test Pattern Compression for Full Scan SoC Designs
Using on-chip Test Pattern Compression for Full Scan SoC Designs Helmut Lang Senior Staff Engineer Jens Pfeiffer CAD Engineer Jeff Maguire Principal Staff Engineer Motorola SPS, System-on-a-Chip Design
Extending the Usable Range of Error Vector Magnitude Testing
t a m V- 3000.0 2500.0 2000.0 1500.0 1000.0 500.0 0.00-500.0-1000.0-1500.0 Design file: MSFT DIFF CLOCK WITH TERMINATORREV2.FFS Designer: Microsoft HyperLynx V8.0 Comment: 650MHz at clk input, J10, fixture
Digital Integrated Circuits Lecture 19: Design for Testability
Digital Integrated Circuits Lecture 19: Design for Testability Chih-Wei Liu VLSI Signal Processing LAB National Chiao Tung University cwliu@twins.ee.nctu.edu.tw DIC-Lec19 cwliu@twins.ee.nctu.edu.tw 1 Outline
nmos transistor Basics of VLSI Design and Test Solution: CMOS pmos transistor CMOS Inverter First-Order DC Analysis CMOS Inverter: Transient Response
nmos transistor asics of VLSI Design and Test If the gate is high, the switch is on If the gate is low, the switch is off Mohammad Tehranipoor Drain ECE495/695: Introduction to Hardware Security & Trust
for Digital IC's Design-for-Test and Embedded Core Systems Alfred L. Crouch Prentice Hall PTR Upper Saddle River, NJ
Design-for-Test for Digital IC's and Embedded Core Systems Alfred L. Crouch Prentice Hall PTR Upper Saddle River, NJ 07458 www.phptr.com ISBN D-13-DflMfla7-l : Ml H Contents Preface Acknowledgments Introduction
Tools to Debug Dead Boards
Tools to Debug Dead Boards Hardware Prototype Bring-up Ryan Jones Senior Application Engineer Corelis 1 Boundary-Scan Without Boundaries click to start the show Webinar Outline What is a Dead Board? Prototype
Slide Set 14. Design for Testability
Slide Set 14 Design for Testability Steve Wilton Dept. of ECE University of British Columbia stevew@ece.ubc.ca Slide Set 14, Page 1 Overview Wolf 4.8, 5.6, 5.7, 8.7 Up to this point in the class, we have
Based on slides/material by. Topic Testing. Logic Verification. Testing
Based on slides/material by Topic 4 K. Masselos http://cas.ee.ic.ac.uk/~kostas J. Rabaey http://bwrc.eecs.berkeley.edu/classes/icbook/instructors.html igital Integrated Circuits: A esign Perspective, Prentice
Solutions to Embedded System Design Challenges Part II
Solutions to Embedded System Design Challenges Part II Time-Saving Tips to Improve Productivity In Embedded System Design, Validation and Debug Hi, my name is Mike Juliana. Welcome to today s elearning.
At-speed Testing of SOC ICs
At-speed Testing of SOC ICs Vlado Vorisek, Thomas Koch, Hermann Fischer Multimedia Design Center, Semiconductor Products Sector Motorola Munich, Germany Abstract This paper discusses the aspects and associated
TKK S ASIC-PIIRIEN SUUNNITTELU
Design TKK S-88.134 ASIC-PIIRIEN SUUNNITTELU Design Flow 3.2.2005 RTL Design 10.2.2005 Implementation 7.4.2005 Contents 1. Terminology 2. RTL to Parts flow 3. Logic synthesis 4. Static Timing Analysis
Based on slides/material by. Topic 14. Testing. Testing. Logic Verification. Recommended Reading:
Based on slides/material by Topic 4 Testing Peter Y. K. Cheung Department of Electrical & Electronic Engineering Imperial College London!! K. Masselos http://cas.ee.ic.ac.uk/~kostas!! J. Rabaey http://bwrc.eecs.berkeley.edu/classes/icbook/instructors.html
3D IC Test through Power Line Methodology. Alberto Pagani
3D IC Test through Power Line Methodology Alberto Pagani Outline 2 Power Line Communication (PLC) approach 2D Test architecture through PLC Advantages Methodology Feasibility Study Rx test chip for digital
A Briefing on IEEE Standard Test Access Port And Boundary-Scan Architecture ( AKA JTAG )
A Briefing on IEEE 1149.1 1990 Standard Test Access Port And Boundary-Scan Architecture ( AKA JTAG ) Summary With the advent of large Ball Grid Array (BGA) and fine pitch SMD semiconductor devices the
Lecture 23 Design for Testability (DFT): Full-Scan
Lecture 23 Design for Testability (DFT): Full-Scan (Lecture 19alt in the Alternative Sequence) Definition Ad-hoc methods Scan design Design rules Scan register Scan flip-flops Scan test sequences Overheads
A 400MHz Direct Digital Synthesizer with the AD9912
A MHz Direct Digital Synthesizer with the AD991 Daniel Da Costa danieljdacosta@gmail.com Brendan Mulholland firemulholland@gmail.com Project Sponser: Dr. Kirk W. Madison Project 11 Engineering Physics
SignalTap Plus System Analyzer
SignalTap Plus System Analyzer June 2000, ver. 1 Data Sheet Features Simultaneous internal programmable logic device (PLD) and external (board-level) logic analysis 32-channel external logic analyzer 166
Logic Analysis Basics
Logic Analysis Basics September 27, 2006 presented by: Alex Dickson Copyright 2003 Agilent Technologies, Inc. Introduction If you have ever asked yourself these questions: What is a logic analyzer? What
EEC 116 Fall 2011 Lab #5: Pipelined 32b Adder
EEC 116 Fall 2011 Lab #5: Pipelined 32b Adder Dept. of Electrical and Computer Engineering University of California, Davis Issued: November 2, 2011 Due: November 16, 2011, 4PM Reading: Rabaey Sections
Logic Analysis Basics
Logic Analysis Basics September 27, 2006 presented by: Alex Dickson Copyright 2003 Agilent Technologies, Inc. Introduction If you have ever asked yourself these questions: What is a logic analyzer? What
Boosting Performance Oscilloscope Versatility, Scalability
Boosting Performance Oscilloscope Versatility, Scalability Rising data communication rates are driving the need for very high-bandwidth real-time oscilloscopes in the range of 60-70 GHz. These instruments
Timing Error Detection: An Adaptive Scheme To Combat Variability EE241 Final Report Nathan Narevsky and Richard Ott {nnarevsky,
Timing Error Detection: An Adaptive Scheme To Combat Variability EE241 Final Report Nathan Narevsky and Richard Ott {nnarevsky, tomott}@berkeley.edu Abstract With the reduction of feature sizes, more sources
Laboratory 1 - Introduction to Digital Electronics and Lab Equipment (Logic Analyzers, Digital Oscilloscope, and FPGA-based Labkit)
Massachusetts Institute of Technology Department of Electrical Engineering and Computer Science 6. - Introductory Digital Systems Laboratory (Spring 006) Laboratory - Introduction to Digital Electronics
Spatial Light Modulators XY Series
Spatial Light Modulators XY Series Phase and Amplitude 512x512 and 256x256 A spatial light modulator (SLM) is an electrically programmable device that modulates light according to a fixed spatial (pixel)
Experiment # 4 Counters and Logic Analyzer
EE20L - Introduction to Digital Circuits Experiment # 4. Synopsis: Experiment # 4 Counters and Logic Analyzer In this lab we will build an up-counter and a down-counter using 74LS76A - Flip Flops. The
Jin-Fu Li Advanced Reliable Systems (ARES) Laboratory. National Central University
Chapter 3 Basics of VLSI Testing (2) Jin-Fu Li Advanced Reliable Systems (ARES) Laboratory Department of Electrical Engineering National Central University Jhongli, Taiwan Outline Testing Process Fault
EECS150 - Digital Design Lecture 2 - CMOS
EECS150 - Digital Design Lecture 2 - CMOS January 23, 2003 John Wawrzynek Spring 2003 EECS150 - Lec02-CMOS Page 1 Outline Overview of Physical Implementations CMOS devices Announcements/Break CMOS transistor
Future of Analog Design and Upcoming Challenges in Nanometer CMOS
Future of Analog Design and Upcoming Challenges in Nanometer CMOS Greg Taylor VLSI Design 2010 Outline Introduction Logic processing trends Analog design trends Analog design challenge Approaches Conclusion
Design of Fault Coverage Test Pattern Generator Using LFSR
Design of Fault Coverage Test Pattern Generator Using LFSR B.Saritha M.Tech Student, Department of ECE, Dhruva Institue of Engineering & Technology. Abstract: A new fault coverage test pattern generator
12-bit Wallace Tree Multiplier CMPEN 411 Final Report Matthew Poremba 5/1/2009
12-bit Wallace Tree Multiplier CMPEN 411 Final Report Matthew Poremba 5/1/2009 Project Overview This project was originally titled Fast Fourier Transform Unit, but due to space and time constraints, the
SPATIAL LIGHT MODULATORS
SPATIAL LIGHT MODULATORS Reflective XY Series Phase and Amplitude 512x512 A spatial light modulator (SLM) is an electrically programmable device that modulates light according to a fixed spatial (pixel)
EE241 - Spring 2001 Advanced Digital Integrated Circuits. References
EE241 - Spring 2001 Advanced Digital Integrated Circuits Lecture 28 References Rabaey, Digital Integrated Circuits and EE241 (1998) notes Chapter 25, ing of High-Performance Processors by D.K. Bhavsar
Design for Testability
TDTS 01 Lecture 9 Design for Testability Zebo Peng Embedded Systems Laboratory IDA, Linköping University Lecture 9 The test problems Fault modeling Design for testability techniques Zebo Peng, IDA, LiTH
Lecture 23 Design for Testability (DFT): Full-Scan (chapter14)
Lecture 23 Design for Testability (DFT): Full-Scan (chapter14) Definition Ad-hoc methods Scan design Design rules Scan register Scan flip-flops Scan test sequences Overheads Scan design system Summary
EXPERIMENT #6 DIGITAL BASICS
EXPERIMENT #6 DIGITL SICS Digital electronics is based on the binary number system. Instead of having signals which can vary continuously as in analog circuits, digital signals are characterized by only
Lecture 1: Introduction to Digital Logic Design. CK Cheng CSE Dept. UC San Diego
Lecture 1: Introduction to Digital Logic Design CK Cheng CSE Dept. UC San Diego 1 Outlines Administration Motivation Scope 2 Administration Web site: http://www.cse.ucsd.edu/classes/fa12/cse140-a/ WebCT:
Project 6: Latches and flip-flops
Project 6: Latches and flip-flops Yuan Ze University epartment of Computer Engineering and Science Copyright by Rung-Bin Lin, 1999 All rights reserved ate out: 06/5/2003 ate due: 06/25/2003 Purpose: This
Synthesized Clock Generator
Synthesized Clock Generator CG635 DC to 2.05 GHz low-jitter clock generator Clocks from DC to 2.05 GHz Random jitter
Clock Generation and Distribution for High-Performance Processors
Clock Generation and Distribution for High-Performance Processors Stefan Rusu Senior Principal Engineer Enterprise Microprocessor Division Intel Corporation stefan.rusu@intel.com Outline Clock Distribution
Name: Date: Suggested Reading Chapter 7, Digital Systems, Principals and Applications; Tocci
Richland College Engineering Technology Rev. 0 B. Donham Rev. 1 (7/2003) J. Horne Rev. 2 (1/2008) J. Bradbury Digital Fundamentals CETT 1425 Lab 7 Asynchronous Ripple Counters Name: Date: Objectives: To
Flip-Flops A) Synchronization: Clocks and Latches B) Two Stage Latch C) Memory Requires Feedback D) Simple Flip-Flop Gate
Lecture 19: November 5, 2001 Midterm in Class Wed. Nov 7 th Covers Material 6 th -10 th week including W#10 Closed Book, Closed Notes, Bring Calculator, Paper Provided Last Name A-K 2040 Valley LSB; Last
Analog Performance-based Self-Test Approaches for Mixed-Signal Circuits
Analog Performance-based Self-Test Approaches for Mixed-Signal Circuits Tutorial, September 1, 2015 Byoungho Kim, Ph.D. Division of Electrical Engineering Hanyang University Outline State of the Art for
Sharif University of Technology. SoC: Introduction
SoC Design Lecture 1: Introduction Shaahin Hessabi Department of Computer Engineering System-on-Chip System: a set of related parts that act as a whole to achieve a given goal. A system is a set of interacting
Reading an Image using CMOS Linear Image Sensor. S.R.Shinthu 1, P.Maheswari 2, C.S.Manikandababu 3. 1 Introduction. A.
International Journal of Inventions in Computer Science and Engineering, Volume 2 Issue 4 April 2015 Reading an Image using CMOS Linear Image Sensor S.R.Shinthu 1, P.Maheswari 2, C.S.Manikandababu 3 1,2
Failure Analysis Technology for Advanced Devices
ISHIYAMA Toshio, WADA Shinichi, KUZUMI Hajime, IDE Takashi Abstract The sophistication of functions, miniaturization and reduced weight of household appliances and various devices have been accelerating
40-Gb/s Limiting Amplifier Model 1424
USER S GUIDE 40-Gb/s Limiting Amplifier Model 1424 2584 Junction Ave. San Jose, CA 95134-1902 USA phone: (408) 919-1500 e-mail: contact@newfocus.com www.newfocus.com Warranty New Focus, Inc. guarantees
DT3162. Ideal Applications Machine Vision Medical Imaging/Diagnostics Scientific Imaging
Compatible Windows Software GLOBAL LAB Image/2 DT Vision Foundry DT3162 Variable-Scan Monochrome Frame Grabber for the PCI Bus Key Features High-speed acquisition up to 40 MHz pixel acquire rate allows
The XYZs of Logic Analyzers
L o g i c A n a l y z e r s ii The XYZs of Logic Analyzers Contents Introduction 1 Where It All Began 1 The Digital Oscilloscope 1 The Logic Analyzer 3 Logic Analyzer Architecture and Operation 5 Probe
Outline. EECS150 - Digital Design Lecture 27 - Asynchronous Sequential Circuits. Cross-coupled NOR gates. Asynchronous State Transition Diagram
EECS150 - Digital Design Lecture 27 - Asynchronous Sequential Circuits Nov 26, 2002 John Wawrzynek Outline SR Latches and other storage elements Synchronizers Figures from Digital Design, John F. Wakerly
How to overcome/avoid High Frequency Effects on Debug Interfaces Trace Port Design Guidelines
How to overcome/avoid High Frequency Effects on Debug Interfaces Trace Port Design Guidelines An On-Chip Debugger/Analyzer (OCD) like isystem s ic5000 (Figure 1) acts as a link to the target hardware by
CREATE. CONTROL. CONNECT.
CREATE. CONTROL. CONNECT. CREATE. CONTROL. CONNECT. DYVI offers unprecedented creativity, simple and secure operations along with technical reliability all in a costeffective, tailored and highly reliable
Logic Analyzer Triggering Techniques to Capture Elusive Problems
Logic Analyzer Triggering Techniques to Capture Elusive Problems Efficient Solutions to Elusive Problems For digital designers who need to verify and debug their product designs, logic analyzers provide
GFT Channel Digital Delay Generator
Features 20 independent delay Channels 100 ps resolution 25 ps rms jitter 10 second range Output pulse up to 6 V/50 Ω Independent trigger for every channel Fours Triggers Three are repetitive from three
VLSI Technology used in Auto-Scan Delay Testing Design For Bench Mark Circuits
VLSI Technology used in Auto-Scan Delay Testing Design For Bench Mark Circuits N.Brindha, A.Kaleel Rahuman ABSTRACT: Auto scan, a design for testability (DFT) technique for synchronous sequential circuits.
High Performance Microprocessor Design and Automation: Overview, Challenges and Opportunities IBM Corporation
High Performance Microprocessor Design and Automation: Overview, Challenges and Opportunities Introduction About Myself What to expect out of this lecture Understand the current trend in the IC Design
Testability: Lecture 23 Design for Testability (DFT) Slide 1 of 43
Testability: Lecture 23 Design for Testability (DFT) Shaahin hi Hessabi Department of Computer Engineering Sharif University of Technology Adapted, with modifications, from lecture notes prepared p by
Digital Delay / Pulse Generator DG535 Digital delay and pulse generator (4-channel)
Digital Delay / Pulse Generator Digital delay and pulse generator (4-channel) Digital Delay/Pulse Generator Four independent delay channels Two fully defined pulse channels 5 ps delay resolution 50 ps
Exercise 2: D-Type Flip-Flop
Flip-Flops Digital Logic Fundamentals Exercise 2: D-Type Flip-Flop EXERCISE OBJECTIVE When you have completed this exercise, you will be able to determine the characteristics of a D-type results with an
PicoScope 6407 Digitizer
YE AR PicoScope 6407 Digitizer HIGH PERFORMANCE USB DIGITIZER Programmable and Powerful 1 GHz bandwidth 1 GS buffer size 5 GS/s real-time sampling Advanced digital triggers Built-in function generator
Design and Implementation of Timer, GPIO, and 7-segment Peripherals
Design and Implementation of Timer, GPIO, and 7-segment Peripherals 1 Module Overview Learn about timers, GPIO and 7-segment display; Design and implement an AHB timer, a GPIO peripheral, and a 7-segment
4-BIT PARALLEL-TO-SERIAL CONVERTER
4-BIT PARALLEL-TO-SERIAL CONVERTER FEATURES DESCRIPTION On-chip clock 4 and 8 Extended 00E VEE range of 4.2V to 5.5V.6Gb/s typical data rate capability Differential clock and serial inputs VBB output for
University of Victoria. Department of Electrical and Computer Engineering. CENG 290 Digital Design I Lab Manual
University of Victoria Department of Electrical and Computer Engineering CENG 290 Digital Design I Lab Manual INDEX Introduction to the labs Lab1: Digital Instrumentation Lab2: Basic Digital Components
RX40_V1_0 Measurement Report F.Faccio
RX40_V1_0 Measurement Report F.Faccio This document follows the previous report An 80Mbit/s Optical Receiver for the CMS digital optical link, dating back to January 2000 and concerning the first prototype
A FOUR GAIN READOUT INTEGRATED CIRCUIT : FRIC 96_1
A FOUR GAIN READOUT INTEGRATED CIRCUIT : FRIC 96_1 J. M. Bussat 1, G. Bohner 1, O. Rossetto 2, D. Dzahini 2, J. Lecoq 1, J. Pouxe 2, J. Colas 1, (1) L. A. P. P. Annecy-le-vieux, France (2) I. S. N. Grenoble,
Timing EECS141 EE141. EE141-Fall 2011 Digital Integrated Circuits. Pipelining. Administrative Stuff. Last Lecture. Latch-Based Clocking.
EE141-Fall 2011 Digital Integrated Circuits Lecture 2 Clock, I/O Timing 1 4 Administrative Stuff Pipelining Project Phase 4 due on Monday, Nov. 21, 10am Homework 9 Due Thursday, December 1 Visit to Intel
FDTD_SPICE Analysis of EMI and SSO of LSI ICs Using a Full Chip Macro Model
FDTD_SPICE Analysis of EMI and SSO of LSI ICs Using a Full Chip Macro Model Norio Matsui Applied Simulation Technology 2025 Gateway Place #318 San Jose, CA USA 95110 matsui@apsimtech.com Neven Orhanovic
Features of the 745T-20C: Applications of the 745T-20C: Model 745T-20C 20 Channel Digital Delay Generator
20 Channel Digital Delay Generator Features of the 745T-20C: 20 Independent delay channels - 100 ps resolution - 25 ps rms jitter - 10 second range Output pulse up to 6 V/50 Ω Independent trigger for every
Integrated Circuit Design ELCT 701 (Winter 2017) Lecture 1: Introduction
1 Integrated Circuit Design ELCT 701 (Winter 2017) Lecture 1: Introduction Assistant Professor Office: C3.315 E-mail: eman.azab@guc.edu.eg 2 Course Overview Lecturer Teaching Assistant Course Team E-mail:
CHEETAH-X Compact Picosecond Laser. Customized systems with SESAM technology*
CHEETAH-X Compact Picosecond Laser Customized systems with SESAM technology* www.lumentum.com Data Sheet The CHEETAH-X high-average power, passively mode-locked, diode-pumped, solid-state laser system
ECE 555 DESIGN PROJECT Introduction and Phase 1
March 15, 1998 ECE 555 DESIGN PROJECT Introduction and Phase 1 Charles R. Kime Dept. of Electrical and Computer Engineering University of Wisconsin Madison Phase I Due Wednesday, March 24; One Week Grace
Digital Circuits I and II Nov. 17, 1999
Physics 623 Digital Circuits I and II Nov. 17, 1999 Digital Circuits I 1 Purpose To introduce the basic principles of digital circuitry. To understand the small signal response of various gates and circuits
Conceps and trends for Front-end chips in Astroparticle physics
Conceps and trends for Front-end chips in Astroparticle physics Eric Delagnes Fabrice Feinstein CEA/DAPNIA Saclay LPTA/IN2P3 Montpellier General interest performances Fast pulses : bandwidth > ~ 300 MHz
Using the XC9500/XL/XV JTAG Boundary Scan Interface
Application Note: XC95/XL/XV Family XAPP69 (v3.) December, 22 R Using the XC95/XL/XV JTAG Boundary Scan Interface Summary This application note explains the XC95 /XL/XV Boundary Scan interface and demonstrates
Lecture 18 Design For Test (DFT)
Lecture 18 Design For Test (DFT) Xuan Silvia Zhang Washington University in St. Louis http://classes.engineering.wustl.edu/ese461/ ASIC Test Two Stages Wafer test, one die at a time, using probe card production
Saving time & money with JTAG
Saving time & money with JTAG AltiumLive 2017: ANNUAL PCB DESIGN SUMMIT Simon Payne CEO, XJTAG Ltd. Saving time and money with JTAG JTAG / IEEE 1149.X Take-away points Get JTAG right from the start Use
PicoScope 6407 Digitizer
YE AR HIGH PERFORMANCE USB DIGITIZER Programmable and Powerful 1 GHz bandwidth 1 GS buffer size 5 GS/s real-time sampling Advanced digital triggers Built-in function generator USB-connected Signals Analysis
Quad ADC EV10AQ190A Synchronization of Multiple ADCs
Synchronization of Multiple ADCs Application Note Applies to EV10AQ190A 1. Introduction This application note provides some recommendations for the correct synchronization of multiple EV10AQ190A Quad 10-bit
Trigger synchronization and phase coherent in high speed multi-channels data acquisition system
White Paper Trigger synchronization and phase coherent in high speed multi-channels data acquisition system Synopsis Trigger synchronization and phase coherent acquisition over multiple Data Acquisition
1. Publishable summary
1. Publishable summary 1.1. Project objectives. The target of the project is to develop a highly reliable high brightness conformable low cost scalable display for demanding applications such as their
Product Level MTBF Calculation
2014 Fifth International Conference on Intelligent Systems, Modelling and Simulation Product Level MTBF Calculation Ang Boon Chong easic Corp bang@easic.com Abstract Synchronizers are used in sampling
Asynchronous IC Interconnect Network Design and Implementation Using a Standard ASIC Flow
Asynchronous IC Interconnect Network Design and Implementation Using a Standard ASIC Flow Bradley R. Quinton*, Mark R. Greenstreet, Steven J.E. Wilton*, *Dept. of Electrical and Computer Engineering, Dept.
Digilent Nexys-3 Cellular RAM Controller Reference Design Overview
Digilent Nexys-3 Cellular RAM Controller Reference Design Overview General Overview This document describes a reference design of the Cellular RAM (or PSRAM Pseudo Static RAM) controller for the Digilent
VLSI Test Technology and Reliability (ET4076)
VLSI Test Technology and Reliability (ET476) Lecture 9 (2) Built-In-Self Test (Chapter 5) Said Hamdioui Computer Engineering Lab Delft University of Technology 29-2 Learning aims Describe the concept and
Overcoming challenges of high multi-site, high multi-port RF wafer sort testing
June 7-10, 2009 San Diego, CA Overcoming challenges of high multi-site, high multi-port RF wafer sort testing Daniel Watson Mechanical Engineer Teradyne, nc. Worldwide RF Semiconductor Market Trends: Strong
MTL Software. Overview
MTL Software Overview MTL Windows Control software requires a 2350 controller and together - offer a highly integrated solution to the needs of mechanical tensile, compression and fatigue testing. MTL
Multi-Media Card (MMC) DLL Tuning
Application Report Multi-Media Card (MMC) DLL Tuning Shiou Mei Huang ABSTRACT This application report describes how to perform DLL tuning with Multi-Media Cards (MMCs) at 192 MHz (SDR14, HS2) on the OMAP5,
Product Update. JTAG Issues and the Use of RT54SX Devices
Product Update Revision Date: September 2, 999 JTAG Issues and the Use of RT54SX Devices BACKGROUND The attached paper authored by Richard B. Katz of NASA GSFC and J. J. Wang of Actel describes anomalies
Testing Results for a Video Poker System on a Chip
Testing Results for a Video Poker System on a Chip Preston Thomson and Travis Johnson Introduction- This report examines the results of a system on a chip SoC video poker system. The report will begin
Transforming Electronic Interconnect Breaking through historical boundaries Tim Olson Founder & CTO
Transforming Electronic Interconnect Breaking through historical boundaries Tim Olson Founder & CTO Remember when? There were three distinct industries Wafer Foundries SATS EMS Semiconductor Devices Nanometers
Lab #10: Building Output Ports with the 6811
1 Tiffany Q. Liu April 11, 2011 CSC 270 Lab #10 Lab #10: Building Output Ports with the 6811 Introduction The purpose of this lab was to build a 1-bit as well as a 2-bit output port with the 6811 training
VirtualScan TM An Application Story
Test Data Compaction Tool from SynTest TM VirtualScan TM An Application Story January 29, 2004 Hiroshi Furukawa SoC No. 3 Group, SoC Development Division 1 Agenda Current Problems What is VirtualScan?
Page 1 of 6 Follow these guidelines to design testable ASICs, boards, and systems. (includes related article on automatic testpattern generation basics) (Tutorial) From: EDN Date: August 19, 1993 Author:
DT3130 Series for Machine Vision
Compatible Windows Software DT Vision Foundry GLOBAL LAB /2 DT3130 Series for Machine Vision Simultaneous Frame Grabber Boards for the Key Features Contains the functionality of up to three frame grabbers
ChromaFlex. ChromaFlex CF-QRRX Quad Analog Return Path Receiver Modules HARDWARE INTERFACE MANUAL.
ChromaFlex ChromaFlex CF-QRRX Quad Analog Return Path Receiver Modules HARDWARE INTERFACE MANUAL www.atxnetworks.com www.atxnetworks.com Although every effort has been taken to ensure the accuracy of this