Track Sorter Slave reference manual

Transcription

1 Available on CMS information server CMS IN 2002/011 March 12, 2002 Track Sorter Slave reference manual A. Montanari, F. Odorici Istituto Nazionale di Fisica Nucleare, Sezione di Bologna, Italy Abstract The Track Sorter Slave (TSS) is one of the basic units that form the Trigger Server (TS) system of Drift Tube Chambers in Muon Barrel detector. This part of the local trigger is mounted directly on the chambers and its task is the selection of the two best muon segments found in smaller sections of a Muon Station, together with the rejection of fakes and duplicate tracks. The TSS functionalities are implemented in a CMOS 0.5 µm ASIC (from Alcatel). Since the devices will not be accessible during data taking, important issues in the design are the remote programmability, the system monitoring and self-test capability. In total about 1100 TSS units will equip the full CMS detector. The paper describes the TSS functionalities and the features of its hardware implementation.

2 1 Introduction The CMS Muon Barrel is formed by 250 stations of drift chambers. Each station is composed by 12 planes of drift tubes divided in 3 groups of 4 planes each, called SuperLayers (SL). Two SLs measure the coordinate in the bending plane (rφ), one SL along the beam direction (z). The four layers in a SL are staggered by half-cell: correlation of drift times can be used to compute coordinate and angle of crossing tracks. The trigger front-end device is called Bunch and Track Identifier (BTI) [1]: it finds track segments and correlates them to the corresponding bunch crossings (BX). In the rφ view the track segments found by the BTIs of the two SLs are eventually correlated by the Track Correlator (TRACO)[1]. Each TRACO selects up to two trigger candidates, looking for the segments with higher quality and smaller bending angle (corresponding to higher transverse momentum). In the longitudinal view (only one SL) the BTIs select only tracks pointing to the interaction region. The Trigger Server (TS) system is the final stage of the trigger electronics of one muon station (see Figure 1): there are in total 250 TS systems, one for each muon station. It has to select the two best segments of the station and forward them to the following system in the trigger chain: the Muon Regional Trigger. The Muon Regional Trigger will match the segments found in the different stations and assign the transverse momentum of each reconstructed track. Figure 1: architecture of DT local trigger system. 2 The Trigger Server system The TS has to select the two best trigger candidates among the track segments selected by all TRACOs in a muon station and sends them to the Sector Collector [1], where they will be forwarded to the Muon Regional Trigger. The TS has to fulfill the following requirements: since a lot of interesting physics has two close muons that can hit the same muon station, much emphasis should be put on the efficiency and purity of both selected segments. The selection should be based on both the bending angle and the quality of the track segments and selection priorities should be configurable; 2

3 it has to reject fakes generated by TRACOs using a configurable fake rejection algorithm; the processing time must be independent on the number of TRACOs in the station; the TS should be able to treat pile-up events; since only one TS is mounted on each station, it represents the bottleneck of the on-chamber trigger devices and therefore it should have built-in redundancy. The TS is composed by two subsystems: one for the transverse view (TSf ) and the other for the longitudinal view (TS?). The TS? has to detect triggers produced by the 64 BTIs that equip the SL in the? view. This information is sent to the TRACOs of the f view and can be used there as a validation of a trigger in order to reduce background. Besides, a pattern of the track segments found in the longitudinal view has to be sent to the Regional Muon Trigger. The TS? consists of groups of OR of BTI hits. Figure 2: timing diagram of Trigger Server system. The number of TRACOs in a station can be quite large: as much as 24, for the largest station. Each TRACO transmits to the TSf its two best tracks serially in two consecutive BXs, ordered in quality. In order to minimize the latency of TRACO-TS system, the TRACOs send Previews of track segments. While the TSf makes its selection (in pipeline), the TRACOs compute the full track parameters (absolute coordinates with higher 3

4 precision). The TSf then serially reads the full track parameters of the two best tracks from the corresponding TRACOs, and sends them to the Sector Collector [1]. With this mechanism 2 BXs are gained and the total latency of the TRACO-TS system is limited to 6 BXs. We define bunch1 and bunch2 respectively the first and the second bunch of tracks arriving from the TRACOs connected to the TSf. The sorting algorithm could be simple if it was just selecting independently the best track of bunch1 and the best one of bunch2. However, it is not assured that the best track of bunch2 represents the second-best track among all bunch1 and bunch2 tracks. The TSf must sort the truly second-best track among all bunch1 and bunch2 tracks. In order to achieve it, the TSf selects, among the tracks of bunch1, the first-besttrack (FBT) and the second-best-track (SBT). On the following BX, the search for the best is done among bunch2 tracks and the SBT of previous BX (carry). Therefore the sorting algorithm is applied in pipeline at each bunch. In this way the truly two best tracks among all the possible tracks are found. For normal triggers, the TSf is able to sort the two best tracks within two BXs. In case of pile-up triggers, the TS is able to provide to the Sector Collector at least the FBT data resulting from the sorting of bunch1. In case of two close muons, they likely produce two track segments in bunch1 from different TRACOs in the same stations, which are correctly picked up by the TSf algorithm through the carry. The TSf logic diagram is shown in Figure 1. The selection algorithm uses a two-layer cascade of processing units. This architecture was chosen in order to minimize the number of logic cells within a unit and the amount of I/O between blocks [2]. In each unit, a parallel minimum and next-to-minimum search is performed over a small group of input words, using 2 by 2 fast 9-bits comparators. The fully parallel approach guarantees a fixed time response, independent of the number of TRACOs in a station. Each unit of the first layer (TSS: Track Sorter Slave) processes up to four data words, while the second layer unit (TSM: Track Sorter Master) processes up to six data words. The TS? is formed by two identical units (TST), which form the OR of groups of BTIs: the information about the presence of a trigger in the? view is sent to the TRACOs via the TSSs and can be used as trigger validation in the f view. Besides a pattern of trigger hits is sent to the TSM and forwarded to the Sector Collector. As shown in Figure 1, the hardware partitioning of the system matches with the logical blocks. Each TSS device is mounted on a board (PHITRB128) that contains 4 TRACOs and 32 BTIs [1]. The TSM system is composed of three devices mounted on a separate board (Server Board) that receives the output of at most 6 TSSs (for the largest chamber). The two TST devices are mounted on two separate boards (THETATRB). The control and monitoring of the system is possible through a JTAG serial line that links the TSM, the TSSs, the TRACOs and BTIs. In case of failure of this link a backup solution is provided: a Parallel Interface that uses the lines normally dedicated to data transmission. The timing of information exchange between the various devices is shown in Figure Track Sorter Slave (TSS) The main tasks performed by the TSS are the sorting of Preview data coming from the four TRACO placed on the same board and the suppression of noise generated by them. The Preview consists of a 10-bits word (see Table 1): 4 bits are reserved for the quality of the track (First/Second Track choice, H/L trigger, Correlation, Inner/Outer SL), 5 bits are used for the bending angle and one extra bit (angle sign) is not used in the sorting but is reserved for offline monitoring (see 4.2). The best track is the one with best quality and smallest angle (which means higher transverse momentum). If the quality bits are correctly coded, the search for the best track is a search for the minimum. In one BX the TSS is able to activate a select line addressing the TRACO that sent the best Preview: the TRACO will send the corresponding full track parameters to the TSM for further processing. At the same time the best Preview is also sent to the TSM for the second stage processing. Bit First (0) / Second (1) Corr (0)/ NotCor (1) High (0) / Low (1) Inner (0) / Outer (1) Angle sign (not used) 4 Angle_4 Angle_3 Angle_2 Angle_1 Angle_0 Table 1: content of the 10-bit preview word from TRACO (the codes for quality bits are in quotes); the bit reserved for the sign of the angle is received from TRACO, but is not used in the sorting. There are two kinds of ghost segments that the TSS is able to recognize: Ghost type 1: due to the geometry of TRACO acceptance, a TRACO nearby to the one that sends the best segments, can send a copy of the same track, which has to be an Outer segment. This kind of ghost can be cancelled removing carry tracks of type Outer and Not Correlated in the TRACO nearby the one that sent the

5 best track. The final suppression of ghosts of the first type, which involves nearby TRACOs belonging to different boards, can only be done by the TSM. Ghost type 2: if a TRACO cannot correlate the two track segments in the Inner and Outer SLs belonging to the same track, it can send the Inner segment as a First Track and the Outer one as a Second Track. This case generates a ghost that can be removed by requiring that the Outer Second Track, sent by the same TRACO that gave the First best track Not Correlated in the previous BX, is not valid. From the point of view of controls and monitoring, the TSS contains the JTAG controller that can be addressed by the Controller from the Control Board: all TRACOs and BTIs on the corresponding board are serially linked to the TSS. The design of the device was done using the VHDL language, which guaranteed an easy portability on different hardware technologies. 2.2 Track Sorter Master (TSM) The TSM unit in the second layer analyses up to six Preview words from the TSSs. There is one TSM per muon station. It behaves similarly to a TSS unit of the first processing layer, but its processing begins two BXs later. The information handshake between the TS system and the TRACO devices allows data from up to twelve tracks to be stored in the TSM unit. The selected output signal from the TSM, corresponding to the FBT in the first processing cycle and to the SBT in the second cycle, are used to enable the transmission of full track data to the Sector Collector for two out of the twelve possible candidates stored in the TSM unit. The TSM system has two different logic components (Figure 1): a sorter block (TSMS) which performs the sorting on the Previews from the TSSs and a data multiplexing block (TSMD) which outputs the full data from TRACOs, corresponding to the selection done in the TSMS. System robustness considerations suggest splitting TSMD into two hardware blocks, each one looking after half DTBX chamber and with the same functionalities and internal architectures. The TSMS, TSMD0 and TSMD1 are all placed on the Server Board [1]. The TSM also receives information from the? view. The hit pattern received from the TS? is synchronized with f view track data and forwarded to the Sector Collector. 3 TSS functionalities The main functional blocks inside the TSS chip are shown in Figure 3. The online processing logic is the Sorting core: it is the part between the registers shown in the figure. The Configuration registers block contains parameters that allow configuring the working mode of the chip. Figure 3: main blocks of TSS chip. 5

6 The two blocks named Test registers and Snap registers allow the debugging and online monitor of the device. The two blocks Parallel Interface and JTAG controller allow respectively parallel and serial communication with the external world. 3.1 Sorting core The functionality of each TSS is performed in two consecutive cycles (one cycle per BX), called sort1 and sort2. The sort1 processing status is recognized when at least one TRACO gives a non-null track of bunch1 type, while the sort2 status simply corresponds to the cycle following sort1. The sort2 status can be aborted in case of pile up triggers that causes two consecutive sort1 cycles. In the sort1 cycle, each TSS unit analyses four Preview data words and transmits the minimum (FBT) to the TSM unit in the second layer, while the next-to-minimum (carry) is stored locally and carried over to the sort2 cycle. At the same time a local select is given in output to enable transmission of the full data from the selected TRACO to the TSM. In the sort2 cycle, each TSS unit analyses the four input words of bunch2 together with the carry word of the sort1 cycle. If the carry is the best trigger candidate in the sort2 cycle, a post-select line is used to inform the TRACO that it has to transmit to the TSM the track segment of the previous cycle (SBT). Using the internal configuration registers, it is possible to steer the sorting algorithm: Input mask: each of the input Previews from TRACOs can be masked in case of noisy channels; Quality filter: it is also possible to mask only the tracks with a certain quality, for example only LTRGs; Priority encoder: during normal operation the priorities used in the sorting are, in order of decreasing importance: correlation, quality of the trigger, position of the trigger (i.e. inner or outer SL), angular deviation with respect to the radial direction. It is possible to swap the priority order of the quality bits to the following ordering: High/Low, Corr/NotCorr, Inner/Outer; normally the carry track from sort1 cycle is used in sort2 cycle: it is possible to disable this mechanism. it is also possible to disable the algorithms for ghost suppression. After filtering, the four 9 bits preview words from TRACOs, together with the carry track of the previous cycle, enter a battery of ten 2-words comparators. The First Best Track (FBT) is sent to the TSM while the Second Best Track (SBT) is kept as carry. At the same time the select lines to TRACOs are activated. In case of identical previews, the selection priority, in order of decreasing importance, is the following: previews from TRACOs 3, 2, 1, 0 in sort1 (i.e. in case of null tracks TRACO 3 will be selected). In case of sort2 the carry has priority over the current previews. 3.2 Configuration registers The Configuration registers are used to program the various functionalities of the device. In total there are seven 8-bit read-write registers that can be accessed by both the JTAG and Parallel Interface (see section 4). The contents of these registers are shown in Table 2. The meaning of the various words is the following: trmskii(i) = 1 mask all second tracks in TRACO i; trmski(3) = 1 mask all tracks from TRACO i; trmski(2) = 1 mask not correlated tracks from TRACO i; trmski(1) = 1 mask Low trigger tracks from TRACO i; trmski(0) = 1 mask Outer tracks from TRACO i; ghost1 = 1 disable suppression of ghost type 1 (Carry Outer Not Correlated near First Best track); ghost2 = 1 disable suppression of ghost type 2 (Second track Outer on same TRACO that gave First Best track Not Correlated); ghost1c =1 ignore Correlation bit for ghost type 1; ghost2c =1 ignore Correlation bit for ghost type 2; 6

7 prisj(2) = 1 mask Correlation bit for all tracks in Sort j (j =1 or 2); prisj (1) = 1 mask High/Low trigger bit for all tracks in Sort j; prisj (0) = 1 mask Inner/Outer bit for all tracks in Sort j; pric(2) = 1 mask Correlation bit in Carry track; pric(1) = 1 mask High/Low trigger bit in Carry track; pric(0) = 1 mask Inner/Outer bit in Carry track; priosj = 1 order of priority bits: H/L(bit 7) C/NC(bit 6) I/O (bit 5) in Sort j (j =1 or 2); carry =1 disable Carry track (mask it); tsmff=1 no FF on output to TSM; trff =1 add one extra FF on output to TRACOs (select and post-select lines); inff = 1 remove FF on input from TRACOs; thff = 1 add FF on input from Theta board; thctrl(2,1,0) 3 bit code for Theta Filter (see 3.7); NoSqDiv = 1 no clock division for Sequencer (see 3.5); SnapTrg(1,0) 2 bit code for Snap autotrigger (see 3.3); testmode = 1 starts the Test patterns injection in Sorting core (see 3.4). Reg P.I. Add Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 $00 trmskii(3) trmskii(2) trmskii(1) trmskii(0) ghost2c ghost2 ghost1c ghost1 1 $01 trmsk1(3) trmsk1(2) trmsk1(1) trmsk1(0) trmsk0(3) trmsk0(2) trmsk0(1) trmsk0(0) 2 $02 trmsk3(3) trmsk3(2) trmsk3(1) trmsk3(0) trmsk2(3) trmsk2(2) trmsk2(1) trmsk2(0) 3 $03 not used pris2(2) pris2(1) pris2(0) not used pric(2) pric(1) pric(0) 4 $04 not used carry prios2 prios1 not used pris1(2) pris1(1) pris1(0) 5 $05 not used not used not used NoSqDiv not used thctrl(2) thctrl(1) thctrl(0) 6 $06 SnapTrg(1) SnapTrg(0) not used testmode thff tsmff trff inff Table 2: contents of seven 8-bits registers of Configuration memory; the Parallel Interface address of each register is given in the second column. 7

8 3.3 Snap registers During the normal data taking activity, the functionality of the sorting core can be spied by using Snap registers, as shown in Figure 4. These registers are organized as two blocks of FIFOs that take data respectively from the input and the output of the sorting core. Figure 4: connections of Snap and Test registers to the Sorting core. The correspondence between the input of the FIFOs and the spied lines is indicated on the left side of Figure 5. Figure 5: FIFO architecture of Snap registers. The addresses for P.I. access are also indicated. The JTAG serial link connects together all registers, from snap-in to snap-out, with a unique chain, as shown. 8

9 The clock of these FIFOs is free running and is the same 40 MHz clock used for the core. The clock is stopped only when snap-in data satisfy a triggering condition. The depth of the FIFOs is chosen in order to get a picture of the whole event (4 BXs). The default trigger condition is given by the presence of at least one High trigger quality among the four preview words. The triggering condition can be changed by writing the SnapTRG word in register 6 of Configuration memory. See Figure 5 for trigger codes. The triggering condition is evaluated after the third column of the FIFOs that monitor the inputs to the sorting core, corresponding to BX 0. Data from the previous (BX -1) and the two following (BX +1, BX+2) bunch crossings are also latched. A copy of the triggering condition which caused the stop of the FIFOs clock is kept for crosscheck in register $0D. The 8-bit registers that form the FIFOs are read-only and can be accessed by JTAG or Parallel Interface (see Figure 5 for the PI addresses of 32 registers that form the Snap FIFOs and for the topology of JTAG chain). The start of the sampling is enabled by a Snap reset signal, until a new trigger condition is found. 3.4 Test registers Test registers can be used to inject patterns into the sorting core for offline tests of the sorting circuitry at 40 MHz. When the Test Mode operation is activated (by setting the bit TESTMODE in register 6 of Configuration memory), the inputs of the sorting core are no more driven by the external pads but by a battery of 5 FIFOs (depth of four 8-bit registers): see Figure 4 and Figure 6. The response of the sorting core can be monitored by using the Snap registers. Therefore data patterns loaded into the test registers must fulfil the snap trigger condition in order that the event can be recorded. The triggering event must be loaded into the third column of FIFO, corresponding to BX 0. Figure 6: FIFO architecture of Test registers. The 8-bit registers of the FIFO can be preloaded (and eventually read) by using JTAG or Parallel Interface. Default contents at power on of Test registers are null tracks ($FF code) and also the inputs of the FIFO are set to null tracks. This means that, anyway, after 4 clocks all the registers are filled with null tracks. In order to start the injection (after entering the Test Mode) a Snap reset signal must be issued: patterns are injected at 40 MHz into the core. At the same time Snap registers are activated so that it is possible to monitor the core activity. The timing of the operations necessary to start the Test registers is shown in Figure 7. 9

10 Figure 7: timing of Test registers operations. 3.5 Sequencer In order to monitor the trigger electronics functionality during CMS data taking periods using the on-chamber Test Pulse Generator a dedicated Sequencer has been implemented. Three control lines are used to drive the Sequencer: SQTST (active High), SQRST (active Low), SQADV (active High). The Sequencer is activated when SQTST is set: the sorter is disabled by masking all TRACO preview inputs, but the input indicated by a sequence counter that ranges from 0 to 3. The sequence counter is incremented cyclically by the SQADV strobe divided by 4 (default; but it is possible to cause an increment in the counter every SQADV rising edge by setting the bit NoSqDiv in configuration register 5). In the meanwhile the TRACO can cycle on the 4 pairs of BTIs. The sequence counter can be reset to 0 when SQRST is activated. 3.6 Reset control There are four main reset signals coming from input pins: HWRST: hardware reset (active Low); SWRST: software reset (active Low); SNRST: snap registers reset (active Low); SQRST: sequencer reset (active Low). From the previous signals ten internal reset lines are built: RST_CORE = HWRST SWRST : reset core; RST_CONFIG = HWRST : reset configuration registers; RST_CONTROL = HWRST : reset Controller for Parallel Interface; RST_TAP = HWRST SWRST : reset JTAG TAP controller; RST_PWRTAP = HWRST : reset JTAG TAP controller; RST_SQ = HWRST SQRST : reset sequencer; RST_SNAPFF = HWRST(sync.) SWRST : reset Snap registers FFs; RST_SNAPTRG = HWRST(sync.) SWRST SNRST : reset Snap registers trigger FF; RST_TEST = HWRST : reset Test registers FFs; RST_SYNCRO = HWRST : reset (or set) input syncronization FFs; 3.7 Theta filter Two input lines come from the Theta Trigger boards: THETA: at least one trigger found in the θ view; HTHETA: at least one High trigger found in the θ view. It is possible to insert an optional FF on the input line (for time tuning purposes): the option can be switched on by setting the bit THFF in Configuration register 6. 10

11 From these signals the Theta filter builds an individual line ITHETA that as to be sent to TRACO for trigger validation, according to the setting of the 3 bits word THCTRL in Configuration register 5: ITHETA = THETA if THCTRL= 000 (default) = HTHETA if THCTRL= 001 = not (HTHETA) THETA if THCTRL= 010 = 0 if THCTRL= 011 = 1 if THCTRL= 100 =THETA 3.8 Input synchronization if THCTRL= other cases All control signals that arrive to the Trigger Board are generated by the chamber Control Board and are asynchronous. In order to synchronize and to filter these signals from noise, two types of synchronizations were foreseen, as shown in Figure 8. (a) Figure 8: (a) synchronizer for input levels; (b) synchronizer for input edges, with glitch filtering. The type (a) is used to synchronize control levels: the input must be stable for at least one clock cycle and it is delayed between one or two clock periods. The type (b) is applied to control signals that are used as external strobes: in this case the coincidence prevents external glitches (shorter than one clock period) to pass the filter and the original control signals are delayed between two and three clock periods. All the FFs of these filters are reset (or set, according to the active logic of the signal) at power on. The signals (see appendix A) SWRST, SNRST, SQRST, SQTST, NPROG and WR are filtered for levels, while TCK, SQADV and STR are filtered for glitches. 3.9 I/O pads The complete list of the I/O pads can be found in Appendix A. Four kind of pads are used: Bi-directional: CMOS/CMOS without internal pull resistors; Input (fast signals): CMOS with internal 50kΩ pull resistors; Input (control signals): TTL + Schmitt trigger with internal 50kΩ pull resistors; Output: CMOS. The clock signal is internally inverted: this is done for compatibility with TRACO that sends its previews on the falling edge of the clock distributed on the Trigger Board. (b) 4 TSS interfaces Two independent channels can access the internal registers of the TSS: JTAG, which allows online serial transmission of data using a standard protocol [6]; Parallel Interface, which uses an ad-hoc protocol for offline parallel data transmission. In case of failure of one of the two systems, the other one guarantees the accessibility of the device. 11

12 4.1 JTAG The basic architecture of the implementation of the JTAG in the TSS is shown in Figure 9. The inputs to the TAP controller are activated only when the Trigger Board that contains the TSS is addressed (JTAGA is a 4-bit code coming from Controller which must be equal to the BADD which comes from a dip switch on the board). In this case the TSS forwards the TCK and TMS signal also to all 32 BTIs and 4 TRACOs of the board. The TSS is the first device in the serial chain. The chain continues through the line ITDO to all TRACOs and BTIs and finally exits the board through the TSS again (signals ITDI-TDO). Figure 9: JTAG architecture inside TSS and topology of serial chain on the Trigger Board. The working mode depend on the instruction register code (see Table 3). The mandatory EXTEST, SAMPLE and BYPASS working modes are implemented. The SAMPLE mode allows scanning through the Boundary Scan Register, that is the cells which are placed on the I/O pins of the device; the EXTEST mode is used to inject signals on the output pads in order to test board connections; the BYPASS mode is used to skip the chains inside TSS (see Figure 9). The CONFIG, TEST and SNAP are user mode and allow the access to Configuration registers, Test registers and Snap registers. Instruction Register Name Description 0 EXTEST Boundary Scan Registers test (OUT) SAMPLE Boudary Scan Registers sampling CONFIG Configuration registers (R/W) 8 TEST Test registers access (R/W) 9 SNAP Snap registers access (R) BYPASS Chip bypass Table 3: JTAG Instruction Register codes used in TSS. 12

13 The basic cell structures for Input and Output pins and for Bi-directional pins are shown in Appendix D, as well as the basic cells for Snap and Test registers. The bit ordering for the Boundary Scan Registers chain and for the Configuration registers chain can be found in Appendix B and C, while bit ordering in the chains for Snap and Test registers can be found in Figure 5 and Figure Parallel Interface The basic principle of Parallel Interface (PI) is to use the trigger busses dedicated for preview transfer as links for parallel communication between the various devices in the trigger chain. This implies that during this type of communication the trigger system must be offline. The architecture of the links is shown in Figure 10. The bidirectional 8-bit data bus is formed by the preview words (lower 8-bits) from TRACO and the preview to TSM. The full system has a tree architecture: from the TSM it possible to access one of the TSS; from the TSS it is possible to access one of the TRACOs, and from the TRACO one of the BTIs. Figure 10: architecture of Parallel Interface busses inside TSS (in shadowed parts, list of internal signals used for synchronization and register multiplexing) In order to control the PI data transfer, 3 control lines are foreseen: NPROG: WR: STR: put the system offline and initialize PI (=1 during normal data taking); indicates if Read or Write operation (=1 for write); it is the strobe signal (positive logic). These control lines, generated by the chamber control board, are asynchronous signals. The NPROG and WR lines are filtered for levels, while STR is filtered to eliminate glitches (see section 3.8). This implies that NPROG and WR signal enter the PI controller with at most 50 ns delay, while STR with at most 75 ns delay. Besides the STR level must be stable for at least 50 ns, which implies that the clock frequency for PI cannot exceed 10 MHz. The protocol for data transfer is illustrated in Figure 11. When the system enters in PI mode (NPROG=0) the preview bus to TSM is switched in input mode and represents the data line. The data present during the first strobe signal is the address: it can be an internal or external address. In case of an external address all the subsequent data are forwarded to the devices downward in the chain. In case of internal address the following data are the data to be written in case of write operation. In case of a read operation, the content of the addressed register is put into the data bus for the length of the strobe signal at level high. The direction of the data busses is 13

14 determined by the status of PI controller, through enable lines. In case of internal operation, after the first strobe signal that set the starting address, the following address for read or writes operation is given by the auto increment of the original address. Figure 11: timing for Parallel Interface operations (internal read); note that the active clock edge is the falling one. All control lines (NPROG, WR, STR) are synchronized (s_nprog, s_wr, s_str). The address codes for external and internal operation are shown in Table 4. All the other addresses do not correspond to operations and are ineffective. Address range # registers TRACO $80 - $83 4 CONFIG $00 - $06 7 free $07 - $08 2 SNAP $09 - $28 32 TEST $29 - $3C 20 Table 4: Parallel Interface register addresses. An example of timing for read operation on TRACOs is shown in Figure 12. It should be noted that the TSS forwards all the 3 control lines (NPROG, WR, STR) to TRACOs and BTIs on the Theta Trigger Board (on the NPROG line there is an extra FF in output in order to delay by one cycle the start of PI operations in TRACO and BTIs). The data is present on the data bus to TSM only when the strobe is active: otherwise the bus is in tristate. This is true for any device driving the PI data bus. 14

15 Figure 12: timing for TRACO read operation; the table reports the response time and time constraints, mainly due to the synchronization of the control lines. Examples of read and write operations on TSS internal registers are illustrated in Figure 13 and Figure 14. Figure 13: timing for TSS read operation. 15

16 Figure 14: timing for TSS write operation. 5 Timing response The timing response of the device was simulated by using a CAD simulator. The relevant results are summarized in Figure 15. It should be noted that the active clock edge is the falling one (actually all the design was based on rising clock edge and only afterward an inverter was added at the beginning of the clock tree in order to fix the timing with TRACOs) Figure 15: timing of relevant output signals (from Synopsys post-layout simulation). Typ and Max values correspond respectively to the operating conditions: 25 o C at 3.3V and 85 o C at 3.0V. 16

17 References [1] CERN LHCC 2000/038, CMS Collaboration, The Level-1 Trigger, Technical Design Report. [2] CMS TN 1996/078, G.M.Dallavalle et al., Track Segment Sorting in the Trigger Server of a Barrel Muon Station in CMS. [3] CERN LHCC 1998/ , G.M.Dallavalle et al., Proceedings of the Fourth Workshop on Electronics for LHC experiments. [4] CERN LHCC 1998/ , G.M.Dallavalle et al., Proceedings of the Fourth Workshop on Electronics for LHC experiments. [5] CMS NOTE 2001/028, G.M.Dallavalle et al., Antifuse FPGAs for the Track-Sorter-Master of the CMS Muon Barrel Drift Tubes: Design Issues and Irradiation Test. [6] IEEE Std ,"IEEE Standard Test Access Port and Boundary -Scan Architecture". [7] Nucl. Instr. and Meth. A150 (2000) 155, M.Huhtinen and F.Faccio, Computational method to estimate Single Event Upset rates in an accelerator environment. 17

18 Appendix A: pinout CHIP package: QFP-120; pin 1 is in the upper pin on left side (top view); pin numbering is anti-clockwise. Pin # Pin name Pin Description I/O I ma PAD type Alcatel PAD Syn.FF 40 MHz VHDL Pin name 1 P0ANG0 TRACO-0 angle(0) I/O 2 C/C msr BD2CRM P10 / - PRW0(0) 2 P0ANG1 TRACO-0 angle(1) I/O 2 C/C msr BD2CRM P10 / - PRW0(1) 3 P0ANG2 TRACO-0 angle(2) I/O 2 C/C msr BD2CRM P10 / - PRW0(2) 4 P0ANG3 TRACO-0 angle(3) I/O 2 C/C msr BD2CRM P10 / - PRW0(3) 5 P0ANG4 TRACO-0 angle(4) I/O 2 C/C msr BD2CRM P10 / - PRW0(4) 6 P0ANGS TRACO-0 ang.sign I/O 2 C/C msr BD2CRM PRW0(5) 7 GNDE GND periphery XVSSE_3 8 VCCE VCC periphery XVDDE_3 9 P0IO TRACO-0 In/Outer I/O 2 C/C msr BD2CRM P10 / - PRW0(6) 10 P0HL TRACO-0 High/Low I/O 2 C/C msr BD2CRM P10 / - PRW0(7) 11 P0CR TRACO-0 Corr/NCo I C 50K up IBUFU_50K P10 PRW0i(0) 12 P0FS TRACO-0 1st/2 nd I C 50K up IBUFU_50K P10 PRW0i(1) 13 TSEL0 TRACO-0 Select O 2 C nosr B2C P12 H TSEL0 14 GNDI GND core XVSSI_1 15 VCCI VCC core XVDDI_1 16 TSEL1 TRACO-1 Select O 2 C nosr B2C P12 H TSEL1 17 P1ANG0 TRACO-1 angle(0) I/O 2 C/C msr BD2CRM P10 / - PRW1(0) 18 P1ANG1 TRACO-1 angle(1) I/O 2 C/C msr BD2CRM P10 / - PRW1(1) 19 GNDE GND periphery XVSSE_2 20 VCCE VCC periphery XVDDE_2 21 P1ANG2 TRACO-1 angle(2) I/O 2 C/C msr BD2CRM P10 / - PRW1(2) 22 P1ANG3 TRACO-1 angle(3) I/O 2 C/C msr BD2CRM P10 / - PRW1(3) 23 P1ANG4 TRACO-1 angle(4) I/O 2 C/C msr BD2CRM P10 / - PRW1(4) 24 P1ANGS TRACO-1 ang.sign I/O 2 C/C msr BD2CRM PRW1(5) 25 P1IO TRACO-1 In/Outer I/O 2 C/C msr BD2CRM P10 / - PRW1(6) 26 P1HL TRACO-1 High/Low I/O 2 C/C msr BD2CRM P10 / - PRW1(7) 27 P1CR TRACO-1 Corr/NCo I C 50K up IBUFU_50K P10 PRW1i(0) 28 P1FS TRACO-1 1 st /2 nd I C 50K up IBUFU_50K P10 PRW1i(1) 29 GNDE GND periphery XVSSE_1 30 VCCE VCC periphery XVDDE_1 31 BANG0 BestTck angle(0) I/O 8 C/C nosr BD8STC - / P10 BESTW(0) 32 BANG1 BestTck angle(1) I/O 8 C/C nosr BD8STC - / P10 BESTW(1) 33 BANG2 BestTck angle(2) I/O 8 C/C nosr BD8STC - / P10 BESTW(2) 34 VCCE VCC periphery XVDDE_4 35 GNDE GND periphery XVSSE_4 36 BANG3 BestTck angle(3) I/O 8 C/C nosr BD8STC - / P10 BESTW(3) 37 BANG4 BestTck angle(4) I/O 8 C/C nosr BD8STC - / P10 BESTW(4) 38 BIO BestTck In/Outer I/O 8 C/C nosr BD8STC - / P10 BESTW(5) 39 VCCE VCC periphery XVDDE_5 40 GNDE GND periphery XVSSE_5 18

19 41 BHL BestTck High/Low I/O 8 C/C nosr BD8STC - / P10 BESTW(6) 42 BCR BestTck Cor/NCor I/O 8 C/C nosr BD8STC - / P10 BESTW(7) 43 BFS BestTck 1 st /2 nd O 8 C/C nosr B8C P10 BESTWo(0) 44 VCCE VCC periphery XVDDE_6 45 GNDE GND periphery XVSSE_6 46 BSEL0 BestTck Sel(0) O 8 C/C nosr B8C P10 BESTWo(1) 47 BSEL1 BestTck Sel(1) O 8 C/C nosr B8C P10 BESTWo(2) 48 TDO JTAG Data Out O 8 C msr BT8CRM TDO 49 STR Par.Intrf.Strobe I Sch T 50K dw SCHMITTD_50K 3 STRTSM 50 WR P.I. Write/nRead I Sch T 50K up SCHMITTU_50K 2 WRTSM 51 THETA Theta Trigger I T 50K dw TLCHTD_50K P10 H THTRG 52 HTHETA Theta HighTrig. I T 50K dw TLCHTD_50K P10 H THHTRG 53 JADD0 JTAG Address 0 I Sch T 50K up SCHMITTU_50K JTAGA(0) 54 JADD1 JTAG Address 1 I Sch T 50K up SCHMITTU_50K JTAGA(1) 55 JADD2 JTAG Address 2 I Sch T 50K up SCHMITTU_50K JTAGA(2) 56 JADD3 JTAG Address 3 I Sch T 50K up SCHMITTU_50K JTAGA(3) 57 TDI JTAG Data In I Sch T 50K up SCHMITTU_50K TDI 58 TMS JTAG Mode Select I Sch T 50K up SCHMITTU_50K TMS 59 TCK JTAG Clock I Sch T 50K dw SCHMITTD_50K 3 R TCK 60 NPROG Program Mode I Sch T 50K up SCHMITTU_50K 2+1 L NPROG 61 VCCE VCC periphery XVDDE_7 62 GNDE GND periphery XVSSE_7 63 P2FS TRACO-2 1 st /2 nd I C 50K up IBUFU_50K P10 PRW2i(1) 64 P2CR TRACO-2 Cor/NCor I C 50K up IBUFU_50K P10 PRW2i(0) 65 P2HL TRACO-2 High/Low I/O 2 C/C msr BD2CRM P10 / - PRW2(7) 66 P2IO TRACO-2 In/Outer I/O 2 C/C msr BD2CRM P10 / - PRW2(6) 67 P2ANGS TRACO-2 ang.sign I/O 2 C/C msr BD2CRM PRW2(5) 68 P2ANG4 TRACO-2 angle(4) I/O 2 C/C msr BD2CRM P10 / - PRW2(4) 69 P2ANG3 TRACO-2 angle(3) I/O 2 C/C msr BD2CRM P10 / - PRW2(3) 70 P2ANG2 TRACO-2 angle(2) I/O 2 C/C msr BD2CRM P10 / - PRW2(2) 71 VCCE VCC periphery XVDDE_8 72 GNDE GND periphery XVSSE_8 73 P2ANG1 TRACO-2 angle(1) I/O 2 C/C msr BD2CRM P10 / - PRW2(1) 74 P2ANG0 TRACO-2 angle(0) I/O 2 C/C msr BD2CRM P10 / - PRW2(0) 75 TSEL2 TRACO-2 Select O 2 C nosr B2C P12 H TSEL2 76 VCCI VCC core XVDDI_2 77 GNDI GND core XVSSI_2 78 TSEL3 TRACO-3 Select O 2 C nosr B2C P12 H TSEL3 79 P3FS TRACO-3 1 st /2 nd I C 50K up IBUFU_50K P10 PRW3i(1) 80 P3CR TRACO-3 Cor/NCor I C 50K up IBUFU_50K P10 PRW3i(0) 81 P3HL TRACO-3 High/Low I/O 2 C/C msr BD2CRM P10 / - PRW3(7) 82 P3IO TRACO-3 In/Outer I/O 2 C/C msr BD2CRM P10 / - PRW3(6) 83 VCCE VCC periphery XVDDE_9 84 GNDE GND periphery XVSSE_9 85 P3ANGS TRACO-3 ang.sign I/O 2 C/C msr BD2CRM PRW3(5) 86 P3ANG4 TRACO-3 angle(4) I/O 2 C/C msr BD2CRM P10 / - PRW3(4) 19

20 87 P3ANG3 TRACO-3 angle(3) I/O 2 C/C msr BD2CRM P10 / - PRW3(3) 88 P3ANG2 TRACO-3 angle(2) I/O 2 C/C msr BD2CRM P10 / - PRW3(2) 89 P3ANG1 TRACO-3 angle(1) I/O 2 C/C msr BD2CRM P10 / - PRW3(1) 90 P3ANG0 TRACO-3 angle(0) I/O 2 C/C msr BD2CRM P10 / - PRW3(0) 91 GNDE GND periphery XVSSE_12 92 TPSEL BestTck PostSel O 4 C nosr B4C P10 H TPSEL 93 ISQADV SQADV to Board O 2 C msr B2CRM H ISQADV 94 SQADV Sequence Advance I Sch T 50K dw SCHMITTD_50K 2 H SQADV 95 ISQTST SQTST to Board O 2 C msr B2CRM H ISQTST 96 SQTST Sequence Test I Sch T 50K dw SCHMITTD_50K 2 H SQTST 97 GNDE GND periphery XVSSE_11 98 VCCE VCC periphery XVDDE_11 99 ISQRST SQRST to Board O 2 C msr B2CRM H ISQRESET 100 SQRST Sequence Reset I Sch T 50K dw SCHMITTD_50K 2 H SQRESET 101 INPROG NPROG to Board O 8 C msr B8CRM L INPROG 102 BADD3 Board Address 3 I T 50K up TLCHTU_50K BADD(3) 103 BADD2 Board Address 2 I T 50K up TLCHTU_50K BADD(2) 104 BADD1 Board Address 1 I T 50K up TLCHTU_50K BADD(1) 105 BADD0 Board Address 0 I T 50K up TLCHTU_50K BADD(0) 106 ITDI TDI from board I Sch T 50K up SCHMITTU_50K ITDI 107 ITDO TDO to board O 2 C msr BT2CRM ITDO 108 ITMS TMS to board O 8 C msr B8CRM ITMS 109 GNDR GND periphery XVSSR_1 110 VCCR VCC periphery XVDDR_1 111 ITCK TCK to board O 8 C msr B8CRM R ITCK 112 ITHETA THETA to TRACO O 4 C msr B4C H ITHTRG 113 GNDE GND periphery XVSSE_ VCCE VCC periphery XVDDE_ ISNRST SNRST to Board O 8 C msr B8CRM L ISNRESET 116 ISRST SRST to Board O 8 C msr B8CRM L ISRESET 117 SNRST Snap Reset I Sch T 50K up SCHMITTU_50K 2 L SNRESET 118 SRST Software Reset I Sch T 50K up SCHMITTU_50K 2 L SRESET 119 HRST Hardware Reset I T 50K up TLCHTU_50K L RESET 120 CK40 40 MHz Clock I T 50K dw TLCHTD_50K F PHI Table notes: Column 4: pin I/O direction (I Sch = Schmidt Trigger input pad); Column 6: pad type (C=CMOS, T=TTL), with Slew Rate (msr = medium SR, nosr = no SR), with (if any) pull up or pull down values; Column 8: number of FF used to synchronise (40 MHz) an I/O pin. When FF insertion is programmable, table reports Pyx, where x corresponds to the default state and y to the programming option; Column 9: logic or signal edge used for a given signal (H/L=High/Low, R/F=Rise/Fall). 20

21 Appendix B: Boundary Scan Registers chain BSR Name Description BSR Name Description BSR Name Description 123 NPROG Program Mode 81 " (out) " (out) 39 " (out) " (out) 122 SNRST Snap Reset 80 P3ANG1 TRACO-3 angle(1) 38 P0FS TRACO-1 1st/2 nd 121 SQADV Sequence Advance 79 " (out) " (out) 37 P0CR TRACO-1 Corr/NCo 120 SQRST Sequence Reset 78 P3ANG0 TRACO-3 angle(0) 36 EN_P0 Enable P0 (def=1) 119 SQTST Sequence Test 77 " (out) " (out) 35 P0HL TRACO-0 High/Low 118 SRST Software Reset 76 P2FS TRACO-2 1st/2 nd 34 " (out) " (out) 117 STR Par.Intrf.Strobe 75 P2CR TRACO-2 Corr/NCo 33 P0IO TRACO-0 In/Outer 116 THETA Theta Trigger 74 EN_P2 Enable P2 (def=1) 32 " (out) " (out) 115 HTHETA Theta HighTrig. 73 P2HL TRACO-2 High/Low 31 P0ANGS TRACO-0 ang.sign 114 WR P.I. Write/nRead 72 " (out) " (out) 30 " (out) " (out) 113 JADD3 JTAG Address 3 71 P2IO TRACO-2 In/Outer 29 P0ANG4 TRACO-0 angle(4) 112 JADD2 JTAG Address 2 70 " (out) " (out) 28 " (out) " (out) 111 JADD1 JTAG Address 1 69 P2ANG5 TRACO-2 ang.sign 27 P0ANG3 TRACO-0 angle(3) 110 JADD0 JTAG Address 0 68 " (out) " (out) 26 " (out) " (out) 109 BADD3 Board Address 3 67 P2ANG4 TRACO-2 angle(4) 25 P0ANG2 TRACO-0 angle(2) 108 BADD2 Board Address 2 66 " (out) " (out) 24 " (out) " (out) 107 BADD1 Board Address 1 65 P2ANG3 TRACO-2 angle(3) 23 P0ANG1 TRACO-0 angle(1) 106 BADD0 Board Address 0 64 " (out) " (out) 22 " (out) " (out) 105 ISNRST SNRST to Board 63 P2ANG2 TRACO-2 angle(2) 21 P0ANG0 TRACO-0 angle(0) 104 ISQADV SQADV to Board 62 " (out) " (out) 20 " (out) " (out) 103 ISQRST SQRST to Board 61 P2ANG1 TRACO-2 angle(1) 19 BSEL1 BestTck Sel(1) 102 ISQTST SQTST to Board 60 " (out) " (out) 18 BSEL0 BestTck Sel(0) 101 ISRST SRST to Board 59 P2ANG0 TRACO-2 angle(0) 17 BFS BestTck 1 st /2 nd 100 TPSEL BestTck Postsel 58 " (out) " (out) 16 EN_BW Enable BW (def=0) 99 TSEL3 TRACO-3 Select 57 P1FS TRACO-1 1st/2 nd 15 BCR BestTck Cor/NCor 98 TSEL2 TRACO-2 Select 56 P1CR TRACO-1 Corr/NCo 14 " (out) " (out) 97 TSEL1 TRACO-1 Select 55 EN_P1 Enable P1 (def=1) 13 BHL BestTck High/Low 96 TSEL0 TRACO-0 Select 54 P1HL TRACO-1 High/Low 12 " (out) " (out) 95 P3FS TRACO-3 1st/2 nd 53 " (out) " (out) 11 BIO BestTck In/Outer 94 P3CR TRACO-3 Corr/NCo 52 P1IO TRACO-1 In/Outer 10 " (out) " (out) 93 EN_P3 Enable P3 (def=1) 51 " (out) " (out) 9 BANG4 BestTck angle(4) 92 P3HL TRACO-3 High/Low 50 P1ANG5 TRACO-1 ang.sign 8 " (out) " (out) 91 " (out) " (out) 49 " (out) " (out) 7 BANG3 BestTck angle(3) 90 P3IO TRACO-3 In/Outer 48 P1ANG4 TRACO-1 angle(4) 6 " (out) " (out) 89 " (out) " (out) 47 " (out) " (out) 5 BANG2 BestTck angle(2) 88 P3ANG5 TRACO-3 ang.sign 46 P1ANG3 TRACO-1 angle(3) 4 " (out) " (out) 87 " (out) " (out) 45 " (out) " (out) 3 BANG1 BestTck angle(1) 86 P3ANG4 TRACO-3 angle(4) 44 P1ANG2 TRACO-1 angle(2) 2 " (out) " (out) 85 " (out) " (out) 43 " (out) " (out) 1 BANG0 BestTck angle(0) 84 P3ANG3 TRACO-3 angle(3) 42 P1ANG1 TRACO-1 angle(1) 0 " (out) " (out) 83 " (out) " (out) 41 " (out) " (out) 82 P3ANG2 TRACO-3 angle(2) 40 P1ANG0 TRACO-1 angle(0) Table 5: BSR chain in TSS (BSR 0 is the output; shadowed cells are critical bits: bidir. bus enable lines). 21

22 Appendix C: Configuration registers JTAG chain Bit Name Description Bit Name Description Bit Name Description 55 SnTrg(1) Snap trigger cond. 36 prios1 Priority order Sort 2 17 trmsk2(1) " 54 SnTrg(0) " 35 free - 16 trmsk2(0) " 53 free - 34 pris1(2) Disable priority Sort1 15 trmsk1(3) Mask TRACO 1 52 testmode Go in Test mode 33 pris1(1) " 14 trmsk1(2) " 51 thff Add FF on theta IN 32 pris1(0) " 13 trmsk1(1) " 50 tsmff Remove FF to TSM 31 free - 12 trmsk1(0) " 49 trff Add FF to TRACO 30 pris2(2) Disable priority Sort2 11 trmsk0(3) Mask TRACO 0 48 inff Remove FF on IN 29 pris2(1) " 10 trmsk0(2) " 47 free - 28 pris2(0) " 9 trmsk0(1) " 46 free - 27 free - 8 trmsk0(0) " 45 free - 26 pric(2) Disable priority carry 7 trmskii(3) Mask 2nd track 44 NoSqDiv Remove seq. div. 25 pric(1) " 6 trmskii(2) " 43 free - 24 pric(0) " 5 trmskii(1) " 42 thctrl(2) Theta control 23 trmsk3(3) Mask TRACO 3 4 trmskii(0) " 41 thctrl(1) " 22 trmsk3(2) " 3 ghost2c Ignore corr ghost2 40 thctrl(0) " 21 trmsk3(1) " 2 ghost2 Disable ghost2 39 free - 20 trmsk3(0) " 1 ghost1c Ignore corr ghost1 38 carry Disable carry 19 trmsk2(3) Mask TRACO 2 0 ghost1 Disable ghost1 37 prios2 Priority order Sort 2 18 trmsk2(2) " Table 6: bit ordering in Configuration registers JTAG chain. Bit 55 and bit 0 are respectively the input and the output of the chain. 22

23 Appendix D: architecture of memory cells (a) Figure 16: (a) basic 1-bit cell for configuration registers (RW); (b) basic 1-bit cell of Snap registers (Read only). These cells can be accessed by the JTAG (shadowed) or by the PI (DataIN line). The JSEL line is used to select between the two access modes. (b) Figure 17: basic 1-bit cell of Test registers (RW). The cells can be accessed by the JTAG (shadowed) or by the PI (DataIN line). When the TestMode internal control line is set, the cells are concatenated to form a FIFO. 23

24 (a) Figure 18: (a) Boundary scan input cell; (b) Boundary scan output cell. (b) Figure 19: Boundary scan bi-directional cell. 24

25 Appendix E: technical specifications (Alcatel, CMOS 0.5 mm) Absolute Maximum ratings Supply Voltage, Vdd -0.5V to 6.0V Input or Output voltage DC Forward Bias Current, Input or Output -0.5V to (Vdd+0.5V) -24mA source, +24mA sink Recommended DC Operating Conditions Normal Operating Supply Voltage Vdd Extended Operating Supply Voltage Vdd Operating Ambient Temperature (Industrial) 3.3V +/- 10% (3.0V to 3.6V) 3.3V + 0.3V/-0.6V (2.7V to 3.6V) -40 to 85 degrees Centigrade TTL DC Electrical Characteristics Symbol Parameter Min Typ Max Vil Low Level Input Voltage 0.8V Vih High Level Input Voltage 2.0V Vol Low Level Output Voltage 0.2V 0.4V Voh High Level Output Voltage 2.4V 3.0V Vt+ Schmitt Trigger rising threshold 1.7V 1.9V Vt- Schmitt Trigger falling threshold 1.1V CMOS DC Electrical Characteristics Symbol Parameter Min Typ Max Vil Low Level Input Voltage 20% Vdd Vih High Level Input Voltage 80% Vdd Vol Low Level Output Voltage 0.2V 0.4V Voh High Level Output Voltage 85% Vdd 90% Vdd Vt+ Schmitt Trigger rising threshold 1.7V 1.9V Vt- Schmitt Trigger falling threshold 0.9V 1.1V Definition of operating conditions Worst Industrial Typical Best Industrial Process slow typical fast Temp. (Celsius degree) Voltage (V)

26 Process derating Process Derating factor slow 1.00 nom 0.78 fast 0.60 Voltage derating Voltage (V) Derating factor Temperature derating Temp. (C) Derating factor Power consumption (Typ cond W load on outputs) Clock rate Max absorbed current (ma) static MHz

27 Appendix F: package Package type: PQFP-120 Lead pitch: 0.80 mm Tip-to-Tip: 31.9 mm Foot Length: 0.88 mm 27

28 Appendix G: chip layout Chip area: 4.5x4.5 mm 2 Number of Standard Cells: Number of pads: 120 Number of input pads: 32 Number of output pads: 19 Number of bi-directional pads: 40 Number of Vcc for core: 2 Number of Gnd for core: 2 Number of Vcc for periphery: 12 Number of Gnd for periphery: 13 28

29 Appendix H: Alcatel library (I/O pads specifications) 29

30 30

31 31

32 32

33 33

34 34

35 35