DT Trigger Server: Milestone D324 : Sep99 TSM (ASIC) 1st prototype
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1 DT Trigger Server: Sorting Step 2: Track Sorter Master Milestone D324 : Sep99 TSM (ASIC) 1st prototype work of : M.D., I.Lax, C.Magro, A.Montanari, F.Odorici, G.Torromeo, R.Travaglini, M.Zuffa (INFN\Bologna) CMS\TRIDAS\Nov.,1999 M.Dallavalle\INFN\Bologna 1
2 DT on-chamber trigger electronics Muon DT chamber BTI TRACO TRACO BTI Trigger Server TSS TSM TSS Track 1 & 2 to MTTF O TSM is the last element o is a prinpipal requirement O a total of only 250 TSMs CMS\TRIDAS\Nov.,1999 M.Dallavalle\INFN\Bologna 2
3 Track Sorter Master requirements DT Trigger Server is a two-stage sorting tree (TSS+TSM). It collects track-segment candidates and outputs for Track Finding. Dimuon physics requires high quality for second segment. O Suppress noise and ghosts O detect and treat out-of-bx segments CMS\TRIDAS\Nov.,1999 M.Dallavalle\INFN\Bologna 3
4 Track Sorter Master requirements BX Tx 2 x 7 selected tracks Input B1 Data Mux & store Trk1&2 Input B2 Data Output Trk1 Mux & output Trk2 Track1 Track2 BX Select Select 2 x 7 TSS outputs Input B1 PRWs Noise & ghosts suppression Sort and store best 2 of B1 Input B2 PRWs Noise & ghosts suppression Sort and store best 2 of B2 Compare B1 & B2 Default mode. In back-up mode TSMD processing also includes sorting. CMS\TRIDAS\Nov.,1999 M.Dallavalle\INFN\Bologna 4
5 TSM I/O 4xDATA(24:0) TSMD0 I/O=141 24xCTRL,JTAG 7xPRW(12:0) TH1(7:0) TH2(7:0) TSMS I/O=168 Track1(24:0) Track2(24:0) TH(15:0) 3xDATA(24:0) TSMD1 I/O=116 TSM I/O=372+Vcc/G Each TSMD processes data from a half chamber TSMD redundancy TSMS can select two tracks in the same TSMD one track each TSMD CMS\TRIDAS\Nov.,1999 M.Dallavalle\INFN\Bologna 5
6 TSM architecture/technology options Architecture 1 TSMS-7w ASIC TSMD discr.comp 3 TSMS-4w ASIC 2 TSMD pasic 1 TSMS-7w pasic 2 TSMD pasic System cost (w/o PCB) System size Architecture robustness Latency Radiation hardness Prototyping cost Flexibility (proj-to-prot time) Design simplicity (ex:jtag) It is assumed TSMD0 = TSMD1. We favour a, which also allows more redundancy against failures. Two processing modes: Default: TSMS sorts on the TSS PRW infos and issues Selects that TSMDs use to output 2 tracks (2/0, 1/1, 0/2) -- Safe on failure of one TSMD Back-up: each TSMD sorts the best track among 4 and outputs one track -- Case of TSMS failure CMS\TRIDAS\Nov.,1999 M.Dallavalle\INFN\Bologna 6
7 TSM architecture/technology options Radiation tollerance: NASA TID tests antifuse technology shows rad-tolerant performance two possibilities: QuickLogic, Actel CMS\TRIDAS\Nov.,1999 M.Dallavalle\INFN\Bologna 7
8 pasic implementation: QuickLogic TSMS and TSMD0/1 implemented in 3 identical QL pasic3 QL3025-3PQ208C speed grade 3, 208 pins, PQFP, 174 I/O pins, 25K gates, 672 logic cells full JTAG four low-skew clock/control networks TSMS basic design completed. Used 90% of the chip resources. Sorting time within requirements. TSMD design for default mode is at simulation stage. Use 40% of chip resources. This will grow over 80% when back-up processing mode is implemented. CMS\TRIDAS\Nov.,1999 M.Dallavalle\INFN\Bologna 8
9 Test System: TSM test Board 6-layers PRW and DATA patterns and control bits provided through 3 Pattern Unit VME boards, 1 more Pattern Unit to read the output (LVDS). CMS\TRIDAS\Nov.,1999 M.Dallavalle\INFN\Bologna 9
10 Test System: Pattern Unit v.2 4K patterns of 128 VME board designed by I.Lax,F.Odorici CMS\TRIDAS\Nov.,1999 M.Dallavalle\INFN\Bologna 10
11 Test System set-up TSMS undergoing extensive tests. So far no major problem found. CMS\TRIDAS\Nov.,1999 M.Dallavalle\INFN\Bologna 11
12 JTAG Monitoring and Control TSM-TSS-TRACO-BTI are connected with a Parallel Interface (R.Martinelli) -- in program mode the data busses are reversed and access is given to the configuration/test registers the TSM interfaces with the DT chamber Controller. Details of the connection under study. CMS\TRIDAS\Nov.,1999 M.Dallavalle\INFN\Bologna 12
13 To-Do list Extensive test campaigne: performance in extreme conditions with final (un-homogeneous) cable lenghts validate two-processing mechanisms repeat for Actel implementation and further studies: possibility of two tracks out serially on one bus TSS-TSM communication in programming mode ( Parallel Interface ) and PRW bus driving conflicts neutron tests Proposed Milestones: May 2000: TSM prototype test results Nov 2000: full functionality TSM prototype CMS\TRIDAS\Nov.,1999 M.Dallavalle\INFN\Bologna 13
14 Conclusions The TSM architecture has been revised. The new architecture has a higher internal redundancy. The TSM functionality is distributed over three functional blocks which can be configured in several processing modes. A first prototype using 3 pasics QL3025-3PQ208 is under test Addenda: DT Trigger Server documentation: For the TSS: basic material in For the TSM: in preparation TSM design could be used also for DT Wedge and Barrel sorters CMS\TRIDAS\Nov.,1999 M.Dallavalle\INFN\Bologna 14
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