PTL-AND CLOCK-PULSE CIRCUIT DRIVEN NOVEL SHIFT REGISTER ARCHITECTURE

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1 PTL-AND CLOCK-PULSE CIRCUIT DRIVEN NOVEL SHIFT REGISTER ARCHITECTURE Nicee Staney Department of Electronics and Communication Engineering Rajagiri School of Engineering and Technology Kakkanad, Kochi, India Anand.S Department of Electronics and Communication Engineering, Rajagiri School of Engineering and Technology Kakkanad, Kochi, India Abstract In this paper, low power and area efficient 16-bit 2 SISO(Serial In Serial Out) shift register is proposed. In this P C L * proposed design, the master-slave flip-flops are replaced by pulsed latches called SSASPL(Static differential Sense-Amp Shared Pulsed Latch)in order to reduce the area and power consumption. The timing issue of the pulsed latch is overcome by generating multiple non-overlap delayed short pulsed clock signals instead of using single pulsed clock signal. The shift register is divided into sub shift registers to reduce the number of clock buffers. Two circuits of256-bitand a 16-bitshift register(driven by CMOS-AND based clock pulse generator) are also implemented for study and comparison with proposed design. The proposed 16-bit shift register is driven by PTL- AND based clock pulse generator and is implemented using CMOS 0.18μm technology in Cadence Virtuoso. The proposed 16-bit shift register using PTL-AND clock pulse circuit consumes 14% less power and 4% less area compared to CMOS-AND pulse generation circuit. Keywords Cadence Virtuoso, SISO, SSASPL, PTL logic I. INTRODUCTION Complementary Metal-Oxide-Semiconductor (CMOS) is a technology for constructing integrated circuits. Moore s law is considered as one of the most common description of the evolution of cmos technology. It states that as a result of continuous miniaturization, transistor count would get doubled every 18 months. As the no. of transistors increases, the switching activity also gets increased. Due to this, more power is dissipated in the form of heat. Heat is one of the main packaging challenge in this era. Power consumption is one of the top issues in VLSI circuit design, for which CMOS is the prominent technology. The two main sources of power consumption are: 1) Static power consumption 2) Dynamic power consumption * f dd clk (2) Shift register finds applications in digital filters, communication receivers and image processing ICs[15]. In some applications, as the word length of shift register increases the power consumption as well as area increases. So there is a need for designing a low power and area shift register. The architecture of shift register comprises sequencing elements such as latches or flip-flops. Latches are widely used in high-performance microprocessors. Flipflops are memory elements that are commonly used in the design of sequential circuits such as finite state machine controllers and pipelined circuits. Flip-Flops (FFs) and latches are responsible for a large fraction of the power budget of microprocessors and VLSI systems. Typically, they dissipate 80 % of the total clock power, and 30 % of the overall power budget. Latches impose a lesser overhead in terms of delay, clock load and area than flip-flops. Size(area) of a design is also an important metrics to be considered. Since power consumption and area is an important design metrics nowadays aiming at long battery life and portability for electronic devices, a low power and area efficient shift register is proposed. Reducing clock distribution network leads to low power consumption. The delayed pulse clock generator is a penalty of pulsed latches such that it also consumes power. Application of PTL logic to the AND gate in the clock-pulse circuit can effectively reduces area, power and delay by reducing the transistor count, interconnects and routing area. Replacement of flip-flops with pulsed latches saves more power and area because a pulsed latch is smaller than a master-slave flip-flop. The below Fig. 1(a) and (b) depicts the above fact. The occurrence of static power consumption is due to theleakage current generating in the circuit. Equation(1) shows the static power consumption. P(t) i dd (t) *V dd (1) Total chip power consumption is mainly due to the dynamic components. The occurrence of dynamic power consumption is mainly due to the switching activity of a circuit that causes charging and discharging of capacitor. It also depends upon the clock distribution networks that drive a circuit for its switching. It consumes nearly 90% of total dynamic power consumption. Equation(2) shows the dynamic power consumption /17/$ IEEE 1072 Figure 1. (a)master-slave flip-flop (b) Pulsed latch The rest of the paper is categorized as follows: Section II characterises the literature survey behind this work. Section III describes the architecture of 256-bit shift register[5], 16- bit shift register and proposed 16-bit shift register. Section IV denotes the results and discussions regarding the work. And finally the conclusion and future scope.

2 II. LITERATURE REVIEW Considering flip-flops, for an edge triggered flip-flop, the triggering circuit for each flip-flop is complex and race around conditions occur. To overcome this problem, masterslave flip-flops are used. Focusing on low power and area design, master-slave flip-flop is replaced by pulsed latch since it consumes more power and area compared to latter. So pulsed latches are preferred over the master-slave flipflop in the present study.anuja Kakde et al. (2017)[2] proposed 8-bit shift register using PFF(Pulse triggered Flip- Flop).Even though the power and area gets reduced using explicit type flip-flop, comparatively with present study, the no. of transistors in PFF is more than a single SSASPL in the present study(more area overhead). There are various other power reduction techniques including lock gating, power gating, creating multi-supply voltage designs and minimizing clock network. Among these, minimizing the clock network can reduce the dynamic power to a great extent. And it is the dynamic power which causes 90% of total power consumption. So minimizing the clock network as in the proposed design through sharing clock pulses can effectively reduces the dynamic power. Replacing PTL rather than CMOS and GDI[1], power and area can be reduced[8]. Bipankaushal et al.(2014)[10] proposed a shift register configuration with two-bit flip-flop. Flip-flop that stores one bit of data is replaced by multi-bit flip-flop by cascading single bit flip-flops that shares same driving strength. Thus it reduces the clock network as well as no. of flip-flops. As a result, power gets reduced. But it possess more area overhead as it is a master-slave flip-flop compared to present study. G.F Sudha et al.(2013)[11] proposed a shift register with reversible logic. It is one of the technique for power reduction. But it requires more no. of transistors and leads to more area compared to present study. A. Selection of Flip-flops and Latches Every flip-flops and latches will have either increased data activity or clock activity or output activity[9]. Among various flip-flop and latch designs, PPCFF(Power PC Flip- Flop) is the lowest power and area master-slave flip-flop, and SSASPL(Static differential Sense-Amp Shared Pulsed Latch) is the lowest power and area latch which is utilized for the proposed design. The 256-bit shift register using SSASPL driven with CMOS-AND clock-pulse generator[5] is compared with the conventional method using masterslave flip-flop(ppcff)and the proposed 16-bit shift register using SSASPL driven with PTL-AND clock pulse generator is compared with 16-bit shift register using SSASPL driven with CMOS-AND clock-pulse generator. The proposed design uses pulsed latches(ssaspl).the penalty of timing issue and pulse generator of pulsed latch is overcome in the proposed design. The timing issue is that, if a shift register is made up of several latches and a single pulsed clock signal as in Fig. 2, when the clock pulse arrives, it s previous input might not be constant during pulse resulting in uncertain output signal [5] as shown in Fig. 2. Figure 2. Schematic and waveform of shift register using pulsed latches with a single clock pulse To prevent the above problem, delay circuits are implemented in between latches or pulsed clock signals. But it increases area overhead. Another solution is to generate multiple non-overlap pulsed clock signals and share it with several latches as in the proposed design. III. METHODOLOGY 16-bit SISO(Serial In Serial Out)Shift register is proposed with different configuration. Two circuits of 256- bit shift register [5] and two 16-bit shift registers were implemented for study and comparison. The 256-bit shift registers and one 16-bit shift register were implemented using CMOS-AND pulse generator. The another 16-bit shift register was proposed using PTL-AND clock pulse generator. A master-slave flip-flop is replaced by a pulsed latch, which consists only a D-latch and a pulse signal. Single pulse generation circuit is used to generate multiple non-overlap delayed pulsed clock signals. All pulsed latches share this circuit for getting triggered. A pulsed latch consumes power and area half of those of master-slave flipflop[5]. The whole shift register is subdivided into P sub shift registers with each having a size S with S+1 latches(one temporary latch) [5]. It is subdivided to reduce the clock distribution network by sharing the limited no. of clock pulses by all sub shift registers. The no. of clock pulses generated depends on the size S of sub shift register. The block diagram of shift register with S=4 sub shift register is shown in Fig Figure 3. Block diagram of shift register with S=4 sub shift register[5] This architecture can effectively reduces the power related to clock distribution network due to sharing of clock pulses to various sub shift registers. The data gets shifted

3 according to the arrival of multiple pulsed clock signals. Rest of the time the data get stored in the corresponding latches. For an N-bit shift register, divided into P sub shift registers each having size S, there are S+1 latches in each sub shift register and S+1 clock-pulses generated. The P is considered to be N/S and no. of temporary latches is also N/S. The value of S depends upon various parameters discussed later. This shift register increases no. of latches, since each sub shift registers includes temporary storage latches. Each pulsed clock signal is generated from a clock-pulse circuit and clock buffer. Each clock-pulse circuit consists of AND gate, so that the generated pulse width can be shorter than the summation of rising and falling times[5]. The two inputs to the AND gate is the main clock signal and the delayed inverted clock signal. Whenever the two signals become high, the output becomes a pulse with a width of picoseconds range. A pulse with small width is enough to trigger each latches in the circuit. A CMOS-AND gate based clock-pulse circuit is used in the delayed pulse generator of 256-bit shift registers [5] and one 16-bit shift register whereas, PTL-AND gate based clock-pulse circuit is used in the proposed 16-bit shift register. Fig. 4 shows the schematic of delayed pulse clock generator. The max. value of S is limited to clock frequency. For a max. frequency, min. clock cycle time(t min_clk )is T cp + S *T delay +T cq [5], where T cp and T cq are the delay from rising edge of main clock signal to first pulsed clock signal[pulsed clk<temp>] and delay from rising edge of last pulsed clock signal[pulsed clk<1>] to falling edge of main clock period. T delay is the delay between consecutive pulsed signals. It is depicted in Fig. 5. Since frequency and time period are inversely proportional, as S increases the clock frequency decreases in proportion to 1/S. Figure 5. Minimum clock cycle time for proposed shift register The large clock pulse intervals cancel out effects of pulse skew differences. A. Selection of S Figure 4. Delayed clock-pulse generator[5] 1) Area Optimization The circuit areas are normalized with the latch. Therefore, the areas of clock-pulse circuit and latch are A and 1 respectively. The total area is given by A *(S+1)+N(1+1/S).The Optimal S(= N/ A )for minimum area is obtained from first order differential equation of total area[5].the integer S for minimum area must be divisor of N(2,4,8,16,32...) which is nearest to N/ A. 2) Power Optimization The circuit powers are normalized with the latch. Therefore, the power of clock-pulse circuit and latch are P and 1respectively. The total power is given by P *(S+1)+N(1+1/S).The optimal S(= N/ P )for minimum power is obtained from first-order differential equation of total power[5].the integer S for minimum power must be divisor ofn(2,4,8,16,32...) which is nearest to N/ P. 3) Speed B. SSASPL design SSASPL stands for Static differential Sense-Amp Shared Pulsed Latch. It is the most low power D-latch among other latches. SSASPL with 9 transistors[9] is modified to one that possess only 7 transistors by removing an inverter [5]. There are two inputs: one is (D) and its complementary data(db). The clock load to this circuit is one, ie, a single transistor is driven by pulsed clock signal. It consists of two cross coupled inverters and three NMOS transistors as shown in Fig. 6. As a result, it consumes less power and area too. Therefore, this latch is chosen for the previous 256-bit, 16- bit shift register and proposed 16-bit shift register. Here considering the power, the clock load to the latch is only one and the no. of transistors are less. When no. of transistors are less, the switching activity get reduced. As a result, the power consumption also gets reduced. It also leads to reduction in area too when compared to PPCFF with 16 transistors(clock load=8) which is the lowest power and area master-slave flip-flop. Figure 6. SSASPL(Static differential Sense Amp Shared Pulsed Latch)[9] The cross coupled inverters stores data and three NMOS transistors updates the data. 1074

4 C. 256-bit Shift Register and 16-bit Shift register[5] The shift registers are driven by CMOS-AND gate based pulse generation circuit as shown in Fig. 4. The CMOS- AND gate consists of six transistors as shown in Fig. 7. The architecture of these shift registers are made up of SSASPL. (= N/ P = 16/ 25.31).The shift register is proposed for power optimization. Considering area optimization for 16-bit shift register, the area of clock-pulse circuit without clock buffer is 4.29times ( =4.29)greater than a latch. Therefore, optimal S is 2 nearest to 1.92 (= = 16/ 4.29). Since it is a shift register of short word length, chosen values of S are same for circuits of power and area optimization. For power and area optimization, it is shift register with S=2 sub shift registers and three pulsed clock signals. Figure 7. CMOS AND gate Considering the power optimization for 256-bit shift register, the power of single clock-pulse circuit without clock buffer is times( P =26.56)greater than a latch. Therefore, optimal S is 4 nearest to 3.10(== N/ P = 256/ 26.56). Considering area optimization, the area of clock-pulse circuit without clock buffer is 4.96 times ( =4.96)greater than a latch. Therefore, optimal S is 8 nearest to 7.18 (= N/ A =).Two circuits of 256-bit shift registers are implemented based on power and area optimization. For power optimization, it is shift register with S=4 sub shift registers and five delayed pulsed clock signals. And for area optimization, it is shift register with S=8 sub shift registers and nine delayed pulsed clock signals. Considering power optimization for 16-bit shift register, the power of clock-pulse circuit without clock buffer is 26.56times greater than a latch. Therefore, optimal S is 2 nearest to 0.77(= N/ P = 16/ 26.56). Considering area optimization for 16-bit shift register, the area of clock-pulse circuit without clock buffer is 4.96 times ( =4.96)greater than a latch. Therefore, optimal S is 2 nearest to 1.79 (= = 16/ 4.96). Since it is a shift register of short word length, chosen values of S are same for circuits of power and area optimization(no much difference). D. Proposed 16-bit Shift Register The shift register is driven by PTL-AND gate based pulse generation circuit as shown in Fig. 4. PTL-AND gate consists only two transistors as in Fig. 8. The PTL defines Pass Transistor Logic. The CMOS-AND clock pulse generator is replaced with the PTL-AND clock pulse generator. Comparatively, it reduces the power of clockpulse circuit and leads to power reduction in 16-bit shift register. Even though the output voltage level decreases shortly, it is maintained using the clock buffers. Considering the power optimization, clock-pulse circuit without clock buffer is times (( P =25.31)greater than a latch. Therefore, optimal S is 2 nearest to 0.79 IV. Figure 8. PTL-AND gate [7] RESULTS AND DISCUSSIONS The SSASPL was simulated with 0.18μm CMOS process at VDD=1.8V. The sizes (W/L ) of the three NMOS transistors are(1μm/0.18μm)[5]. The sizes of NMOS and PMOS transistors in the two inverters are all (0.5μm/0.18μm). The clock pulse width of 210ps was selected for the simulation. The schematic of timing issue of shift register using pulsed latches is shown in Fig. 9. As described in Fig. 2, uncertain output is obtained due to setup time violation. Setup time violation occurs when an input does not become constant before a clock pulse arrives. Figure 9. Schematic of shift register using pulsed latches with single clock pulse The waveform of obtained result for the shift register using pulsed latches with single clock pulse is shown in Fig

5 .. Figure 12. ayout of S=4 clock-pulse generator Figure 10. Waveform of shift register using pulsed latches with single clock pulse In the above waveform, the first signal depicts the input, second signal depicts the same clock pulses, third signal depicts the first output from the first latch and fourth signal depicts the second output from the second latch. From the above waveform, it is clear that the output of first latch which acts as an input to the second latch is not constant during the clock pulse. This causes a problem of obtaining uncertain output in the second latch. The above problem is resolved using multiple delayed clock-pulse generator. Here, each latch of subshift register is triggered by different pulses that are delayed. A. Implementation results of study of 256-bit shift register and 16-bit shift register Considering the 256-bit shift register for S=4 (power optimization),cmos-and based clock-pulse generator generates five delayed pulses. Fig. 11 shows the waveform of clock-pulse generator for S=4. Each pulse generated from this circuit triggers each five latches of a sub shift register with size S=4. The no. of clock buffers required are less when compared with conventional shift register with PPCFF. In conventional shift register each flip-flop is driven by separate clock buffers. This leads to more area and power consumption in the conventional design. This problem is rectified in the 256-bit shift register using CMOS-AND clock pulse circuit that uses only five clock buffers for circuit with S=4. In conventional method it requires 256 clock buffers in total. Fig. 13 shows the waveform of S=4 256-bit shift register. The outputs are taken from four stages Q1,Q2,Q3 and Q4 in the waveform that depicts the shifting. The power consumption of this circuit is 1.6μW. A single SSASPL consumes 3.2μW. Figure 13. Waveform of S=4 256-bit shift register Considering the area optimization for 256-bit shift register driven by S=8 clock-pulse generator generates nine delayed pulses. Fig. 14 shows the waveform of clock-pulse generator for S=8. The power consumption of the S=8 clock pulse generator is mw. Figure 14. Waveform of S=8 clock pulse generator The total area consumed by S=8 clock-pulse generator is 10236μm 2 as shown in Fig. 15.The layout consists of nine clock-pulse circuits to produce nine delayed pulsed clock signals. Figure 11. Waveform of S=4 clock-pulse generator The power consumption of S=4 clock pulse generator is0.555 mw. The power of a single pulse circuit is 85μW. The total area consumed by S=4 clock-pulse generator is 6366μ m 2 as shown in Fig. 12. Figure 15. Layout of S=8 clock pulse gnerator 1076

6 The waveform of S= bit shift register is shown in Fig. 16. The outputs are taken from two stages Q1 and Q2. The shifting is shown in Fig. 16(a) and Fig. 16(b). The average power consumed by the S=8 256-bit shift register is 1.9μW. TABLE I. A (a) Waveform of S=8 256-bit shift register with the beginning of first stage output Figure 16. (b) Waveform of S=8 256-bit shift register with the beginning of second stage Waveform of S=8 256-bit shift register The layout of single SSASPL is shown in Fig. 17. The area consumed by single SSASPL is μm 2. The total estimated area consumed by S=4 256-bit shift register is52130μm 2. Further area can be reduced by sharing all possible drains and sources in the layout[5]. T Figure 19. Waveform of S=2 16-bit shift register The power consumption of PTL-AND clock pulse generatoris less than that of CMOS-AND clock pulse generator.the power consumed by above circuit is 0.158mW whereascmos-and clock pulse generator for 16-bit shift register is 0.192mW. The layout ofptl-and gate is shown in Fig. 20. Figure 17. Layout of Single SSASPL B. Implementation results of proposed 16-bit shift register Considering the proposed16-bit shift register for S=2(power optimisation and area optimization),triggered by the PTL-AND clock pulse generator, the waveform of clockpulse generator is shown in Fig. 18. Figure 18. Waveform of S=2 clock pulse generator Here, the same clock pulses are generated with amplitude of 1.8V. The waveform of proposed 16-bit shift register is shown in Fig. 19. Figure 20. Layout of PTL-AND gate The area consumed by the PTL-AND gate is μm 2 whereas CMOS-AND gate possess 142.9μm 2. The total estimated area consumed by the delayed pulsed clock generator using PTL-AND gate is 3532μm 2. Whereas the total estimated area consumed by the delayed pulsed clock generator using CMOS-AND gate is 3819μm 2. C. Performance comparison Two 256-bit shift registers(power and area optimization) using CMOS-AND based clock-pulse generator were implemented for the purpose of study. Table I shows the performance comparison of SSASPL and PPCFF. This design uses SSASPL and is compared with conventional design with PPCFF. TABLE I No. of transistors PERFORMANCE COMPARISON OF SSASPL AND PPCFF PPCFF SSASPL Type Flip-flop Pulsed latch Total 16 7 Clock 8 1 Power[μW]@f_clk=100MHz (38.9%) Area(μm 2 ) (26%) The Table I shows the power and area reduction in SSASPL compared to PPCFF in conventional design. The power and area of SSASPL is 38.9% and 26% of PPCFF respectively. The Table II shows the performance comparison of whole 256- bit shift register. 1077

7 TABLE II PERFORMANCE COMPARISON OF 256- BITCONVENTIONALSHIFT REGISTER AND 256-BIT SHIFT REGISTER USING CMOS-AND CLOCK GENERATOR Type Word length of shift register(n) Word length of sub shift registers(s) Total no. of flip-flops or pulsed latches Area[μm 2 ] Conventional Shift register PPCF (Flip-Flop) Total Flip-flop or pulsed latch Clock buffer Clockpulse Shift register using (CMOS-AND) 256 SSSASPL (Pulsed latch) (37. 7%) 51400(3 7.2%) (66.7%) 1.9 (79.2%) The Table II shows that the power and area is reduced in the shift register with CMOS-AND clock-pulse circuit. The area can be further optimized and reduced by sharing all the possible drains and sources in the layout [5]. The area of shift register with S=4 is only 37.7% and with S=8 is only 37.2% of conventional shift register. Similarly, the power of shift register with S=4 is only 66.7% and with S=8 is only 79.2% of conventional shifter. Fig. 21 shows the area and power consumption of 256-bit shift register. AND clock-pulse circuit consumes further less power and area than the conventional method. TABLE IIIdPERFORMANCE COMPARISON OF 16-BIT SHIFTREGISTER WITH CMOS-AND CLOCK PULSE CIRCUITAND PROPOSED 16-BIT SHIFT REGISTER WITH PTL-AND CLOCK PULSE CIRCUIT Shift register (CMOS-AND) Shift register (PTL-AND) Type SSASPL SSASPL Word length of shift register(n) Word length of sub shift registers(s) 2 2 Total (96.04%) Total Flip-flop or Estimated pulsed latch area[μm 2 ] Clock buffer Clock-pulse (84.2%) Fig. 22 shows the power and area consumption of 16-bit shift register with PTL-AND clock-pulse circuit. Figure 22 Area and power consumption of 16-bit shift register with PTL-AND logic clock pulse circuit The shift register circuit with PTL-AND gate based clock pulse circuit consumes less power and area compared to one with CMOS-AND gate based clock-pulse circuit. Here, the no. of transistors of delayed pulsed clock generator gets reduced from 64 transistors to 52 transistors. Hence, the area and power of pulse generator gets reduced which is penalty for pulsed latches. Figure 21. Area and Power consumption of 256-bit shift register From the above graph, its clear that the power and area optimization mainly depends on the value of S. For a 256-bit shift register, the optimized design is for S=4 and S=8. The value of S depends upon power and area optimization calculation for a particular word length of shift register. Here, for 256-bit shift register the minimum value of power and area is for S=4 and s=8 respectively. But as the value of S increases the speed decreases. So for the chip design S=4 shift register is appropriate. Implementation of proposed 16- bit shift register further reduces the power and area because of the usage of PTL-AND gate clock pulse circuit. The Table III shows the comparison of 16-bit shift register with CMOS logic and PTL logic AND clock-pulse circuits respectively. It is found that the shift register with PTL- CONCLUSION AND FUTURE SCOPE Hence this paper proposed a low-power and area efficient 16-bitshift register using pulsed latches. A 256-bit shift register and16-bit shift register driven with CMOS- AND clock pulse circuit were also implemented for study and comparison. Area and power of shift register is reduced by replacing master-slave flip-flop with pulsed latch and replacing CMOS-AND with PTL-AND gate. A 256-bit shift register(ssaspl) and 16-bit shift register with CMOS- AND pulse circuit and proposed 16-bit shift register(ssaspl) with PTL-AND pulse circuit were simulated at 100Mhz frequency and VDD=1.8V. The shift register with PTL-AND pulse circuit consumes further less power and area compared to those with CMOS-AND pulse circuit. The 256-bit circuit saves 33.3% of power and 62.2% of area compared to conventional design. The proposed 16- bit shift register with PTL-AND clock pulse circuit saves 14% of power and 4% of area compared to those with 1078

8 CMOS-AND pulse circuit. In future work, shift register(ssaspl) with higher order bits can be implemented with PTL-AND clock pulse circuit. The SISO can be changed to different configurations such as SIPO, PISO and PIPO so that it can find applications in various other fields. REFERENCES [1] N. Sathya, M. Anto Bennet, G. Hemapriya, S. Mohanambal, and A. Nandhini, Analysis of shift register using GDI AND gate and SSASPL using Multi Threshold CMOS technique in 22nm technology, International Journal of Innovation and Scientific Research, vol. 22, no. 2, pp , April [2] Anuja Kakde and BL. Malleshwari, Design of low power 8-bit shift register using PFF, Imternational J. of Emerging and Engineering Research and Technology, vol. 5,no. 1, pp 28-33, January,2017. [3] J. Montanaro et al. A160-MHz,32-b,0.5-W CMOS RISC processor IEEE J. Solid State Circuits,vol. 31,no.11,pp ,Nov [4] Y. Ude et al.6.33mw MPEG audio decoding on a multimedia processor, IEEE International Solid-State circuits Conf. Pp ,2006. [5] Byung-Do Yang, Low-Power and Area-Efficient Shift Register Using Pulsed Latches, IEEE Trans. on Circuits and systems. vol. 62, no. 6, pp , [6] Partha Bhattacharyya Bhattacharyya,Bijoy Kundu, Sovan, Ghosh, Vinay Kumar and Anup Dandapat, Performance Analysis of a Low- Power High-Speed Hybrid 1- bit Full Adder Circuit, IEEE Trans. Very Large Scale Integration (VLSI) systems. pp. 1-8, [7] Tripti Sharma and K. G. Sharma, High Performance and Function Design on the Transistor Level, International Journal of Computer Applications. vol. 78,no. 10,pp , [8] Paras Gupta, Pranjal Ahluwalia, Kanishk Sanwal and Peyush Pande4, Performance Comparison of Digital Gates using Cmos and Pass Transistor Logic using Cadence Virtuoso, International Journal of Science Technology & Management. vol. 4,no. 1,pp , [9] Seongmoo Heo, Ronny Krashinsky and Krste Asanovic, Activity- Sensitive Flip-Flop and Latch Selection for Reduced Energy,IEEETrans. Very Large Scale Integration (VLSI) systems. vol. 15,no. 9,pp , [10] Shefali Sharma and Bipan Kaushal, Shift Register Design Using Two Bit Flip-Flop,IEEE Proceedings of 2014 RAECS UIET Panjab University Chandigarh [11] A.V.Ananthalakshmi and G.F.Sudha, Design of 4-Bit Reversible Shift Registers, WSEAS Trans. on Circuits and Systems. vol. 12,no. 12,pp , [12] Vladimir Stojanovic and Vojin G. Oklobdzija, Comparative Analysis of MasterSlave Latches and Flip-Flops for High-Performance and Low Power Systems, IEEE Journal of Solid-state Circuits. vol. 34,no. 4,pp , [13] A.Vasanthapriyanga and S.Sellam, Design and Analysis of Shift register using Dual- Dynamic Flip-Flop, International J. of AdvancedResearch Trends in Engineering and Technology vol. 3,no.24,pp , [14] Consoli, M. Alioto, G. Palumbo, and J. Rabaey, Conditional pushpull pulsed latch with 726 fjops energy delay product in 65 nm CMOS,IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers. pp , [15] H. Yamasaki and T. Shibata, A real-time image-feature-extraction and vector-generation vlsi employing arrayed shift register architecture, IEEE J. Solid-state circuits. Vol.42, no. 9,pp ,2007. [16] H.-S. Kim, J.-H. Yang, S.-H. Park, S.-T. Ryu, and G.-H. Cho, A 10- bit column-driver IC interpolation for mobile active-matrix LCDs,IEEE Trns. Control Syst. Technol. vol. 49, no. 3, pp , [17] S.-H. W. Chiang and S. Kleinfelder, Scaling and design of a 16- megapixel CMOS image sensor for electron microscopy,proc. IEEENucl. Sci. SympConf. Record (NSS/MIC)., pp ,