Post Silicon Electrical Validation Lecture 2. Tony Muilenburg

Transcription

1 Post Silicon Electrical Validation Lecture 2 Tony Muilenburg

2 Agenda Topics for Today Homework Q&A Escapes Future outlook Product lifecycle Manufacturing flow Validation Disciplines Electrical Validation Disciplines

3 Homework Q&A Questions about Homework 1? Homework 1 due Tuesday, Jan 14 at 7pm Every assignment due seven days later 7pm before class starts Hoping for preferred as soon as possible Reading assignments most useful before the next class

4 Recalls / Escapes

5 Effective SI is Pre-Product Release. It costs less here. 50 Cost of failure (M$) Why? Time = $ 0 Preprototype Validation Post Release Introduction Richard Mellitz

6 The Cost of Being Wrong

7 FDIV Pentium flaw was fixed, but some made it into the field From a calculator: type / * = hit the +/- key then = 256 (instead of 0 ) Floating Point error in the chip Initially repalced chips, but later replaced entire systems.

8 SNB Recall SATA may degrade over time Cost around $700 Million ($300M + $400M)

9 Boeing Jet Batteries

10 Firestone Tires

11 Bad press, not handled well

12 Use Cases

13 Future Outlook

14 Moore s Law Alive and Well

15

16 Some Players

17 Product Lifecycle

18 Product Life Cycle Validation cycle integrated in the Product Life Cycle (PLC) Validation coverage at each stage Specifications pushed to limits Product Release Qualification (PRQ) Granted if reliability and quality requirements met 18

19 19 PLC Details

20 Wafer to CPU

21 Manufacturing Flow

22 What Happens at Sort

23 Defect Examples

24 What Happens at Class

25 Product Platform Verification

26 Quality Assurance

27 Catching Defects

28 Survivability

29 Validation Disciplines

30 Post Silicon Validation Disciplines Performance validation, others

31 Validation Goals

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33 Communicating Status and Health

34 Example Activities Test WW Planned # of Repeats # of Cases Test Time (h) Overall Time (hr) Overall Time (d) % Canceled % Blocked % Complete Script checkout % 0% 100% Repeatability % 0% 100% BIOS Regression % 0% 40% DIMM configuration - DQ % 0% 100% DIMM configuration - CA % 0% 0% Debug % 0% 60% VT sweep % 0% 0% Board baseline % 0% 20% Eye test % 0% 100% Automation executive checkout % 0% 80% Termination impedance checkout % 0% 0% Voltage check % 0% 0% Totals % 0% 55.4%

35 Homework 2 Find the exercise on d2l.pdx.edu Under the lecture 2 module Create a plot for percent complete vs planned No need for the blocked or cancelled columns Due Jan 16 th, 7pm Weighting assumption Same for each activity Schedule Week Station/Platform setup Stability Repeatability Parameter sweep DIMM Config VTZ(s) Monte Carlo/ Stim comp Volume DOE(s) BER MRC Regression UPM

36 Electrical Validation 101

37 Agenda Introduction Discipline Summary SMV SIV Bench DV Tester DV

38 Introduction Multiple disciplines Many interfaces Teams across many geographies Tune recipes Optimization knobs Survivability knobs Find bugs Quantify health Provide UPM estimate

39 Importance of Electrical Validation Quantify system robustness over HVM Relatively limited data Predict over time Predict over spec. limits (voltage, temperature, etc) EV plays a major role in time to market Debug Bug fixes Interface speed limited by signal integrity EV can predict risk of pushing very high data transfer rates

40 Example EV Scope

41 Agenda Introduction Summary of Disciplines SMV SIV Bench DV Tester DV

42 EV Disciplines System Margin Validation (SMV) Signal Integrity Validation (SIV) Bench Design Validation (BDV) Others

43 Sample Size SMV: Quick test time, larger sample size Dozens or hundreds of CPUs Model and extrapolate to predict HVM SIV: Longer experiments, longer setup time Handful of CPUs BDV: Early engagement Handful of CPUs Focus is more on functionality

44 Example System

45 Example of Challenges (DDR) Dependence on manufacturer Many suppliers Different designs Many Configurations Single sides vs double ECC vs non-ecc UDIMM vs RDIMM vs SODIMM Motherboard dependence Routing differences Trace length, impedance differences Material differences (halide free, lead free, etc.)

46 Serial Interface Challenges Voltage swing is typically lower Measurement tools require low noise floors Load from instrument probes can corrupt the signal ISI risk due to jitter Very high speed signals Many bits, higher likelihood of bit errors

47 Agenda Introduction Discipline Summary SMV SIV Bench DV Others

48 System Margining (SMV) Interface robustness is characterized by: Measuring how far a reference can be offset until the system fails (margin) Examples include: Signal sampling timing Voltage reference level for logic high/low Many things impact margin Examples: Temperature, impedance, etc. Parameters are varied, performance variation captured Performance over HVM predicted Design modified if predicted failure rate is unacceptable

49 Typical Margining Equipment Examples of margining equipment include: Voltage supply and measurement Current supply Timing Equipment Frequency generator Intel s AVMC card can do all of this Temperature control CPU, PCH, DIMMs Silicon thermal, USTC In target Probe Step though execution, enable test modes, report errors

50 Example SMV Test Station

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52 Selecting Experiments Many operating conditions impact system performance Often there are interactions between conditions Often non-linear response Cannot test every combination of every parameter Parameter discovery experiments Run early on Reduce variables Make experiments tractable

53 Input and Response Experiments over operating conditions Results analyzed Failure rate predicted for HVM

54 Margining Parameters are swept from default settings to the point where data becomes corrupted (margining) Examples: Voltage reference Data vs clock timing Spec limits pushed Temperature Impedance Trace length Termination Note: You need to be in presenter mode to see this animation

55 Significance of Margin Interface robustness is characterized by margining Healthy systems have wide margin Still operate when design limits are pushed Tight margin indicates the system is close to failing Many systems will likely fail when high volumes are produced This error rate is quantified via statistical modeling Relevant operating conditions are determined via: Pre silicon experiments Historical knowledge Parameter sweep experiments

56 PVT Corners Process, Voltage, and Temperature are historically significant parameters These are of particular interest when picking test points Spec limits are pushed, margin is captured Parameters are co-varied to capture interactions Process can cover many properties Want to capture the distribution A corner describes a set of parameters set to spec limit Example: high impedance, cold temperature

57 Design of Experiment DOE methodology is used to: Pick test points intelligently using a software package Model the system After interpolating results, the model can predict Best and worst margin cases High volume response (average, distribution, etc.) Operating conditions are varied Timing or voltage margin response is measured

58 Example DOE Table

59 Margin Result Per Lane

60 Interpreting Results Response Surface Modeling (RSM) Typically used for system characterization Only a small set of measurements are needed Interpolation can be used to predict conditions Monte carlo is an alternative Results from all experiments contribute to a model A statistically significant number of CPUs should be used to predict response over HVM

61 Margin Distribution A margin distribution is generated from the model The model comprehends parameter weightings Guardband is added for parameters not measured The model should comprehend all significant effects

62 Defects per Million DPM can be estimated from the margin distribution Model accuracy should be verified Customer data can be included Test the model by verifying predictions with new measurements Results are communicated to stakeholders

63 Coverage

64 PRQ Risk Assessment Coverage Known Issues UPM / Margin

65 PRQ Risk Assessment Coverage Main methodology focus Known Issues UPM / Margin

66 PRQ Risk Assessment Coverage Known Issues Generally comprehended UPM / Margin

67 PRQ Risk Assessment Inadequate Coverage May miss key bugs May miss key margin / UPM impacts Known Issues UPM / Margin

68 What does coverage mean? Traditional (i.e. well comprehended) Process, Voltage, Temperature, Board Z, Trace length, package impedance, etc Fairly well covered in today s methods Non-traditional (perhaps not well comprehended) Circuit robustness Training stability Interoperability System concurrency Out of guideline designs Are we covering these areas consistently and adequately?

69 Agenda Introduction Discipline Summary SMV SIV Bench DV Others

70 Signal Integrity Validation (SIV) Signal quality measured vs spec Example Specs DDR JEDEC PCIe CEM Common tools High Speed Oscilloscope Bit error rate testers (BERT) Vector network analyzers (VNA) Time domain reflectometry (TDR) Debug

71 Signal Integrity Validation (SIV) Activities include: SMV results verification Measurements SMV cannot cover due to lack of hooks Specification compliance Prove robustness of: Transmitter Receiver Link Debug signal integrity issues Comparison of results to customer results Special tests / designer experiment requests

72 Signal Integrity Issues Some issues that reduce margin include: Impedance mismatch Poor termination Crosstalk Ground Bounce Intersymbol interference Simultaneous switching Poor routing Poor materials Insufficient decoupling Cheap packaging Insufficient power delivery

73 Example Waveform

74 Coverage Both serial and parallel interfaces System level measurements This captures issues with: Packaging Reflections Routing Noise budget Increasing interface speeds Decreasing operating voltages

75 Methods Eye captures over different: Operating conditions Multiple CPUs Compliance testing for: Standard industry interfaces (DDR, PCIe, etc.) Well documented Non-standard interfaces (DMI, QPI, etc.) Not well documented Many similarities between interfaces

76 Selecting Experiments Knowledge of potential issues is key Examples: jitter, signal loss, circuit characteristics Factors at each level Chip Package Board Volume vs corner checking

77 Eye Mask Eye health Shape is an indicator Mask use is common Example of a good and bad eye The signal on the right is attenuated Large amount of jitter

78 Running Experiments More debug early on Manual overrides Stepping through code Recipe tuning Lots of BIOS images High level automation as stability is achieved 24 hour testing Infinite persistence captures Still requires human intervention for: Card or board swapping CPU swapping if a robotic handler is not available Results are stored to a database Post processed using JMP, summarizers, etc.

79 BERT for Example Setup PCIe Signal generation and error checking Two RF switches Compliance load board (CLB) System board (DUT) Clock generator Clean clock testing.

80 Interpreting Results Spec comparison Margin analysis BER and UPM leveraged from SMV results Difference between margin and spec limit Long dwell infinite persistence Probe or cable loss comprehended Compare to projects with similar interfaces Use sightings to track issues Tune recipe Impedance compensation (margin vs power) Equalization

81 Agenda Introduction Discipline Summary SMV SIV Bench DV Others

82 Bench DV Introduction Covers analog behavior of silicon Silicon that can go in many platforms Does the part meet external specs (EMTS, EDS) Analog Components Supporting circuitry Thermal Power delivery Clocking Works closely with SMV Covers PVT, but often pushes past spec limits Pushing past spec limits will be representative of worst case silicon at spec limits Possible to run with no OS by injecting traffic

83 BDV Cycle Gather spec requirements Test plan Generation Include tuning, calibration hook, hardware in the design Generate test conditions Run experiments, opening bug sightings Generate yield analysis Close sightings Feed results into PRQ recommendation

84 Methods More specialized testing than other disciplines Especially for new interfaces A set of traditional tests still exist Difficult to automate due to unique experiments Circuitry with impact on external behavior Example: IO swing calibration Different implementations - unique test requirements Recipe tuning Degradation over time Yield concerns

85 Close Ties with Design Deep understanding of circuits Often designers own BDV planning and/or execution Work closely with other disciplines Careful not to duplicate effort Often ask other disciplines to carry our experiments Recipe tuning regression is an example

86 Execution Examples Effect of power supply noise on band gap reference Glitch filter performance on a slow I/O Receiver clock bias setting

87 Agenda Introduction Discipline Summary SMV SIV Bench DV Others

88 Tester DV Component level design validation Does not focus on platform interactions Focus is on characterization of design goals in: Controlled environment Pristine conditions for power deliver, and signal integrity PVT coverage Close ties with HVM HVM tests every part shipped to customers Wafer level and post packaging Inline DV (ILDV) large amount of data collected per part Great for data mining

89 Power Delivery Validation (PDV) Sufficient power Stable power All parts of the die

90 An Eye is Born

91 Reading assignment High speed digital designs chapter 1 Link: Heck and Hall (This chapter is free online)