Hspice CML IO Kit User s Manual

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1 Hspice CML IO Kit User s Manual Simulation of Lattice SC and ORCA Product CML SERDES Interfaces OVERVIEW The Lattice HSpice IO Kit contains a collection of HSpice model files that allow SERDES serial data link simulation across a PCB module or backplane hardware system. The SERDES buffer models are extracted from product final design files and have been found to closely reflect real device performance. The flexible, high-resolution capabilities of HSpice simulation allow signal integrity assessment of hardware device and interconnection designs. The HSpice IO Kit is available to Lattice customers and prospective customers under NDA. This document describes the HSpice simulation files provided in the IO Kit and how to use them to perform some basic PCB interconnection design signal analysis. A top level HSpice simulation file is described, that allows selection and adjustment of hardware elements, operational parameters, and simulation conditions are described for a single data channel Tx driver to Rx receiver path. The signal path can include different SERDES buffers, device packages, backplane connectors, and PCB transmission line traces, which are included in the IO Kit model library. Signal eye-diagram waveform analysis is used to display data signals as they propagate across the signal path of the system under test (SUT). Several simulation examples are presented in this document, for different Lattice product SERDES buffers HSpice models included in the IO Kit. Different PCB interconnection designs schemes as presented, to demonstrate the range of possible application simulations. The customer is encouraged to replace or modify the board level element HSpice models with one appropriate to represent his specific application. SIMULATIOR SOFTWARE AND FILE STRUCTURE Synopsys HSpice Version or later is recommended for use with this kit. It is assumed that the user has a working knowledge to the HSpice tool. Performing a simulation requires a top-level (.sp type) file that is loaded by the HSpice simulator, prior to running. It in turn selects all the appropriate element model files that are needed..include statements in the top file identify actually link the element model files. These files reside in the LIBR directory of the IO Kit. The top file usually also contains simulation selection statements and output waveform statements that control the simulator operation and output file generation. Experienced HSpice simulation users may generate or may already have their own top-level simulations files that include other portions of their application system. They may choice to just use the buffer and package model files that are provided in the IO Kit, calling them into their top-level simulation file. The user will simply need to identify the IO Kit files (models) of interest and provide appropriate instantiation, connection and stimulation. This information needed to do this can be found the details of the IO Kit top file and the comments contained in the specific model files of interest. Note that some of the model files have been encrypted to protect Lattice proprietary information. The encryption is transparent to the HSpice simulation tools. 1 2/6/26

2 TESTBENCH A generic testbench.sp file is provided that configures a signal path topology across a backplane, as is shown at the top of the Figure 1. FIGURE 1 P1 P2 P3 P4 P5 P6 P7 P8 OUTP Data Pattern Gen TX buffer Device package 1 Line Card 1 Conn ector 1 Back plane Conn ector 2 Line Card 2 Device package 2 RX buffer N1 N2 N3 N4 N5 N6 N7 N8 OUTN Library Models (files): Pats_prbs7 Pats_prbs31 Pats_cjpat Pate_prbs7 Pate_cjpat Pkg1_null Pkg1_68 Pkg1_484 Pkg1_136 Pkg1_sc9b Pkg1_sc9w Pkg1xt_sc9 Pkg1_sc1152b Pkg1_sc1152w Pkg1xt_sc1152 Conn1_null Conn1_gbx_ab Conn1_gbx_jk Conn2_null Conn2_gbx_ab Conn2_gbx_jk Pkg2_null Pkg2_68 Pkg2_484 Pkg2_136 Pkg2_sc9b Pkg2_sc9w Pkg2xt_sc9 Pkg2_sc1152b Pkg2_sc1152w Pkg2xt_sc1152 Tx_4f Tx_4e Tx_4e_ors Tx_4e_ort Tx_SCf Tx_SCe Tx_SCe_fc Tx_SCe_wb Lc1_null Lc1_wele_3in Lc1_ms_5in Bp_null Bp_wele_6in Bp_wele_18in Bp_wele_3in Bp_sl_2in Bp_sl_3in Bp_sl_5in Bp_sl_6in Bp_ms_3in Lc2_null Lc2_wele_3in Lc2_ms_5in Rx_ideal Rx_4f Rx_4e Rx_4e_ors Rx_4e_ort Rx_SCf Rx_SCe Rx_SCe_fc Rx_SCe_wb This top-level file has provisions to select from most of the element models included in the IO Kit. One model from each of the library model boxes in Figure 1 is selected to configure a complete system for simulation. The left-most box of library files, in Figure 1, lists the available data test patterns to provide stimulus for the data link. Note that in each library file block a _null suffix file is included. Selection of this file eliminates the model for that block element and simply connects the input terminals to the output terminals. This configuration option 2 2/6/26

3 allows the user to remove a specific path from the simulation. Comparing this result to that with the element present can often provide useful information about the incremental effect of an element insertion into a system. The testbench.sp file specifies a transient type simulation analysis, with voltage waveform outputs saved for each nodes indicated. Additional output parameters are defined to permit observation of Different signals and eye-diagram signals. The simulation results may be displayed with the HSpice viewer Awaves, or other compatible viewers. In the simulation analysis & control section, the transient simulation time step size and overall time interval are specified in the.tran statement. These values should be adjusted by the user in different applications. The other control parameters of interest to the user are in various model files, as listed in the SIMULATION PARAMETER CONTROL section of this file. When the extracted buffer models are used, the device operating temperature may be specified in the.temp statement. The user may also select from three.dat files to assess the manufacturing process variations in buffer performance. mod_fast.dat and mod_slow.dat files represent worst case processing corner conditions of manufacturing for the Series 4 (ORSO and ORT products). Similarly for Lattice SC product: typical (TT), fast (FF) or slow (SS) process libraries maybe be selected. TESTBENCH LIBRARY FILE DESCRIPTION PATTERN GENERATION MODELS The digital vector file feature of HSpice is used to generate data pattern stimulus to the TX buffer models. In addition to the serial 1- pattern, each.dvf file sets the data bit rate of the simulation. The data bit period is set in the "period" line near the beginning of each file. The number in this line should be set to the desired data rate bit period (in ps). The following models are provided in the library: pats_prbs7.dvf This is an HSpice digital vector file designed to interface the functional TX buffer circuits tx_4f.cir, tx_scf,cir or the extracted model Lattice SC buffer tx_sce.cir. This file provides industry standard PRBS7 pattern (polynomial X^7+X^6+1). The 127 bit pattern is repeated twice in the file. pats_prbs31.dvf This is an HSpice digital vector file designed to interface the Lattice Series-4 FPSC TX buffer model tx_4f.cir or Lattice SC buffer tx_scf.cir. This file provides a segment of the PRBS31 (polynomial X^31+X^28+1). A variety of pattern characteristics can be seen in different regions of the overall sequence. A segment with longer run lengths and greater dc imbalance is provided. The segment is 512 bits long. pats_cjpat.dvf This is an HSpice digital vector file designed to interface the simplified TX buffer circuits tx_4f.cir or tx_5.cir. This file provides a shortened version of the CJPAT test pattern used in XAUI standards testing. It contains each of the repeating patterns found in the full length CJPAT. The total length is 32 bits. pate_prbs7.dvf This is an HSpice digital vector file designed to interface the extracted Series-4 FPSC TX buffer circuit, tx_extr.cir. This file provides industry standard PRBS7 pattern (polynomial X^7+X^6+1). The 127 bit pattern is repeated twice in the file. 3 2/6/26

4 pate_cjpat.dvf This is an HSpice digital vector file designed to interface the extracted TX buffer circuit tx_4e.cir. This file provides a shortened version of the CJPAT test pattern used in XAUI standards testing. It contains each of the repeating patterns found in the full length CJPAT. The total length is 32 bits. BUFFER MODELS Several different TX buffer models and RX buffer models are provided, as described below: tx_4f.cir This is a functional Series-4 FPSC TX buffer circuit. Its simplicity greatly reduces simulation run time. It is appropriate for initial system level alternative evaluations. This file can be modified to apply the half amplitude and pre-emphasis modes of the SERDES TX buffer, by "uncommenting" the appropriate statements in the file. The model must receive its stimulus from a pattern generation file (pats_*.dvf). tx_4e.cir This model provides the full transistor level, Series-4 device extracted buffer model. It provides the most accurate simulation result. Because of its size and complexity, longer simulation run times will be incurred. The two.include lines near the top of the file determine whether the ORT or ORSO buffer models are used. The commented line (first character a *) is ignored by the simulator. The uncommented line is read. Note: The ORT buffer model should be selected for ORSPI4 product simulation. This file provides some additional bias circuitry to operate the extracted model in the correct mode and calls the detailed model file (tx_4e_ors.cir or tx_4e_ort.cir). The model must receive its stimulus from an e type pattern generation file (pate_*.dvf). tx_scf.cir This is a functional model for the Lattice SC product TX buffer circuit. Its simplicity greatly reduces simulation run time. It is appropriate for initial system level alternative evaluations. This file can be modified to select 1 of 4 different amplitude levels and 1 of 4 different pre-emphasis modes, by "uncommenting" the appropriate statements in the file. The model must receive its stimulus from a pattern generation file (pats_*.dvf). tx_sce.cir This model provides the full transistor level, Lattice SC device extracted buffer model. It provides the most accurate simulation result. Because of its size and complexity, longer simulation run times will be incurred. The two.include lines near the top of the file determine whether the wire-bond or the flip-chip buffer models are used. These model differ only in theoutput lead metallization parasitics. The commented line (first character is *) is ignored by the simulator. The uncommented line is read. This file provides some additional bias, clock and control circuitry to operate the extracted model in the correct mode. It calls the detailed model file (tx_sce_fc.cir or (tx_sce_wb.cir). The model must receive its stimulus 4 2/6/26

5 from a s type pattern generation file (pats_*.dvf). The TX Buffer Parameter Control Section of this file allows the user to select buffer output impedance level, the output amplitude and 1 of 4 levels of output pre-emphasis. Selections each of these functions are made by uncommenting the appropriate lines. rx_ideal.cir This model is simply two 5 ohm resistors that are terminated to VDDIB. It represent the ideal external TX buffer signal termination. When comparing simulation results to 5 ohm oscilloscope measurement, connected through a bias-tee element, this is the recommended RX model. No buffer output signals are provided. rx_4f.cir This simplified RX buffer model provides approximate nominal input impedance of the Series-4 buffer input, in Thevenin equivalent form. It includes parasitic input capacitance. No buffer output signals are provided. rx_scf.cir This simplified RX buffer model provides approximate nominal input impedance of the Lattice SC buffer input, in Thevenin equivalent form. It includes parasitic input capacitance. No buffer output signals are provided. rx_4e.cir This model provides the full transistor level, extracted RX buffer model (first stage only). It provides the most accurate simulation result. Because of its size and complexity, longer simulation run times will be incurred. The two.include lines near the top of the file determine whether the ORT or ORSO buffer models are used. The commented line(first character is *) is ignored by the simulator. The uncommented line is read. Note: The ORT buffer model should be selected for ORSPI4 product simulation. This file provides some additional bias circuitry to operate the extracted model in the correct mode and calls the detailed model file (rx_4e_ors.cir or tx_4e_ort.cir). The models differential signal output nodes are designated outp and outn. rx_sce.cir This model provides the full transistor level, extracted Lattice SC RX buffer model. It provides the most accurate simulation result. Because of its size and complexity, longer simulation run times will be incurred. The two.include lines near the top of the file determine whether the wire-bond or the flip-chip buffer models are used. These model differ only in the input lead metallization parasitics. Selections each of these functions are made by uncommenting the appropriate lines. This file provides some additional bias and control circuitry to operate the extracted model in the correct mode and calls the detailed model file (rx_sce_wb.cir or rx_sce_fc.cir). The models differential signal input nodes are designated p8 and n8. The differential signal output has pin designations outp and outn. The Rx buffer configuration setting section of the file allows the user to select the internal termination value, ac or dc internal coupling, and 1 of 3 levels of equalization. PHYSICAL PATH ELEMENT MODELS IC Package 5 2/6/26

6 Device package models are provided for 68 PBGA package. The 3D field solver generated model approximates parasitic impedance elements of the signal connection path between the silicon chip bond pad and the PCB ball pad. Only the P and N signal leads of a single signal pair and ground are included in the model. The model includes package substrate and wire bond portions of the interconnection. pkg1_484.cir This model represents the TX output signal connection path through the 484 pin PBGA package. This is the package available with the ORSO42G5 and ORT42G5 products. pkg1_68.cir This model represents the TX output signal connection path through the 68 pin PBGA package. This is the package available with the ORSO82G5 and ORT82G5 products. pkg1_sc9b.cir This model represents a best case (shorted path length) TX output signal connection path through the 9 pin PBGA package used with the LATTICESC 25 product. pkg1_sc9w.cir This model represents a worst case (longest path length) TX output signal connection path through the 9 pin PBGA package used with the LATTICESC 25 product. pkg1xt_sc9.cir This model reflects package lead cross-coupling between adjacent TX output signal connection paths through the 9 pin PBGA package used with the LATTICESC 25 product. The testbench passes the active signal channel through the 2 nd pair of 4 adjacent HDOUT pair paths. The other 3 TX trace pairs are terminated with 5 ohms to ground at both the IC and PCB ends. The cross-talk signal received on each of the undriven lead terminations may be observed from the testbench simulation run. The undriven trace nodes are nxa, nxb, pxa, and pxb, where a and b indicates the IC and PCB ends (respectively) of the package paths, and x is, 2, and 3, indicating the 3 undriven trace pairs. pkg1_sc1152b.cir This model represents a best case (shorted path length) TX output signal connection path through the 1152 pin flip-chip BGA package used with the LATTICESC 25 product. pkg1_sc1152w.cir This model represents a worst case (longest path length) TX output signal connection path through the 1152 pin flip-chip BGA package used with the LATTICESC 25 product. pkg1xt_sc1152.cir This model reflects package lead cross-coupling between adjacent TX output signal connection paths through the 1152 pin flip-chip BGA package used with the LATTICESC 25 product. The testbench passes the active signal channel through the 2 nd pair of 3 adjacent HDOUT pair paths. The other 2 TX trace pairs are terminated with 5 ohms to ground at both the IC and PCB ends. The cross-talk signal received on each of the undriven lead terminations may be observed from the testbench simulation run. The undriven trace nodes are nxa, nxb, pxa, and pxb, where a and b indicates the IC and PCB ends (respectively) of the package paths, and x is and 2, indicating the 2 undriven trace pairs. pkg1_136.cir This model represents the TX output signal connection path through the 136 pin PBGA package. This is the package available with the ORSPI4 products. pkg1_null.cir This is the zero order model which essentially eliminates the element from the simulation signal path. It provides a zero delay, zero parasitic impedance connection between adjacent elements. 6 2/6/26

7 pkg2_484.cir This model represents the RX input signal connection path through the 484 pin PBGA package. This is the package available with the ORSO42G5 and ORT42G5 products. pkg2_68.cir This model represents the RX output signal connection path through the 68 pin PBGA package. Pkg2_sc9b.cir This model represents a best case (shorted path length) RX output signal connection path through the 9 pin PBGA package used with the LATTICESC 25 product. Pkg2_sc9w.cir This model represents a worst case (longest path length) RX output signal connection path through the 9 pin PBGA package used with the LATTICESC 25 product. Pkg2xt_sc9.cir This model reflects package lead cross-coupling between adjacent RX input signal connection paths through the 9 pin PBGA package used with the LATTICESC 25 product. The testbench passes the active signal channel through the 2 nd pair of 4 adjacent HDIN pair paths. The other 3 RX trace pairs are terminated with 5 ohms to ground at both the IC and PCB ends. The cross-talk signal received on each of the undriven lead terminations may be observed from the testbench simulation run. The undriven trace nodes are nxc, nxd, pxc, and pxd, where a and b indicates the IC and PCB ends (repectively) of the package paths, and x is, 2, and 3, indicating the 3 undriven trace pairs. Pkg2_sc1152b.cir This model represents a best case (shorted path length) RX output signal connection path through the 1152 pin flip-chip BGA package used with the LATTICESC 25 product. Pkg2_sc1152w.cir This model represents a worst case (longest path length) RX output signal connection path through the 1152 pin flip-chip BGA package used with the LATTICESC 25 product. Pkg2xt_sc1152.cir This model reflects package lead cross-coupling between adjacent RX output signal connection paths through the 1152 pin flip-chip BGA package used with the LATTICESC 25 product. The testbench passes the active signal channel through the 2 nd pair of 3 adjacent HDIN pair paths. The other 2 TX trace pairs are terminated with 5 ohms to ground at both the IC and PCB ends. The cross-talk signal received on each of the undriven lead terminations may be observed from the testbench simulation run. The undriven trace nodes are nxa, nxb, pxa, and pxb, where c and d indicates the IC and PCB ends (repectively) of the package paths, and x is and 2, indicating the 2 undriven trace pairs. pkg2_136.cir This model represents the RX input signal connection path through the 136 pin PBGA package. This is the package available with the ORSPI4 products. pkg2_null.cir This is the zero order model which essentially eliminates the element from the simulation signal path. It provides a zero delay, zero parasitic impedance connection between adjacent elements. Line Card and Backplane PCB traces 7 2/6/26

8 Printed circuit board transmission line connections are modeled with the HSpice W-element lossy transmission line element. This model is well accepted in the industry and includes provisions for frequency dependent copper and dielectric loss. The line card and backplane model file described below use RLC form models. The wele named files represent two matched 5 ohm lines with no coupling provision between the two (P and N signal) lines. The loss parameters used are intended to approximate the losses of a FR4 stripline structure, but they have not verified for accuracy. The ms named files represent micro-strip, FR4 structures which are comparable in loss to a real structure with 8 mil edge coupled P and N lines that was measured in our lab. The sl named files represent stripline, FR4 structures which are comparable in loss to a real structure with 6 mil edge coupled P and N lines. Customers wishing to achieve accurate simulation results for their PCB applications will need to develop their own models to reflect the specific line characteristics. lc1_wele_3in.cir This model represents the line card signal interconnection at the TX side. It provides a 3 inch long segments (P and N lines) of the W-element lossy line described above. The L parameter value defined at the end of the WP1 and WN1 lines may be changed to vary the pcb trace length. L is the length of each line, in meters. lc1_ms_5in.cir This model represents the line card signal interconnection at the TX side. It provides a 5 inch long segments (P and N lines) of the ms type, described above. The L parameter value defined at the end of the WP1 and WN1 lines may be changed to vary the pcb trace length. L is the length of each line, in meters. lc2_wele_3in.cir This model represents the line card signal interconnection at the RX side. It provides a 3 inch long segment of the W-element line described above. The L parameter value defined at the end of the WP1 and WN1 lines may be changed to vary the 3 inch length. L is the length of each line, in meters. Lc2_ms_5in.cir This model represents the line card signal interconnection at the RX side. It provides a 5 inch long segments (P and N lines) of the ms type, described above. The L parameter value defined at the end of the WP1 and WN1 lines may be changed to vary the pcb trace length. L is the length of each line, in meters. bp_wele_6in.cir This model represents the backplane pcb interconnection signal traces. It provides a 6 inch long segment of the W-element line pair as described above. The L parameter value defined at the end of the WP2 and WN2 lines may be changed to vary the pcb trace length. L is the length of each line, in meters. bp_wele_18in.cir This model represents the backplane pcb interconnection signal traces. It provides a 18 inch long segment of the W-element line pair as described above. bp_wele_3in.cir This model represents the backplane pcb interconnection signal traces. It provides a 3 inch long segment of the W-element line pair as described above. 8 2/6/26

9 bp_ms_3in.cir This model represents the backplane pcb interconnection signal traces. It provides a 3 inch long segment of the ms type line pair as described above. bp_sl_3in.cir This model represents the backplane pcb interconnection signal traces. It provides a 3 inch long segment of the sl type line pair as described above. bp_ms_6in.cir This model represents the backplane pcb interconnection signal traces. It provides a 6 inch long segment of the ms type line pair as described above. bp_null.cir This is the zero order model which essentially eliminates the element from the simulation signal path. It provides a zero delay, zero parasitic impedance connection between adjacent elements. Two different controlled impedance backplane connector models were provided by Teradyne and are included in the library. A brief description of each follows: conn1_gbx_ab.cir This model represents backplane connector at the TX side. It uses the Teradyne GBX 8-row connector, row a/b (shortest length) pin pair. This file calls the Teradyne pin model in file gbxab.cir. conn1_gbx_jk.cir This model represents backplane connector at the TX side. It uses the Teradyne GBX 8-row connector, row j/k (longest length) pin pair. This file calls the Teradyne pin model in file gbxjk.cir. conn1_null.cir This is the zero order model which essentially eliminates the element from the simulation signal path. It provides a zero delay, zero parasitic impedance connection between adjacent elements. conn2_gbx_ab.cir This model represents backplane connector at the RX side. It uses the Teradyne GBX 8-row connector, row a/b (shortest length) pin pair. This file calls the Teradyne pin model in file gbxab.cir. Note: if conn1_gbx_ab.cir is selected in the testbench file, the.include line in this file must be commented out (* added as the first character of the line), to avoid a compiling error. conn2_gbx_jk.cir This model represents backplane connector at the RX side. It uses the Teradyne GBX 8-row connector, row j/k (longest length) pin pair. This file calls the Teradyne pin model in file gbxjk.cir. Note: if conn1_gbx_jk.cir is selected in the testbench file, the.include line in this file must be commented out (* added as the first character of the line), to avoid a compiling error. 9 2/6/26

10 conn2_null.cir This is the zero order model which essentially eliminates the element from the simulation signal path. It provides a zero delay, zero parasitic impedance connection between adjacent elements. SIMULATION EYE-DIAGRAM DISPLAY A recursive time variable parameter (teye) is defined in the.print statement of the testbench file. When one of the 4 versions of this parameter (teye, teye1, teye2 or teye3) is selected as the x variable in an Awaves display panel, an eye-diagram waveform of any output variable may be created. To obtain a clean eye-diagram display, the following must also be done: 1. The TX buffer clock rate period (set in tx_xxx.cir) must equal the eye-diagram period (set in testbench.sp). 2. The eye-diagram display initialization time (set in testbench.sp) must be set to allow waveform stablization from circuit transient start up anomolies. This portion of the simulation waveform will appear to the left of the eye-diagram section of the display. 3. The 4 teye parameter versions allow 4 different horizontal positionings of the eye-diagram display. The one which best centers the eye is usually best. 4. The output variable in the display should be selected in Awaves; then right-click in the display and toggle the "continuous display" to the "monotonic plot" mode. This will eliminate the retrace lines in the eye-diagram display. 5. The X-zoom feature in Awaves may be used to show only the eye-diagram portion of the initial display. SIMULATION PARAMETER CONTROL The testbench.sp file and the library model files control the parameters of the transient simulation normally performed. The following list identifies the file locations for the controllable simulation parameters. 1. Simulation time interval and step size -- testbench.sp (.tran line) 2. Buffer supply voltages -- are set in the tx_* and rx_* model files. The voltage parameters are identified with comments in those files. 3. Choose a Series-4 FPSC buffer model type (ORSO or ORT) -- tx_4e.cir and rx_4e.cir (uncomment appropriate line). Note: OSPI4 SERDES product simulations should uncomment the.include line with ORT. 4. Extracted buffer model temperature -- testbench.sp (.temp XX line) 5. Extracted buffer process model selection -- testbench.sp (uncomment appropriate.include line(s) 6. Eye-Diagram waveform display time period -- testbench.sp (per parameter) 7. Eye-Diagram display initialization time -- testbench.sp (dly parameter) 8. Setting TX buffer clock (data) rate -- patx_xxx.dvf (set 'per' parameter in the data pattern file being used) 9. TX buffer output amplitude -- Uncomment appropriate line in tx_* model file being used. Available options are explained with comments in the files. 1. TX buffer pre-emphasis mode -- Uncomment appropriate line in tx_* model file being used. Available options are explained with comments in the files. 1 2/6/26

11 11. TX buffer internal termination impedance (Lattice SC products only) -- Uncomment appropriate line in tx_5.cir model file. Available options are explained with comments in the file. 12. RX buffer internal termination impedance (Lattice SC products only) -- Uncomment appropriate line in rx_5.cir model file. Available options are explained with comments in the file. 13. RX buffer internal coupling mode (Lattice SC products only) -- Uncomment appropriate line in rx_5.cir model file. Available options are explained with comments in the file. 14. RX buffer internal signal equalization (Lattice SC products only, extracted model only) -- Uncomment appropriate line in rx_sce.cir model file to enable or disable the default equalization settings. Equalization parameter programming is possible but not supported in this model package version. 15. TX line card PCB trace length -- lc1_xxx.cir (L in meters) 16. RX line card PCB trace length -- lc2_xxx.cir (L in meters) 17. Backplane PCB trace length -- bp_xxx.cir (L in meters) OTHER LIBRARY MODELS Several additional HSpice model files are provided in the libr directory, that are not supported in the testbench. These are more complex package and connector models that may be useful for application crosstalk simulations. The user must create a new testbench or modify the provided testbench to make use of these models. 68_trace_xt.cir 68PBGA extended package model - 16 conductor segment of package substrate. Provides 3 section model of 4 adjacent high speed SERDES input and output ports, including all significant crosstalk coupling elements. (Note this model is not compatible with provided testbench file.) 68_wire_xt.cir 68PBGA extended package model - 16 conductor section of package wire bonds. Provides 3 section model of 4 adjacent channels of high speed SERDES input and output differential ports, including all significant crosstalk coupling elements. (Note this model is not compatible with provided testbench file.) 484_all6_xt.cir 484PBGA extended package model - 6 conductor section of package substrate and wire bonds. Provides a 2 section model of 3 adjacent high speed i/o differential pin paths. It includes all significant crosstalk coupling elements between these paths. The package balls modeled are R21, R22, T21, T22, U21 and U22. (Note this model is not compatible with provided testbench file.) gbx_xt.cir Teradyne GBX connector model - 6 adjacent signal conductors with cross-coupling. Provided courtesy of Teradyne. (Note this model is not compatible with provided testbench file.) Six low-level models files, tx_4e_ors, tx_4e_ort, tx_sce_sl, rx_4e_ors, rx_4e_ort, and rx_sce_sl, are the detailed buffer circuit extraction files from the modeled product devices. These files are partially encrypted to protect Lattice proprietary design information. The low level files are called (included) by higher-level files tx_4e, tx_sce, rx_4e and rx_sce. *** 11 2/6/26

12 Two low-level model files, gbx_ab and gbx_jk, are present in the LIBR directory. These files are subroutines used by connector model files already described. There are 6 manufacturing process files, defining key device parameters for the extracted circuit models. These files are partially encrypted to protect Lattice proprietary design information. The file names are mod_nom.dat, mod_fast.dat, mod_slow.dat, cs1a_g, cs1a_ll_rev1.3, and cs1a_models. These files must be present in the libr/ directory when extracted buffer models are called by the testbench. 12 2/6/26

13 SIMULATION EXAMPLES The first 3 examples described in this section show a progression of test system complexity. The first model uses the simplest function buffer models and short transmission line interconnections. The second and third models progress to calling more complex, extracted buffers, device packages, line-card transmission line segments and backplane connectors. The.sp top-level files used for these simulations are included in the IO Kit, to provide a reference for users wishing to verify operation of their simulation environment or verify their understanding of the IO Kit testbench use. Additional examples are included to demonstrate the breadth of application conditions that may be simulated and to show some design cases that may be of specific interest to some customers. These examples will be limited to a description of the simulation configuration and conditions and resulting output waveforms. 13 2/6/26

14 EXAMPLE 1 Selected Model Elements in Simulation Pat Gen:pats_prbs7, 1. GBPS Conn 1: conn1_null Ln Crd 2: lc2_null TX Buf: tx_4f Bck Pln: bp_wele_6in Pkg 2: pkg2_null Pkg 1: pkg1_null Conn 2: conn2_null Rx Buf: rx_4f Ln Crd 1: lc1_null Comment: D:tr:v(p1) D:tr:v(n1) v2 example 1: prbs7, 1gbps, tx_4f, no pe, bp_wele_6in, rx_4f 1.6 Voltages (lin) D:tr:v(p8) D:tr:v(n8) Voltages (lin) n 4n 6n Time (lin) (TIME) D:tr:par(dif_rxin) 4m 2n 4n 6n Time (lin) (TIME) 2m -2m -4m -1n 1n (teye) 15:54:17 EDT, 1/8/ /6/26

15 Example1.sp top level file content ** Only one statement in each of the following groups **should be uncommented ** The following.include statements select the SUT ** element models ** TX buffer.include libr/tx_4f.cir *.include libr/tx_scf.cir *.include libr/tx_4e.cir *.include libr/tx_sce.cir ** Data pattern file **Uncomment one of these when tx_4f, tx_sce or tx_scf ** is selected above.vec libr/pats_prbs7.dvf *.vec libr/pats_cjpat.dvf *.vec libr/pats_prbs31.dvf * Uncomment one of these when tx_4e is selected above *.vec libr/pate_prbs7.dvf *.vec libr/pate_cjpat.dvf ** TX buffer IC package *.include libr/pkg1_68.cir *.include libr/pkg1_484.cir *.include libr/pkg1_sc9b.cir *.include libr/pkg1_sc9w.cir *.include libr/pkg1xt_sc9.cir *.include libr/pkg1_136.cir.include libr/pkg1_null.cir ** TX line card PCB trace *.include libr/lc1_wele_3in.cir *.include libr/lc1_ms_5in.cir.include libr/lc1_null.cir ** TX backplane connector *.include libr/conn1_gbx_ab.cir *.include libr/conn1_gbx_jk.cir.include libr/conn1_null.cir ** Backplane PCB trace.include libr/bp_wele_6in.cir *.include libr/bp_wele_18in.cir *.include libr/bp_wele_3in.cir *.include libr/bp_ms_3in.cir *.include libr/bp_ms_6in.cir *.include libr/bp_sl_3in.cir *.include libr/bp_sl_6in.cir *.include libr/bp_null.cir ** RX backplane connector *.include libr/conn2_gbx_ab.cir *.include libr/conn2_gbx_jk.cir.include libr/conn2_null.cir ** RX line card PCB trace *.include libr/lc2_wele_3in.cir *.include libr/lc2_ms_5in.cir.include libr/lc2_null.cir ** RX buffer IC package *.include libr/pkg2_68.cir *.include libr/pkg2_484.cir *.include libr/pkg2_sc9b.cir *.include libr/pkg2_sc9w.cir 15 *.include libr/pkg2xt_sc9.cir *.include libr/pkg2_136.cir.include libr/pkg2_null.cir ** RX buffer *.include libr/rx_ideal.cir.include libr/rx_4f.cir *.include libr/rx_scf.cir *.include libr/rx_4e.cir *.include libr/rx_sce.cir ***************** library model selections ************************** ** Include Series 4 process model library ** Can change this line to use one of SLOW, NOMINAL, FAST. *.include libr/mod_nom.dat *.include libr/mod_fast.dat *.include libr/mod_slow.dat ** Include SC process model library ** Can change this line to use one of SLOW, TYPICAL, FAST. *.lib./libr/cs1a_models TT *.lib./libr/cs1a_models FF *.lib./libr/cs1a_models SS **************** simulation analysis & control *****************.options method=gear.options probe post=2 ingold=2 brief.tran 1p 6ns *.op voltage.temp 7 ****************** display variables ***************************** *** Eye diagram display parameter settings below *** ** per=time period for eye diagram display retrace sweep. This ** parameter is also used in tx_sc.cir model file. ** dly=initial time period not included in eye diagram.param per=1ps.param dly=3.ns.print tran + v(ldata) + v(outp) v(outn) $ RX first stage output + V(p8) V(n8) $ RX input at chip + v(p7) v(n7) $ RX package input + v(p6) v(n6) $ RX line card PCB trace input + v(p5) v(n5) $ backplane PCB trace end (at RX end) + v(p4) v(n4) $ backplane PCB trace end (at TX end) + v(p3) v(n3) $ TX line card PCB trace output + v(p2) v(n2) $ TX package output + v(p1) v(n1) $ TX output at chip * RX input differential voltage + dif_rxin=par('v(p8)-v(n8)') * RX first stage output differential voltage + dif_rxout=par('v(outp)-v(outn)') * Eye Diagram display time variables + teye=par('time-int((time-dly)/per)*per-dly') + teye1=par('time-int((time-dly-per/4)/per)*per-dly-per/4') + teye2=par('time-int((time-dly-per/2)/per)*per-dly-per/2') + teye3=par('time-int((time-dly-per*3/4)/per)*per-dly-per*3/4') ****************************************************************** ** Transmission line initialization circuit Vswitch VSW PWL p 1v 2p 1v 4p v Gswtx p1 n1 VCR PWL(1) VSW (v,1meg) (1v,1m) Gswrx p8 n8 VCR PWL(1) VSW (v,1meg) (1v,1m) ******************************************************************.end 2/6/26

16 EXAMPLE 2 Selected Model Elements in Simulation Pat Gen: pats_cjpat (3.125 GBPS) Conn 1: conn1_null Ln Crd 2: ls2_ms_5in TX Buf: tx_scf ( 32% PE) Bck Pln: 3 lossy line Pkg 2: pkg2_136 Pkg 1: pkg1_sc9w Conn 2: conn2_null Rx Buf: rx_4f Ln Crd 1: ls1_ms_5in Comment: D:tr:v(p2) D:tr:v(n2) v2 exmpl2: cjpat,3.1gbps,tx_scf 32%pe,sc9w,lc_5,bp_3in,lc_5,pkg136,rx_4f 1.4 Voltages (lin) D:tr:v(p8) D:tr:v(n8) Voltages (lin) n 4n Time (lin) (TIME) 1.15 D:tr:par(dif_rxin) 2m 2n 4n Time (lin) (TIME) -2m -2p 2p (teye2) 16:3:33 EDT, 1/8/ /6/26

17 Example2.sp top level file content ** Only one statement in each of the following groups should be ** uncommented ** The following.include statements select the SUT element s ** TX buffer *.include libr/tx_4f.cir.include libr/tx_scf.cir *.include libr/tx_4e.cir *.include libr/tx_sce.cir ** Data pattern file * Uncomment one of these for tx_4f, tx_sce or tx_scf *.vec libr/pats_prbs7.dvf.vec libr/pats_cjpat.dvf *.vec libr/pats_prbs31.dvf * Uncomment one of these when tx_4e is selected above *.vec libr/pate_prbs7.dvf *.vec libr/pate_cjpat.dvf ** TX buffer IC package *.include libr/pkg1_68.cir *.include libr/pkg1_484.cir *.include libr/pkg1_sc9b.cir.include libr/pkg1_sc9w.cir *.include libr/pkg1xt_sc9.cir *.include libr/pkg1_136.cir *.include libr/pkg1_null.cir ** TX line card PCB trace *.include libr/lc1_wele_3in.cir.include libr/lc1_ms_5in.cir *.include libr/lc1_null.cir ** TX backplane connector *.include libr/conn1_gbx_ab.cir *.include libr/conn1_gbx_jk.cir.include libr/conn1_null.cir ** Backplane PCB trace *.include libr/bp_wele_6in.cir *.include libr/bp_wele_18in.cir.include libr/bp_wele_3in.cir *.include libr/bp_ms_3in.cir *.include libr/bp_ms_6in.cir *.include libr/bp_sl_3in.cir *.include libr/bp_sl_6in.cir *.include libr/bp_null.cir ** RX backplane connector *.include libr/conn2_gbx_ab.cir *.include libr/conn2_gbx_jk.cir.include libr/conn2_null.cir ** RX line card PCB trace *.include libr/lc2_wele_3in.cir.include libr/lc2_ms_5in.cir *.include libr/lc2_null.cir ** RX buffer IC package *.include libr/pkg2_68.cir *.include libr/pkg2_484.cir *.include libr/pkg2_sc9b.cir *.include libr/pkg2_sc9w.cir *.include libr/pkg2xt_sc9.cir.include libr/pkg2_136.cir *.include libr/pkg2_null.cir ** RX buffer *.include libr/rx_ideal.cir.include libr/rx_4f.cir *.include libr/rx_scf.cir *.include libr/rx_4e.cir *.include libr/rx_sce.cir ***************** library model selections ************************** ** Include Series 4 process model library ** Can change this line to use one of SLOW, NOMINAL, FAST. *.include libr/mod_nom.dat *.include libr/mod_fast.dat *.include libr/mod_slow.dat ** Include SC process model library ** Can change this line to use one of SLOW, TYPICAL, FAST. *.lib./libr/cs1a_models TT *.lib./libr/cs1a_models FF *.lib./libr/cs1a_models SS **************** simulation analysis & control *****************.options method=gear.options probe post=2 ingold=2 brief.tran 1p 5ns *.op voltage.temp 7 ****************** display variables ***************************** *** Eye diagram display parameter settings below *** ** per=time period for eye diagram display retrace sweep. This ** parameter is also used in tx_sc.cir model file. ** dly=initial time period not included in eye diagram.param per=32ps.param dly=8.ns.print tran + v(ldata) + v(outp) v(outn) $ RX first stage output + V(p8) V(n8) $ RX input at chip + v(p7) v(n7) $ RX package input + v(p6) v(n6) $ RX line card PCB trace input + v(p5) v(n5) $ backpln PCB trace end (at RX end) + v(p4) v(n4) $ backpln PCB trace end (at TX end) + v(p3) v(n3) $ TX line card PCB trace output + v(p2) v(n2) $ TX package output + v(p1) v(n1) $ TX output at chip * RX input differential voltage + dif_rxin=par('v(p8)-v(n8)') * RX first stage output differential voltage + dif_rxout=par('v(outp)-v(outn)') * Eye Diagram display time variables + teye=par('time-int((time-dly)/per)*per-dly') + teye1=par('time-int((time-dly-per/4)/per)*per-dly-per/4') + teye2=par('time-int((time-dly-per/2)/per)*per-dly-per/2') + teye3=par('time-int((time-dly-per*3/4)/per)*per-dly-per*3/4') ****************************************************************** ** Transmission line initialization circuit Vswitch VSW PWL p 1v 2p 1v 4p v Gswtx p1 n1 VCR PWL(1) VSW (v,1meg) (1v,1m) Gswrx p8 n8 VCR PWL(1) VSW (v,1meg) (1v,1m) * ******************************************************************.end 17 2/6/26

18 EXAMPLE 3 Selected Model Elements in Simulation Pat Gen: pate_prbs7 (2.5 GBPS) Conn 1: conn1_gbx_ab Ln Crd 2: lc2_wele_3in TX Buf: tx_4e_orsc Bck Pln: bp_wele_18in Pkg 2: pkg2_sc9b Pkg 1: pkg1_484 Conn 2: Teradyne GBX Rx Buf: rx_sce, med path EQ Ln Crd 1: lc1_wele_3i Comment: D:tr:v(p2) D:tr:v(n2) v2 exmpl3: prbs7,2.5g,tx_4e ors 12pe,484,3in,gbx_ab,18in,gbx_jk,3in,9b,rx_SCe Voltages (lin) D:tr:v(p8) D:tr:v(n8) Voltages (lin) n 2n 3n Time (lin) (TIME) D:tr:par(dif_rxin) 1 4m 2m -2m -4m 1n 2n 3n Time (lin) (TIME) D:tr:par(dif_rxout) 4m 2m -2m -4m -4p -2p 2p 4p (teye3) -4p -2p 2p 4p (teye3) 17:39:23 EDT, 1/8/ /6/26

19 Example3.sp top level file content ** The following.include statements select the SUT element models ** TX buffer *.include libr/tx_4f.cir *.include libr/tx_scf.cir.include libr/tx_4e.cir *.include libr/tx_sce.cir ** Data pattern file * Uncomment one of these when tx_4f, tx_sce or tx_scf is selected above *.vec libr/pats_prbs7.dvf *.vec libr/pats_cjpat.dvf *.vec libr/pats_prbs31.dvf * Uncomment one of these when tx_4e is selected above.vec libr/pate_prbs7.dvf *.vec libr/pate_cjpat.dvf ** TX buffer IC package *.include libr/pkg1_68.cir.include libr/pkg1_484.cir *.include libr/pkg1_sc9b.cir *.include libr/pkg1_sc9w.cir *.include libr/pkg1xt_sc9.cir *.include libr/pkg1_136.cir *.include libr/pkg1_null.cir ** TX line card PCB trace.include libr/lc1_wele_3in.cir *.include libr/lc1_ms_5in.cir *.include libr/lc1_null.cir ** TX backplane connector.include libr/conn1_gbx_ab.cir *.include libr/conn1_gbx_jk.cir *.include libr/conn1_null.cir ** Backplane PCB trace *.include libr/bp_wele_6in.cir.include libr/bp_wele_18in.cir *.include libr/bp_wele_3in.cir *.include libr/bp_ms_3in.cir *.include libr/bp_ms_6in.cir *.include libr/bp_sl_3in.cir *.include libr/bp_sl_6in.cir *.include libr/bp_null.cir ** RX backplane connector *.include libr/conn2_gbx_ab.cir.include libr/conn2_gbx_jk.cir *.include libr/conn2_null.cir ** RX line card PCB trace.include libr/lc2_wele_3in.cir *.include libr/lc2_ms_5in.cir *.include libr/lc2_null.cir ** RX buffer IC package *.include libr/pkg2_68.cir *.include libr/pkg2_484.cir.include libr/pkg2_sc9b.cir *.include libr/pkg2_sc9w.cir *.include libr/pkg2xt_sc9.cir *.include libr/pkg2_136.cir *.include libr/pkg2_null.cir ** RX buffer *.include libr/rx_ideal.cir *.include libr/rx_4f.cir *.include libr/rx_scf.cir *.include libr/rx_4e.cir.include libr/rx_sce.cir ***************** library model selections ************************** ** Include Series 4 process model library ** Can change this line to use one of SLOW, NOMINAL, FAST..include libr/mod_nom.dat *.include libr/mod_fast.dat *.include libr/mod_slow.dat ** Include SC process model library ** Can change this line to use one of SLOW, TYPICAL, FAST..lib./libr/cs1a_models TT *.lib./libr/cs1a_models FF *.lib./libr/cs1a_models SS **************** simulation analysis & control *****************.options method=gear.options probe post=2 ingold=2 brief.tran 1p 3ns *.op voltage.temp 7 ****************** display variables ***************************** *** Eye diagram display parameter settings below *** ** per=time period for eye diagram display retrace sweep. This ** parameter is also used in tx_sc.cir model file. ** dly=initial time period not included in eye diagram.param per=4ps.param dly=6.ns.print tran + v(ldata) + v(outp) v(outn) $ RX first stage output + V(p8) V(n8) $ RX input at chip + v(p7) v(n7) $ RX package input + v(p6) v(n6) $ RX line card PCB trace input + v(p5) v(n5) $ bckpln PCB trace end (at RX end) + v(p4) v(n4) $ bckpln PCB trace end (at TX end) + v(p3) v(n3) $ TX line card PCB trace output + v(p2) v(n2) $ TX package output + v(p1) v(n1) $ TX output at chip * RX input differential voltage + dif_rxin=par('v(p8)-v(n8)') * RX first stage output differential voltage + dif_rxout=par('v(outp)-v(outn)') * Eye Diagram display time variables + teye=par('time-int((time-dly)/per)*per-dly') + teye1=par('time-int((time-dly-per/4)/per)*per-dly-per/4') + teye2=par('time-int((time-dly-per/2)/per)*per-dly-per/2') + teye3=par('time-int((time-dly-per*3/4)/per)*per-dly-per*3/4') ******************************************************************* ***Transmission line initialization circuit Vswitch VSW PWL p 1v 2p 1v 4p v Gswtx p1 n1 VCR PWL(1) VSW (v,1meg) (1v,1m) Gswrx p8 n8 VCR PWL(1) VSW (v,1meg) (1v,1m) * ******************************************************************.end 19 2/6/26

20 EXAMPLE 4 PCI Express Terminations The following PCI Express PCB termination circuit is simulated in the first part (Case A and Case B) of this example. Configuration 1 TX device 5 ohm trms 1152w pkg Default ampl. pre-emph. C1p=.1uF VDDOB=1.5V C1n=.1uF 5 L1=6 5 L1=6 GBX -ab R1p=5 GBX -ab C2p=.1uF R1n=5 C2n=.1uF 5 L2=.5 VDDIB.1uF 5 L2=.5 RX device 2K ohm trms Int. dc cpl. 1152w pkg + - SC device Outside SC device SC device The objective of this topology is full PCI Express Specification (Ver 1.1) compliance, with 5 ohm to ground dc termination. It includes PCB resistor terminations and dual capacitor coupling for both the P and N path connections. This is necessary because normal CML buffer terminations connect to VDD (1.2V or 1.5V dc) rather than ground. The CML Rx device input termination is put in the high impedance state. Transmission Lines L2 represent the PCB trace connection length between PCB capacitors C2p/C2n and the RX device input package balls. A nominal value for L2 of.5 inches was assumed. This length should be kept as short as possible. To address concern about the effects of parasitic impedances associated with the PCB chip capacitors ESR, ESL and pad capacitance to ground elements are included. Selected Model Elements in Simulation Pat Gen: pats_prbs7 (2.5 GBPS) Conn 1: conn1_null Ln Crd 2: wele, length varied by case TX Buf: SC extr., 5 ohm trm Bck Pln: bp_wele_6in Pkg 2: pkg2_1152w Pkg 1: pkg1_1152w Conn 2: conn2_null Rx Buf: rx_sce (2K trm, no EQ) Ln Crd 1: lc1_null Comment: 4-AVX type X7R ceramic capacitors (with parasitics) 2 2/6/26

21 Case A (Configuration 1, L2=.5 inch) Differential Rx input voltage eye-diagram at receive buffer chip input v(dif_rxin). Differential Rx output voltage eye-diagram at receive buffer chip output (dif_rxout): D:tr:v(p8) D:tr:v(n8) ex4a: 1152w pkgs,6in,avx126 xr7 cap,5 trm,cap,.5in,rx_sce 2k 1.4 Voltages (lin) m 6m 2n 4n Time (lin) (TIME) D:tr:par(dif_rxin) 5m -5m DeltaX=1.54e-1 DeltaY=3.68e-1 2p (teye1) 4p D:tr:par(dif_rxout) 4m 2m -2m DeltaX=1.69e-1-4m 2p (teye2) 4p 11:26:41 EST, 12/16/ /6/26

22 CaseB (Configuration 1, L2= inch) Same as Case A except trace lengths between 5 board terminations and package input balls reduced to inches. D:tr:v(p8) D:tr:v(n8) Voltages (lin) ex8a: 1152w pckgs,6in,avx126 xr7 cap,5 trm,cap,in,rx_sce 2k m D:tr:par(dif_rxin) 5m 2n 4n Time (lin) (TIME) DeltaX=9.1e-11 D:tr:par(dif_rxout) -5m 4m 2p (teye1) DeltaY=6.56e- 4p 2m -2m DeltaX=9.19e-11-4m 2p (teye2) 4p 15:5:49 EST, 12/16/ /6/26

23 An alternate configuration is shown below that offers some improvement in eye-diagram performance over configuration 1. Configuration 2 TX device 5 ohm trms 1152w pkg Default ampl. pre-emph. C1p=.1uF VDDOB=1.5V C1n=.1uF 5 L1=6 5 L1=6 GBX -ab R1p=5K GBX -ab C2p=.1uF R1n=5K C2n=.1uF 5 L2=.5 VDDIB.1uF 5 L2=.5 RX device 5 ohm trms Int. dc cpl. 1152w pkg + - SC device Outside SC device SC device The main difference in this configuration (over that of Configuration 1) is shifting from a board 5 ohm termination scheme to that of a chip internal 5 ohm termination. 23 2/6/26

24 CaseC (Configuration 2) Differential Rx input voltage eye-diagram at receive buffer chip input v(dif_rxin). Differential Rx output voltage eye-diagram at receive buffer chip output (dif_rxout): D:tr:v(p8) D:tr:v(n8) Voltages (lin) Extr RX mod w par C & 5 ohm int trm D:tr:par(dif_rxin) 8m 4m 2n 4n Time (lin) (TIME) 2m -2m DeltaX=7.53e-11-4m DeltaY=7.8e-1 D:tr:par(dif_rxout) 4m 2p (teye1) 4p 2m -2m DeltaX=9.14e-11-4m 2p (teye2) 4p 15:38:59 EST, 12/8/ /6/26

25 Discussion Cases A and B show that for Configuration 1 it is very important to place the PCB 5 termination resistors as close to the FPGA SERDES input pins as possible. One-half inch of trace length between the resistors and the input pins (Case B) can cause significant degradation of the eye-opening. This is because the PCB trace L2 (and the package) present an unterminated transmission line stub in parallel with the 5 ohm PCB line termination. The greater this stub length the larger the transmission line reflection and resulting eye closure. Case C, which simulates Configuration 2, effectively eliminates the stub line reflection described above by moving the stub to the left of the path 5 ohm terminations. The stub segments become integral parts of the 5 ohm transmission line connection paths. 25 2/6/26

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