Module Introduction. Purpose This training module covers 68K/ColdFire Specific Peripherals

Transcription

1 Introduction Purpose This training module covers 68K/ColdFire Specific Peripherals Objectives Explain the features of the Physical Layer Interface Controller (PLIC) module, including the configuration of the TDM ports. Describe the features and functions of the IDE Interface. Explain the features and internal structure of the Audio interface. Understand the CD ROM Block Decoder/Encoder module Explain how the Liquid Crystal Display (LCD) controller supports management of a second display area. Content 19 pages 4 questions Learning Time 30 minutes This module introduces you to various Application Specific Peripherals found on our ColdFire devices. We will discuss the features of the Physical Layer Interface Controller (PLIC), the IDE Interface, the Audio interface, the CD-ROM Block Decoder/Encoder module, and the Liquid Crystal Display (LCD) controller. 1

2 PLIC 1K I-Cache 4K SRAM 10/100 Ethernet Controller DMA USB UARTs JTAG V2 I Addr Gen I Fetch Instr Buf Dec&Sel Op A Gen & Ex MAC H/W Divide Debug Software HDLC System Bus Controller Interrupt Ctr Chip Selects SDRAM Ctr General Purpose I/O 3 PWMs DMA 4 Timers QSPI 4 TDMs Primarily intended to facilitate the interface with ISDN transceivers or codecs Connects at the physical layer with devices featuring: Interchip Digital Link (IDL) General Circuit Interface (GCI) 4 TDM ports FEATURES Supports IDL mode of operation Supports GCI mode of operation This module is primarily intended to facilitate designs that include Integrated Services Digital Network (ISDN) interfaces. Let s explore its features. The Physical Layer Interface Controller (PLIC) allows the MCF5272 to connect at a physical level with external Coder/Decoders (CODECs) and other peripheral devices that use either the General Circuit Interface (GCI) or Interchip Digital Link (IDL) physical layer protocols. The MCF5272 has four dedicated physical layer interface ports for connecting to external ISDN transceivers, CODECs, and other peripherals. There are three sets of pins for these interfaces. Port 0 has its own dedicated set of pins. Ports 1, 2, and 3 share a set of pins. Port 3 can also be configured to use a dedicated pin set. Ports 1, 2, and 3 always share the same Data Clock (DCL). When the ports are operated in slave mode, the PLIC can support a DCL frequency of MHz and Frame Sync Frequency (FSC/FSR) of 8 KHz. When in master mode, DCL should be no greater than one-twentieth of the CPU clock (CLKIN), with a maximum FSC/FSR of 8 KHz. The Interchip Digital Link (IDL) mode of operation is a four-wire interface used for full-duplex communication between ICs at the board level. This interface consists of a transmit path, a receive path, an associated clock, and a synchronization signal. These signals are known as Dout, Din, DCL, and FSC. The clock determines the rate of exchange of data in both transmit and receive directions and the sync controls when this exchange occurs. Three channels of data are exchanged every 125 microseconds. These channels consist of two 64-kbps B channels and one 16-kbps D channel used for full-duplex communication. The General Circuit Interface (GCI) mode was defined by European companies (Italtel, Siemens, Alcatel, and GPT). GCI is a time division multiplex (TDM) bus that combines the ISDN 2B+D data, control, and status information onto four signal pins. The GCI frame structure has the following format: two B channels, a monitor channel, the ISDN D channel, the command/indicate channel, and the A and E bits. 2 13

3 PLIC Now that you ve learned the general features of the PLIC, we ll look at it in more detail. This diagram depicts the PLIC from the perspective of connecting it to an ISDN transceiver with 8-KHz frame sync. The MCF5272 PLIC has four ports: Port 0 through Port 3. A port can service, read, or write any 2B + D-channel. These ports are connected through three pin sets, numbered 0, 1, and 3. Pin set 3 consists of data in and data out. Data clock and frame sync are common to pin set 1 and 3. In the case of set 1, which connects multiple ports, separate delayed frame sync generators are provided for each port which distinguish each port s active time slots. The four ports have a number of different timing and connectivity features. Port 0 connects through pin set 0. It operates as a slave-only port; that is, an external device must source Frame Sync Clock/Frame Sync Receive (FSC/FSR) and Data Clock (DCL). These pins are unidirectional inputs. DIN0 and DOUT0 are dedicated pins for Port 0. Port 1 connects through pin set 1. It operates as a master or slave port. In slave mode an external device must source FSC/FSR and DCL. In master mode, DCL1 and FSC1/FSR1 are outputs. These signals are, in turn, derived from the DCL0 and FSC/FSR from Port 0. For Port 1 to function in master mode, Port 0 must be enabled with an external transceiver sourcing DCL and FSC/FSR. The physical interface pins DIN1 and DOUT1 serve Ports 1, 2, and 3. Port 2 connects through pin set 1. It operates as a slave-only port and shares a data clock with Port 1. It shares DCL1 when Port 1 is in slave mode or GDCL when Port 1 is in master mode. A delayed frame sync, DFSC2, derived from FSC1, is connected to the DFSC2 output and fed to the Port 2 IDL/GCI block. Users can synchronize the Port 2 IDL/GCI block with an offset frame sync, (offset with respect to the Port 1 GCI/IDL block), by programming the Port 2 Sync Delay Register (P2SDR). Port 3 connects through pin set 1 or 3. It operates as a slave-only Port and shares a data clock with Port 1. It shares DCL1 when Port 1 is in slave mode, or GDCL, when Port 1 is in master mode. A delayed frame sync, DFSC3, is derived from FSC1 and is fed to the Port 3 IDL/GCI block. Programming the Port 3 sync delay register, P3SDR, allows it to be synchronized with an offset frame sync (offset with respect to the Port 1 GCI/IDL block). Port 3 can also have dedicated data in and data out pins, DIN3 and DOUT3 of pin set 3. This allows the MCF5272 device to connect to ISDN NT1s that have a common frame sync and clock, but two sets of serial data-in and data-out pins. The MCF5272 PLIC provides two sets of D-channel arbitration control pins: DREQ0 and DGNT0 for pin set 0, and DREQ1 and DGNT1 for pin set 1. Finally, because pin set 1 connects Ports 1, 2, and 3, these ports do not have D-channel arbitration control signals. 3

4 TDM Ports Configuration 1K I-Cache 4K SRAM 10/100 Ethernet Controller DMA USB 1.1 JTAG V2 I Addr Gen I Fetch Instr Buf Dec&Sel Op A Gen & Ex MAC H/W Divide Debug System Bus Controller Interrupt Ctr Chip Selects SDRAM Ctr General Purpose I/O 3 PWMs DMA 4 Timers QSPI Port 0 One Set of Pins used for Standard IDL / GCI Port with Pins for D Channel Passive Bus Arbitration Ports 1, 2 & 3 Pins to allow Port 1 Support for D Channel Passive Bus Arbitration Ports 2 & 3 Share Common Frame Sync & Clock with Port 1 Delayed Frame Sync Generation for Ports 1, 2 & 3 Ports 1, 2, & 3 can be used for Codecs or additional transceivers Port 3 can be used as dedicated port Shares common clock with Port 1 Delayed frame sync DFSC3 used to align frame. Multiplexed with other pin functions 2 UARTs Software HDLC 4 TDMs Here is some configuration information for the 4 TDM Ports. Port 0 has one set of pins used for standard IDL/GCI port with pins for D-channel Passive Bus Arbitration. Ports 1, 2 & 3 have pins to allow Port 1 to support D Channel Passive Bus Arbitration. Ports 2 & 3 share common Frame Sync & Clock with Port 1. Ports 1, 2 & 3 also have delayed Frame Sync Generation and can be used for Codecs or additional transceivers. Port 3 can be used as a dedicated port that shares common clock with Port 1. It also has delayed frame sync DFSC3 used to align the frame and is multiplexed with other pin functions. 4 39

5 Question Which of the following are features of the Physical Layer Interface Controller (PLIC) module? Select all that apply and then click Done. A. It allows the MCF5272 to connect at a physical level with external Coder/Decoders. B. It supports the latest TFT (Thin Film Transistor) active matrix panels. C. It is primarily intended to facilitate designs that include Integrated Services Digital Network (ISDN) interfaces D. It has four ports: Port 0 through Port 3. Done Take a moment now to answer this question about the Physical Layer Interface Controller module. Select all that apply and then click Done. Correct! A, C, and D are features of the PLIC. It allows the MCF5272 to connect at a physical level with external Coder/Decoders, it is primarily intended to facilitate designs that include Integrated Services Digital Network (ISDN) interfaces, and it has four ports: Port 0 through Port 3. 5

6 HDLC Software 1K I-Cache 4K SRAM 10/100 Ethernet Controller DMA USB UARTs JTAG V2 I Addr Gen I Fetch Instr Buf Dec&Sel Op A Gen & Ex MAC H/W Divide Debug Software HDLC System Bus Controller Interrupt Ctr Chip Selects SDRAM Ctr General Purpose I/O 3 PWMs DMA 4 Timers QSPI 4 TDMs FEATURES HDLC software module: Supports LAPB, LAPD, X.25, etc Supports multiple channels simultaneously Contains: Table lookup based framer/deframer Operation at 56 ot 64 Kbps CRC generation/verification, bit stuffing/unstuffing Shared or separate opening/closing flags Aborted and erroneous frame counter Provided as linkable object module with documented API ColdFire HLDC Software is available at Another module in ColdFire is the High Level Data Link Control (HDLC) software module. The HDLC is a bit-oriented open systems interconnection (OSI) Layer 2 protocol commonly used in data communications systems. Many other common layer 2 protocols, such as, ISDN LAP-B, ISDN LAP-D, and Ethernet, are heavily based on HDLC. Since the soft HDLC module is just an instantiation of software, it can support multiple channels simultaneously. Freescale has developed a software HDLC framer/deframer function, which is designed to run on an MCF5272 processor. The peripheral independent main software block is capable of running on any ColdFire Version 2 based processor. However, the software object module, as delivered, assumes the presence of a number of lookup tables in ROM, currently only present on the MCF5272 device. The ColdFire HDLC receive (Rx) features include: it operates at 56 or 64 Kbps, it enables or disables CRC checking, it reports the number of CRC errors and aborts to calling function, it has address recognition of up to three independent addresses per channel - two regular independent addresses, one independent address associated with a mask, and the broadcast address. It also recognizes 0-, 8-, or 16-bit addresses. Finally, it restarts reception on any frame boundary. The MCF5272 ColdFire HDLC software module is available on the external Freescale website for free via a click software license agreement. The software is delivered to the licensee in object format library (libhdlc.a) ready to be linked together with the customer s own software. It consists of two main functions: HDLC_Tx_Driver and HDLC_Rx_Driver. 6 14

7 IDE interface Audio 8K Byte i-cache ColdFire V2 I Addr Gen B u s FEATURES PLL Frequency Synthesizer QSPI 12-bit ADC IDE interface Flash Media interface 96K Byte SRAM DUART Timers GPIOs I²Cs I Fetch Instr Buf Dec & Sel Op A Gen & Ex EMAC H/W Divide Debug C o n t r o l SDRAM Cntr & Chip Selects DMAs IDE and FlashMedia interface MCF5249 CS2, CS3, and RWb are used for IDE Interface Buffer enable outputs supplied by MCF5249 Next, let s look at the IDE interface and gather some details about its features and functions. The MCF5249 device system bus allows connection of an IDE hard disk drive and SmartMedia flash card with minimal external hardware. The IDE interface is useful in industrial and audio applications to interface with devices in order to store or retrieve large amounts of data in non-volatile memory such as a hard disk drive or CD-ROM. The MCF5249 uses chip select 2, chip select 3, and RWb to generate control signals DIOR and DIOW for f the IDE interface. The loading associated with the IDE bus means that buffers are required to reduce the loading on the MCF5249 bus. The MCF5249 also has two buffer enable outputs that help to eliminate the need for external logic to control address and data bus buffers. The enables are programmable to allow buffers to be connected singly or cascaded. 7

8 IDE interface Example MCF5249 A1 A2 A3 A4 A5 BUFENB2 D[31:16] BUFENB2 R/W GPO IDEIORDY IDEIOR IDEIOW GPIO Buffer /OE DIR Buffer /OE DIR IDE 40-pin header IDE_A0 IDE_A1 IDE_A2 IDE_CS0 IDE_CS1 IDE_D[15:0] IDE_RESET IDE_IOCHRDY IDE_IOR IDE_IOW IDE_IRQ Let s take a look at an IDE interface example. Notice that there is one set of buffers in the graphic set-up. The SDRAM or flash ROM is connected directly to the ColdFire bus. The IDE interface shares most signals with the ColdFire address and data bus. To prevent the flash ROM or SDRAM signals from going to or from the IDE interface, the address and data lines are buffered to the IDE interface. The BUFENB2 signal is active-low external buffer enable. This enable is always inactive when CS0 is active, and it should enable a buffer for peripheral devices, except boot ROM. 8

9 IDE Setup Steps Step Notes 1. Program the Chip Select 2 registers. You need to program CSAR2, CSMR2, and CSCR2. Use the following settings for CSCR2: AA = 0 (/TA generated by IDEconfig2 register) PS = 10 (16-bit port size) BSTR, BSTW = 00 (disable bursting for read and write cycles)] 2. Program the IDEconfig1 register. This step controls IDE bus timings and buffer enables. 3. Program the IDEconfig2 register. Use the following settings for IDEconfig2: TAenable2 = 1 (this allows the IDE control block to generate /TA for CS2 cycles) IORDYenable2 = 1 (only if IORDY signal is used)] Once the hardware interface is set up, there is a simple software sequence to configure the bus for the IDE interface. Program the Chip Select 2 registers inside the chip select module. (CSAR2, CSMR2, CSCR2). CSAR2, CSMR2 must be programmed to see the IDE interface in the correct part of the ColdFire address map. Next, write the IDEconfig1 register for bus timings and buffer enables. Program IDECONFIG2 register. Program this register with TA enable 2 = 1,IORDY enable 2 = 1 if IORDY is connected from the IDE drive to the MCF5249 chip and IORDY enable 2 = 0 if IORDY wait handshake is not used. 9

10 Question True or false? The IDE interface is useful in industrial and audio applications to interface with devices in order to store or retrieve large amounts of data in non-volatile memory. Click the correct answer and then click Done. A) True A) False Done Please answer this question about the IDE interface. Correct! The IDE interface is useful in industrial and audio applications to interface with devices in order to store or retrieve large amounts of data in non-volatile memory. 10

11 Audio Audio 8K Byte i-cache ColdFire V2 I Addr Gen B u s FEATURES PLL Frequency Synthesizer QSPI 12-bit ADC IDE interface Flash Media interface 96K Byte SRAM DUART Timers GPIOs I²Cs I Fetch Instr Buf Dec & Sel Op A Gen & Ex EMAC H/W Divide Debug C o n t r o l SDRAM Cntr & Chip Selects DMAs Four serial audio interfaces supporting IIS and EIAJ formats Two IEC958 digital audio receivers with 4 muxed inputs One IEC958 transmitter with two outputs Here we have the Audio interface, which is available on the MCF5249. This module allows the MCF5249 to receive and transmit digital audio over serial audio interfaces (IIS/EIAJ) and digital audio interfaces (IEC958). It contains four serial audio interfaces that support IIS and EIAJ formats. It also contains two IEC958 digital audio receivers with four multiplexed inputs. Finally, the last component of the Audio is one IEC958 transmitter with two outputs. 11

12 Audio interface IEC958 (SPDIF) Digital Audio Interfaces 2-Serial Digital Audio Receivers 1-Serial Digital Audio Transmitter with 2 output pin Audio interface Digital Audio interfaces Serial Audio interfaces Philips I2S / Sony EIAJ Serial Audio Interfaces 1-Four pin interface-transmit /Receive interface 3- Three pin interfaces, 2 are dedicated to Receive and 1 is dedicated to Transmit 40-bit wide Audio Data Bus Block Encoder/Decoder is also included to read/write CD-ROM format CD ROM Block Encoder / Decoder PDOR and PDIR Processor interfaces Audio data routes from any input to any output or through the CPU via the PDOR and PDIR processor interfaces. Frequency control module for clock synchronization with incoming sample frequency. Frequency Control Audio Tick Interrupt Generator The Audio interface allows you to receive and transmit digital audio over serial audio and digital audio interfaces. The Audio Tick Interrupt is used to aid a busy system by allowing an interrupt to occur after a number of (programmable) sample pairs to help avoid underrun issues on the transmit or receive FIFOs. The Audio interface has two IEC958 digital audio input interfaces and one IEC958 digital audio output interface. There are four digital audio input pins and two digital audio output pins. An internal multiplexer selects one of the four inputs to the digital audio input interface. There is one digital audio output interface but it has two IEC958 outputs. One output carries the professional c channel and the other caries the consumer c channel. The remaining outputs carry identical data. The module has four serial Philips I2S/Sony EIAJ audio interfaces. One interface is a 4-pin (one bit clock, one word clock, one data in, one data out). The other three interfaces are 3-pin (one bit clock, one word clock, one data in or out). Serial data transmit / receive interfaces have no limit on minimum incoming or outgoing sampling frequency. The maximum SCLK frequency is limited to 1/3 of the internal system clock (CPUclk/2). The Audio interface also includes a 40-bit wide Audio Data bus CD ROM Block Encoder/Decoder to read and write CD-ROM format. The module contains a frequency control module for clock synchronization with incoming sample frequency. The PDOR and PDIR processor interfaces allow audio data routes from any input to any output or through the CPU. 12

13 Audio interfaces Digital Audio Receivers 1&2 Serial Audio Receivers 1, 3 & 4 CPU Bus PDOR1 PDOR2 PDOR3 Block Encoder Audio Bus bit Time Multiplexed Bus Source Select Source Select Source Select Source Select Source Select FIFO 6 Fields FIFOs 6 fields each FIFO 6 Fields FIFO 6 Fields Block Decoder FIFO 6 Fields Digital Audio Transmitter Serial Audio Transmitters 1 & 2 PDIR1 PDIR2 CPU Bus PDIR3 Let s take a closer look at the Audio interface s internal structure. The Audio s FIFOs (PDIR 1,2 and 3 and PDOR 1,2 and 3) interface directly to the internal ColdFire bus. Audio data sent to and from the FIFOs are routed to and from the specific audio interface through the 40-bit Audio bus controlled by the Audio interface s configuration registers. Once the audio path is set up and configured, the user simply reads and writes the PDIR and PDOR registers respectively to receive and transmit audio data to and from the audio interfaces. 13

14 Question True or false? The Audio s FIFOs (PDIR 1,2 and 3 and PDOR 1,2 and 3) interface directly to the Audio Bus. Click the correct answer and then click Done. A) True B) False Done Please answer this question about the Audio. Correct! The Audio s FIFOs (PDIR 1,2 and 3 and PDOR 1,2 and 3) interface directly to the internal ColdFire bus. 14

15 CD-ROM Block Decoder/Encoder CPU Bus PDOR1 PDOR2 PDOR3 One 32-bit block control register is associated with the interface Source Select FIFO 6 Fields PDIR1 Audio Bus Source Select FIFO 6 Fields Block Decoder PDIR2 Block Encoder Source Select FIFO 6 Fields PDIR3 PDOR3 is equipped with a CD ROM block encoder block by block basis Nominal block length of 2352 bytes PDIR2 is equipped with a CD ROM block decoder Due to the addition of the decoder, PDIR2 is equipped with additional interrupts CPU Bus Let s move on to the CD ROM Block Decoder/Encoder. This is used to interface to a CD ROM. This interface allows the MCF52429 to decode/encode CD ROM formats through the audio interface module. One 32-bit block control register is associated with the interface. PDOR3 is equipped with a CD ROM block encoder. This functions on a block by block basis, in which each block is generally 2352 bytes long. PDIR2 is equipped with a CD ROM block decoder. Due to the addition of the decoder, PDIR2 is equipped with additional interrupts. 15

16 LCD Controller Support for single (non-split) screen monochrome or color LCD panels and self-refresh type LCD panels: Passive-matrix color (passive color or CSTN) Active matrix color (active color or TFT) Grey-scale Black and white Maximum resolution of 800 x 600 Panel Type Monochrome CSTN TFT Bit/Pixel ,8 12 4,8 12, 16, 18 Panel Interface (bits) 1,2,4,8 1,2,4,8 1,2,4, , 16, 18 Number of Gray Level/Color Black and white 4 out of palette of , 256 out of palette of , 256 out of palette of 256K 4096, 64K, 256K The LCD controller provides support for panels with resolutions up to SVGA which is (800x600) pixels with a maximum of 262K different colors in an 18 bits per pixel format. Not only are standard panels supported, but extra interface signals are provided for special SHARP panels. It supports the latest TFT (Thin Film Transistor) active matrix panels, as well as older passive matrix color (CSTN), grey scale, and B/W (monochrome) panels. The value of each color pixel on the screen is represented by a 4-, 8-, 12-, 16- or 18-bit code from the image stored in memory. And the 4- and 8- bit per pixel modes utilize mapping RAMs for both the background plane and the graphics window. For 4-bit and 8-bit passive matrix color displays, the 12-bit RGB code from the mapping RAM is output to the FRC blocks that independently process the code corresponding to the red, green, and blue components of each pixel to generate the required shade and intensity. For 4-bit and 8-bit active matrix display, the 18-bit output from the mapping RAM is output to the panel. For 12-bit mode for passive matrix color display, the mapping RAM is by-passed and output directly to the FRC block. Now let s examine the table. A 4bpp image on a TFT panel will have 16 available color entries out of a palette of 256K possible colors. An 8bpp image on a TFT panel will have 256 available color entries out of a palette of 256K possible colors. A 12, 16, or 18 bpp image on a TFT panel will output the image color data from memory to the panel with the maximum available colors of the image being 4096 colors for a 12bpp image, 64K colors for a 16 bpp image, and 256K colors for an 18bpp image. For CSTN the palette of available colors is A 4bpp image on a CSTN panel will have 16 available entries out of a palette of 4096 possible colors. An 8bpp image on a CSTN panel will have 256 available entries out of a palette of 4096 possible colors. A 12bpp image on a CSTN panel will output image data from memory to the panel with the maximum available colors for the image being 4096 colors. In monochrome mode images of 2bpp have 4 gray scale entries in the look-up table out of a palette of

17 LCD Controller Supports various industry standard LCD Displays Supports timing requirements for Sharp 240x320 HR-TFT Panel Support for single (non-split) screen monochrome or color LCD panels and self-refresh type LCD panels Logical operation between color hardware cursor and background plane Hardware panning enabled Graphic Window support for view finder function in color display 256 transparency levels for alpha blending between graphic window and background plane. LCD Controller Block Diagram Background Plane Gray Scale Interface & Buffer LCD Arbiter Alpha Blending Interface Logic LCD Panel Graphic Window Color Interface & Buffer The (LCD) Liquid Crystal Display controller supports management of a second display area called a graphic window. Similar to the background plane, the graphic window is supported in LCD color panel screens for viewfinder and graphic hardware cursor functions. The position and size of the graphic window displayed on and LCD screen is programmable, and it is overlaid on top of the background plane. The graphic window can be alpha blended with the background plane. This process combines the graphic window with the background plane allowing the two planes to render new blended colors and/or images. Another feature supported by the controller is color keying for a graphical hardware cursor. Color keying is the removal of color from one image to reveal another image in the background. As shown in the diagram, there are two parallel data paths. One for the background plane and one for the graphic window, also known as the foreground plane. Data for the background and foreground planes are fetched from system memory (for example, SDRAM) via the LCD controller s internal DMA controller. The LCD controller DMA controller accesses the system memory using fixed length or dynamic burst length, depending on the desired system performance. After data is loaded into the buffer, the LCD controller can byte swap the data or perform hardware panning if those operations are selected. If the data is in 4bpp or 8bpp format, then that same 4bpp or 8bpp data will be used and an index into a color mapping table to select an 18-bit color. Data in 12bpp, 16bpp, or 18bpp do not use the color mapping table. The background data and graphics window data is then shifted to an alpha blending module which combines the two planes with reference to an alpha value or a color key. The alpha blending module then generates a single image. The image is then shifted to either a gray scale or color interface buffer depending on the image type. From one of these buffers the image is directed to an interface logic block to be shifted out to a panel. One last thing to note, configuring the LCD clock and the LCD panel timing correctly is critical in establishing a properly operating display. 17

18 Question Match the module names with their descriptions by dragging the letters on the left to their appropriate locations on the right. Click Done when you are finished. A Physical Layer Interface Controller (PLIC) module C Allows the MCF5249 to receive and transmit digital audio over serial audio interfaces (IIS/EIAJ) and digital audio interfaces (IEC958). B High Level Data Link Control (HDLC) software module D Allows the MCF52429 to decode/encode CD ROM formats through the audio interface module. C Audio Interface module B A bit-oriented open systems interconnection (OSI) Layer 2 protocol commonly used in data communications systems D CD ROM Block Decoder/Encoder A Allows the MCF5272 to connect at a physical level peripheral devices that use either the General Circuit Interface (GCI) or Interchip Digital Link (IDL) physical layer protocols. Done Reset Show Solution Now, let s check your understanding of the various Coldfire modules. Correct. The correct answers are shown. 18

19 Summary PLIC (MCF5272) TDM Ports (MCF5272) IDE Interface (MCF5249) Audio (MCF5249) CD ROM Block Decoder/Encoder LCD Controller In this module, you learned about the various Application Specific Peripherals found on our ColdFire devices. You learned about the Physical Layer Interface Controller (PLIC), the TDM Ports, the IDE Interface, the Audio interface, the CD- ROM Block Decoder/Encoder module, and the Liquid Crystal Display (LCD) controller. 19