Mitigating FPGA Interconnect Soft Errors by In-Place LUT Inversion

Transcription

1 Mitigating FPGA Interconnect ot Errors y In-Place LUT Inversion Naieng Jing1, Ju-Yueh Lee2, Weieng He1, Zhigang Mao1, Lei He2 1 2 chool o Microelectronics, hanghai Jiao Tong University, hanghai, hina* Electrical Engineering Department, University o aliornia, Los Angeles, UA Astract Modern RAM-ased FPGAs (Field Programmale Gate Arrays) use multipleer-ased unidirectional routing, and RAM coniguration cells in these multipleers contriute to the majority o sot errors in FPGAs. In this paper, we ormulate an In-Placed inversion (IPV) on LUT (Look-Up Tale) logic polarities to reduce the ot Error Rate () at chip level, and reveal a locality and NP-Hardness o the IPV prolem. We then develop an eact algorithm ased on the inary integer linear programming (ILP) and also a heuristic ased on the simulated annealing (A), oth enaled y the locality. We report results or the 10 largest MN cominational enchmarks synthesized y AB and then placed and routed y VPR. The results show that IPV otains close to chip level reduction on average and A is highly eective y otaining the same reduction as ILP does. A recent work IPD has the largest LUT level reduction o 2.7 in literature, ut its chip level reduction is merely 7% due to the dominance o interconnects. In contrast, A-ased IPV otains nearly chip level reduction and runs 30 aster. Furthermore, comining IPV and IPD leads to a chip level reduction o 5.3. This does not change placement and routing, and does not aect design closure. To the est o our knowledge, our work is the irst in-depth study on reduction or modern multipleer-ased FPGA routing y in-placed logic re-synthesis. Keywords - RAM-ased FPGA; ot Errors; ; Routing; Interconnect; Fault Mitigation; Logic Re-synthesis; Logic Polarity I. INTRODUTION Modern RAM-ased FPGAs use RAM cells to conigure logic and interconnects, numerically totaling up to 160 million in XilinVirte-6 [1]. These FPGAs suer rom single event upset (EU) induced sot errors, and their resilience against EU decreases with technology scaling. Thereore, reducing the sot error rate () or RAM-ased FPGAs has gained growing signiicance. lassic Triple Module Redundancy (TMR) employs circuit redundancy oth in LUT and interconnect ut with high overhead in area, power and perormance. Recent logic re-synthesis techniques, such as ROE [2], IPR [3], IPD [] and R2 [5] reduce in LUTs y leveraging dierent logic masking techniques. Targeting on low or no cost in area, power, perormance and design closure, they are preerred y non-mission-critical applications, e.g. networking and communications, which in act are the primary applications o FPGAs. However, these techniques do not eplicitly consider the interconnect and thus chip level reduction could e limited due to the interconnect dominance in FPGAs. The paper is organized as ollows. ection II introduces the ehavior and evaluation o the sot error on the unidirectional routing architecture. Net, we ormulate the IPV prolem in section III and present IPV properties and algorithms in section IV. ection V shows the eperimental results and section VI concludes this paper. II. PRELIMINARIE A. FPGA Architecture and Interconnect Fault An FPGA architecture is mainly deined y onigurale Logic Blocks (LBs) and routing architectures as illustrated in Fig. 1. Interconnects are critical ecause they contriute a large portion o total FPGA area and total coniguration its. In our concerned unidirectional routing architecture, oth the interlb routing (including connection oes and switch oes) and intra-lb routing employ directional MUXes to route signals. Each MUX is typically conigured y several encoded coniguration its (RAM its), which contriute to the majority o the RAM its in an FPGA. For eample, we oserve that interconnects contriute to nearly 80% o the RAM its or the 10 largest MN enchmarks when they are synthesized to the minimum FPGA dimensions y 6-input LUT [12]. As illustrated in Fig. 1, when one o the its lips its value due to a sot error on a MUX, an erroneous input signal (dotted) is then selected. I this signal rom the aulty MUX reaches the Modern FPGAs have shited to multipleer-ased (MUXased) unidirectional routing architecture [6][7], where the ault mechanism is dierent rom conventional idirectional * upported y National Hi-Tech Research and Development Program (863) o hina under Grant No.29AA This work was partially sponsored y isco and JPL /11/$ IEEE routing in the previous studies [8][9]. In this paper, considering MUX-ased unidirectional routing, we ormulate an In-Place inversion (IPV) o LUT logic polarities to reduce the interconnect, and reveal a locality and NP-Hardness o the IPV prolem. We then develop an eact algorithm ased on the inary Integer Linear Programming (ILP) and a heuristic algorithm ased on the imulated Annealing (A), oth enaled y the locality. We report results or the 10 largest MN enchmark circuits mapped y AB [10] and then placed and routed y VPR [11]. The results show that IPV can otain nearly reduction on chip level. In addition, the A approach is highly eective, otaining the same quality o results when compared to eact ILP solutions ut is much aster in runtime. In contrast to the IPD algorithm with highest 7% chip-level reduction among [2-5], A-ased IPV otains nearly reduction and runs 30 aster. Furthermore, comining IPV and IPD leads to 5.3 reductions at the chip level. This does not change placement and routing, and thus has no impact on design closure. To the est o our knowledge, this work is the irst in-depth study on reduction or modern MUX-ased FPGA routing y the in-placed logic re-synthesis. 582

2 1 a,+ m MUX m LB LB LB LB LB LB LB v(i) pin i v(j) pin j,+ a,+ 0 1,+ c,+ (0) = 0 (1) = 1 (010) = 0 (011) = 1 (1) = 0 (101) = 1 (110) = 1 (111) = 0 c,+ o,+ a,,+ + positive logic negative logic c, (0) = 1 (1) = 0 (010) = 1 (011) = 0 (1) = 1 (101) = 0 (110) = 0 (111) = 1 o, (0) = 1 (1) = 0 (010) = 0 (011) = 1 (1) = 1 (101) = 0 (110) = 1 (111) = 0 o,+ Figure 2. Atomic operations or LUT logic polarity inversion. Figure 1. FPGA unidirectional routing and multipler structure. m MUX m inputs on net i: B. Fault Rate Evaluation We evaluate the ailure rate or each RAM it under the single ault assumption1 y, which is deined as ollows. + inputs on net j: (+) (+) (+) Logic Inversion ( ) & mu osevaility: = DEFINITION 1: For a circuit with n primary inputs, the sot error rate o a RAM it, denoted as is the proaility o unctional ailures on the circuit due to the EU on it. Pr( ( ) ( ) EU ) k 1 primary outputs o the chip, a unctional ailure at the chip level occurs. Note that this ault mechanism is not a ridging ault as studied or idirectional routing in [8][9]. (k): [ ] /10 = 0.5 [] /10 = 0 Figure 3. LUT polarity inversion improves ault tolerance on interconnects. (1) where (0,1)n is the ehaustive set o input vectors and () is the circuit outputs under, and () is the circuit outputs when is lipped due to EU. The can e otained y ehausting 2n input vectors, which is a very time-consuming process. In practice, it can e approimated y a Monte arlo ased ault simulation o as many as K times, which can provide a good accuracy as studied in [1]. each input and the output o an LUT in FPGA (see one eample in Fig. 2). This technique is called logic polarity inversion and has een used to optimize timing [15] and power [16]. Here, we use an eample in Fig. 3 to show how logic polarity inversion helps to reduce on a single LUT. Given the oservaility or the MUX and the two values on pin i and pin j, one can see that the o k can e reduced rom 0.5 to 0 y inverting the logic polarity on net j. In general, the metric o applies to any circuit element as long as it is conigured y RAM its. For eample, we introduce R in (2), as the total routing to evaluate the sensitivity o unctional ailure to all the RAM its in routing elements denoted y R. We also quantiy the circuit ault rate y all the RAM its in various elements in circuit as in (3), which is reerred as chip level in this paper. B. Prolem Formulation Logic polarity inversion may lead to conlict among multiple LUTs. An eample is illustrated in Fig., where m1 may require LUT 2 as negative to locally mitigate the ault, while m2 may require LUT 2 to stay positive. To ind an optimal logic polarity assignment or all the LUTs and minimize R, we ormulate the In-Place inversion (IPV) prolem as ollows. R R (2) (3) III. FORMULATION 1 (In-Place inversion Prolem): Given a circuit, assign the logic polarity or each LUT, such that the or all multipleer-ased interconnects is minimized. We provide a ipartite graph representation in Fig.5 or a etter understanding o our IPV prolem, where each ottom node Li represents one o the n LUTs, and each top node k represents one o the m RAM its used in the routing MUXes in the placed and routed circuit. There is an edge etween Li and k i Li is either correctly or mistakenly y k at a MUX. PROBLEM FORMULATION A. Motivating Eample o Fault Masking As illustrated in Fig. 1, when MUX m has one o its RAM its lipped due to EU, the output is driven y net j instead o the desired net i. I j carries a dierent logic value v(j) rom v(i), a ault is injected onto the inputs o the immediate an-outs o m. However, i v(j) equals to v(i), no ault is injected even i EU happens. That is, the ault can e instantly masked at m. In addition, also depends on the oservaility don t care o MUX m, ov(m), which indicates i the ault can e masked y logic during its propagation to circuit outputs as in [3]. As a result, can e given y (v(i) v(j)) ov(m). Given the single ault assumption, each RAM it connects two LUT nodes, known as a pseudo an-in LUT pair, and are denoted L(k) and l(k). For the eample in Fig., L(k) = LUT 3 is the desired driving LUT and l(k) = LUT 1 is the selected driving LUT due to EU. Thereore in Fig. 5, each k has eact two incoming edges, ut the degree o each Li depends on the numer o MUXes it connects to. Each k is annotated with a it value that is associated with the polarities o its pseudo Note that logic polarity can e independently determined on 1 imultaneous multiple EUs seldom happen in commercial FPGAs as reported in [13]. 583

3 pseudo an-in LUT pair L()=LUT 3, l()=lut 1 LUT 1 LUT 2 LUT 3 m 1 m 2 in m 3 Figure. The pseudo an-in pair o a EU aected it m L 1,+ L 2,+ L 3,+ L n,+ Figure 5. IPV prolem representation y a ipartite graph LUT 5 LUT an-in LUT pair (as stated y Property 2 elow). Thus, our IPV prolem tries to reassign the polarity or each L i, so that R can e minimized or all k (k=1,, m). IV. A. Properties o IPV Prolem PROPERTIE AND ALGORITHM PROPERTY 1: Our IPV prolem is NP-Hard. ketch o PROOF: IPV prolem can e reduced rom the inary Ma-um (laeling) prolem which is known to e NP-Hard [17]. We skip the details o the proo due to the limited space. In IPV prolem, when one or multiple LUTs are selected to e inverted or ault masking, R should e updated accordingly ater each inversion. Intuitively, each update needs a new pass o circuit ault simulation that is highly time-consuming. In this paper, we reveal that R can e analytically updated y a pre-calculation o the it ault rates ased on property 2. PROPERTY 2 (Locality o Bit upon Polarity Inversion): Under the single ault assumption and or a given logic network, or a routing RAM it solely depends on the logic polarities o its pseudo an-in LUT pair, independent o the polarities o the other LUTs in the network. We also skip the proo due to the limited space here. B. Locality ased alculation Based on the locality property, the R with possile inversions can e calculated or at most compleity to R as in (). ) ) 01 ) ) () 10 ) ) 11 ) ) where the quadruplicate values o {, 01, 10, 11 } are called a quadruplet o it. Each quadruplet provides our error rates indicated y the two superscripted numers, indicating i one o its pseudo an-in LUTs is inverted or not. For areviation, we denote it as [P L(), P l() ], where P is a unction indicating the polarities o LUTs L() and l(), i.e. + or. Thus, the total routing R can e written as R [ P L( ), Pl ( ) ] R Eq. (5) reveals that R or a given circuit can e updated as an algeraic sum upon each RAM it y its quadruplet. To get their values, we currently use the ault simulation method that is within compleity o the R in (2). In this way, the iterative ault simulation ater each reassignment o LUT polarity can e avoided.. Binary ILP Based Algorithm In this section, we use a inary ILP ormulation to provide an insight on the capaility o IPV improvement. We take a set o inary variales i to denote whether a LUT i is inverted or not, i.e., a positive LUT has its i as 0. A inary inverting quadruplet {, 01, 10, 11 } is used to denote the polarities o the pseudo an-in LUTs or each routing it. As a result, the inary ILP ormulation or our IPV prolem is given y min s.t. R (5) ij (6) R 1 s 1 t ij ij, 01,10, s where s =L(), t =l(). This set o constraints models the act that eactly one value in the quadruplet { ij } should e selected or each it using ij as a mask. Other constraints on 01, 10 and 11 can e similarly written as in (7). By orcing the corresponding i values to e 0 in the constraints, our ILP ormulation also applies to the situation where some LUT input or output polarities are not invertile D. imulated Annealing Based Algorithm We also propose a imulated Annealing (A) ased algorithm to solve IPV eiciently while providing good quality o routing reduction compared to ILP. The A ased algorithm starts rom the initial circuit with positive logic polarities or all the LUTs. Then, it switches to another LUT polarity assignment y inverting a random LUT polarity at each move. The ojective unction o the new assignment is evaluated y (5). New assignment with a etter cost is always accepted while the worse assignment is accepted conditionally ased on the acceptance proaility. The annealing starts rom a temperature o 0.8, and is updated y a decreasing actor o 1.3. It continues till the minimum temperature o 2.0e-6 is reached. E. Overall Algorithm Flow As illustrated in Fig. 6, our IPV algorithm mitigating EU ault on FPGA interconnects y LUT logic polarity inversion consists o three phases. tarting rom the given netlist o a circuit, it irst applies logic optimization and technology mapping. The mapped circuit is packed into logic locks, and then placed and routed y physical design tools. econdly, in order to otain the it values, we develop an EU ault analysis ramework which starts right ater P&R. It perorms logic simulation ased on post-layout circuit inormation to calculate t (7) 58

4 Atomic logic inversion ircuit Logic Logic Optimization & Technology Mapping ynthesis and Placement & Routing Architecture File EU Fault Analysis on FPGA interconnects Polarity inverted LUTs Re-synthesis low or the in-place inversion prolem riticality quadruplet ILP model & solver imulated Annealing Figure 6. The overall low o our IPV algorithm the ault rate or each RAM it in routing MUXes in the orm o quadruplet. This is the asis or oth the inary ILP and the A-ased approaches. Finally, we start the ILP solver and the A-ased approach to seek the optimal reassignment o the polarities or all the LUTs. The result with maimum interconnect ault rate reduction is then selected and ack-annotated to the initial circuit y the atomic logic inversion operations to inish our proposed re-synthesis low. V. EXPERIMENTAL REULT A. Eperimental ettings In this section, we report the eperiments or the 10 largest MN cominational circuits as in []. We used parameterized architecture in VPR [11] to characterize dierent FPGA architectures. Firstly, we perorm logic optimization and technology mapping onto and 6-input LUTs y Berkeley AB [10]. Each mapped circuit is packed y two dierent LB architectural settings respectively, i.e. -input LUT with cluster size and 6- input LUT with cluster o 8. Then, VPR was used to implement a minimum dimension FPGA array without incurring etra unused RAM its that eceed the actual need o the circuit. We applied a Monte arlo ased ault simulation to generate the it quadruplets. Note that our IPV algorithm applies to either cominational or sequential circuits to mitigate interconnect EU aults as long as the it quadruplets are availale. We used Mosek as our ILP solver to seek the gloally optimal assignment o the LUT polarities. B. omparision etween the ILP and A appraoches Tale I irst presents size statistics o the enchmark circuits. Net, it compares ault rate reductions in terms o ratios eore and ater applying IPV y ILP and A approaches or all routing MUXes. From the tale, one can see that oth ILP and A approaches signiicantly reduce. For eample, or a -input LUT with cluster size, the interconnect is reduced y 1.2 to 17.2 with an average around 6. For a 6- input LUT with cluster size 8, the is reduced aout 5. on average. In addition, y considering the RAM it percentage, the can e reduced y 3.97 and 3.67 on average at the chip level or the -input and 6-input LUTs, respectively. The reduction or 6-input LUT and 8 LUTs per cluster is slightly smaller, ecause larger LUT and cluster sizes have ewer interconnects and ewer MUXes that limit the room or improvement. While it is natural or dierent circuits to otain dierent improvements, des has the lowest and much smaller reduction. This is ecause the quadruplicate values are high and close to each other in des, which limits the design reedom that can e leveraged y IPV. Tale I also reports runtimes. The runtime ecludes the ault simulation time or quadruplets, which is relatively small compared to the runtime consumed y ILP. From the tale, one can see that ILP is ale to solve most o the circuits optimally while A can otain the same reductions as ILP ut runs almost 1 aster. For the other circuits as marked, where a timeout o 10 hours is applied to the ILP solver like in des, A otains slightly higher reductions. These results show that the A approach is highly eective and eicient or IPV prolem. It is worthwhile to point out that circuits like des are not the largest circuits in eperiments, so the eiciency o ILP depends on oth circuit size and structure. When ILP and A otain the same reductions, LUT inversions in their solutions are oten not the same and ILP inverts ewer LUTs in general. This implies that there are multiple optimal solutions rom the point o view o reduction. TABLE I. INTERONNET AND HIP LEVEL REDUTION FOR 10 BENHMARK IRUIT LUT size k=, luster size N= LUT size k=6, luster size N=8 ircuit Int. Int. hip Int. Int. hip #LUT Reduce RAM #LUT Reduce RAM ILP A it% Reduce ILP A ILP A it% Reduce ILP A e5p * 25.6 alu * * 27.2 mise ape ape seq e des * * 3.5 spla pdc Avg

5 TABLE II. HIP LEVEL REDUTION OMPARED TO PREVIOU WORK IPV IPD IPD+IPV ircuit Reduce Reduce hip Int. hip LUT hip Reduce IPV IPD e5p alu mise ape ape seq e des spla pdc Avg hip Level Reduction ompared to Previous Work Because A is eective and eicient, A is used or IPV in the rest o this paper. Tale II reports chip level reductions, y comparing IPV with a previous IPD algorithm [] on mapped 6-input LUTs. Although IPD signiicantly reduces the ault rate on LUTs (around 5), its chip level reduction is merely 7%, ecause it does not consider interconnects eplicitly. Thereore, uture mitigation algorithms should e developed with eplicit consideration o interconnects. In Tale II, we also evaluated the comined algorithm o IPD+IPV on 6-input LUTs, where the IPV is applied ater IPD. Because IPD is perormed within each LUT, it is orthogonal to IPV. From the tale, we see that the comination o these two algorithms reduces chip level y 5.3 on average. With much reduced interconnect y IPV, the reduction y IPD or LUTs (or in general, y algorithms rom [2-5]) gains more signiicance. Finally, Tale II compares runtimes or IPV and IPD and shows that IPV runs 30 aster on average. VI. ONLUION AND FUTURE WORK By targeting on routing multipleers that are the dominant routing elements in the modern unidirectional FPGA routing architecture, we have identiied a new ault masking mechanism and ormulated an IPV prolem or In-Place inversion o LUT logic polarities to maimize ault masking or all interconnect multipleers. We have shown that the prolem is NP- Hard and also revealed a locality or IPV. Due to the locality, we have developed two algorithms ased on ILP and A approaches. Eperiments have shown that IPV otains nearly reduction on average or the chip level. In addition, A is eective and eicient ecause it otains the same ault reductions as ILP, i not etter, ut runs almost 1 aster. Note that IPV does not change placement and routing, thereore it is an in-place optimization. It should have little or no impact on design closure. This will e veriied in the uture. IPV has otained close to reduction on average or the chip level. The est eisting in-place algorithm is IPD [], which has merely aout 7% chip-level reduction ut runs 30 slower. However, comining IPV and IPD leads to a chiplevel reduction o 5.3 on average. This is ecause IPV and IPD target at interconnects and LUTs respectively and they are complementary to each other. While the proposed IPV algorithms and implementations apply to oth cominational and sequential circuits, we have not yet developed calculation or sequential eedacks. This will e the ocus o our uture work. Furthermore, the interaction etween IPV and those techniques rom literatures such as [2-5] will e studied or urther mitigation. REFERENE [1] Xilin, Virte-6 Family Overview. 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