Bus-Switch Coding, for Dynamic Power Management in off-chip communication channels.

Transcription

1 in off-chip communication channels. Mauro Olivieri *, Francesco Pappalardo ** and Giuseppe Visalli **. * Department of Electronic Engineering, University of La Sapienza Rome, Italy ** Advanced System Technology, ST Microelectronics, Catania Italy Olivieri@dei.uniroma1.it, Francesco.Pappalardo@st.com, Giuseppe-ast.Visalli@st.com ABSTRACT The dynamic power management (DPM) represents an important challenge for extending the attery lifetime in a portale system. The power management, ased on static and off-line approaches, does not consider the asic property of a modern attery, which recovers a fraction of its charge during the idle time. The DPM approach profiles a complex system in different power figures depending on a reduced set of macro-states. The DPM prolem gives a sequence of macro-states which increases the attery lifetime. The dynamic power management is also required in complex systems where the power dissipation in communication channels represent a dominant factor. The modern communication arrangements operate at rate of some G Bit/sec, which implicated high transition activities, responsile of the dynamic power consumption. Moreover, the signal level involved in the output pads has a quadratic contriution in the dynamic power. The prolem of low-power us encoding has een extensively tackled in the past. The asic approach minimizes the transition density, directly related to the lines switching activities, responsile of the load/unload of the parasitic capacities. The current literature on low-power us encoding provides solutions, which do not guarantee a good activity saving increasing the us lines; this issue represents a huge limitation in the modern communication channels, which require high transmission andwidth. The paper introduced a novel low-power us encoding approach, ased on tentatively encoding, clustering and re-ordering the lines of a wide system data us used in multi-processor scenario. The Bus-Switch mechanism, as novel us encoding approach, drastically reduces the transition activity, preserving the required andwidth for high data-rate communications. Since the optimal us switch encoder complexity grows significantly decreasing the level of clustering, a su-optimal approach requires power management policy in order to effectively control the attery life. The paperwork presents an overview of the us-switch mechanism, including the required architecture for encoding/decoding the input lines. The RTL-model has een translated in a modern technology lirary at 90nm low-leakage using the Synopsys Tool for placement and CTS

2 (Physical Compiler v sp1 with Minimum Physical Constraint). We investigated y means of Synopsys Tools the integrity with respect to the ANSI C ehavioral model (VCS and custom PLI), the efficiency of coding (Power Compiler) and critical paths analysis (Primetime). Moreover, the paper addressed the asic guidelines for a software-controlled dynamic power management policy for communication channels, in order to increase the attery life. We presented a run-time power management system, which controls the configuration of the su-optimal us switch encoder, depending on the attery model that considered oth the discharge and recovery effects. The simulations indicated an increasing up to 10% in attery life, operating at 500 K-Bit/sec using a Pentium IV platform. The suoptimal us switch encoder, controlled y an efficient dynamic power management system, represents a good design - performance trade off. 2

3 Tale of Contents 1.0 Introduction The Bus Switch Mechanism The BS VLSI design implementation The power management policy for communication channels Simulation Results BS efficiency measured y means of Synopsys tools Conclusion and Discussions 12 Tale of Figures Figure 1 the roadmap for us-speed in the Intel s family processors.. 15 Figure 2 the Bus Switch Activity performance (Lines=32 Cluster depth=4) Figure 3 the BS activity savings, varying the us input lines, compared to the known algorithms.15 Figure 4 implementation of the swap operation (M=4). The asic swap ox 16 Figure 5 implementation of the swap operation (M=4). The complete swap unit. 16 Figure 6 twin swap unit for the implementation of coding functions II and III 16 Figure 7 architecture of the single unit inside the encoder..16 Figure 8 the L-way BS encoder..16 Figure 9 the BS decoder (Type I)...16 Figure 10 the BS decoder (Type II) 17 Figure 11 the BS decoder (Type III)..17 Figure 12 a multi-processor architecture, with BS-ased communication channels 17 Figure 13 the run-time software-controlled power management system.. 17 Figure 14 the minimum us capacitance for convenient BS at 90 nm 17 Figure 15 the 2-pipe stages BS encoder (Type III): 32lines,4 ways and 16 optimized patterns 18 Figure 16 BS critical path at 90nm and 10ns clock cycle, using Primetime.18 Tale1 examples of pattern and inverse pattern 13 Tale 2 different BS types, varying the coding-decoding functions.13 Tale 3 switching activity reduction of BS, referring to the three coding proposed functions.13 Tale 4 switching activity reduction of BS, assuming a reduced reordering pattern set (16 over 24 possile patterns). Bus width=32, M=4 14 Tale 5 the increased attery lifetime, using a run-time DPM ased on BS approach...14 Tale 6 timing report for 2-pipe BS at 90nm (fast clock 2.5 ns)

4 1.0 Introduction Nowadays, the challenge for reducing power dissipation in VLSI systems has the primary goal to decrease energy, maintaining acceptale some other performance constraints. The power-aware design methodology could e effectively applied to the interconnection media responsile of the major dynamic power consumption in a multi-processor system. The roadmap for the interconnection channels speed had a quadratic law (figure 1) for the Intel processor family in the last decade. In particular, the information rate is very close to the operative frequency, requiring high-speed communication channels. Most of communication channels employee parallel uses for transmitting information at high data rate. A single us line with capacity C and working at frequency 1/T dissipates a dynamic power: 1 P = 1! C! V 2 DD!"! (1.1) 2 T The dynamic power depends also from power supply Vdd and transition activity, which represents the 0->1 and 1->0 logic transitions. The technological approach for low-power uses decreases the signal level (Vdd) or us frequency (1/T). The signal level cannot always e decreased for signal integrity purposes in off-chip channels. Additionally, a reduced us frequency introduces a strong ottleneck with high-speed core at elevate information demand. The Bus Switch (BS) [8] [12] mechanism represents a possile answer for a very low-power us encoding, preserving the required andwidth for high-speed transmission. It is ased on tentatively encoding, clustering and reordering the input lines according to a reordering scheme. The complexity of us-switch encoder implies the use in off-chip communication system scenario, where the power savings involved y parasitic effects overcome the required energy for coding. The hardware required for us switch encoding could e effectively reduced operating in a su-optimal mode; the encoder performs a su-set of trials operating with an optimal su-set of reordering schemes. The process of scheme selection comes from either an on-line or off-line analysis. The paperwork introduced shortly the us switch mechanism, including the VLSI circuit implementation for a set of encoding approaches. We included the performance in terms of activity savings simulating, y ANSI C ehavioral encoder/decode models, a typical traffic in a modern System on a chip: inaries and multimedia files. Moreover, a complete synthesis flow has een pushed using the Synopsys Tool Physical Compiler and a technology lirary at 90nm from ST Microelectronics. The performance power trade off could e improved y a run-time dynamic power management policy. This work illustrates how the configuration of a suoptimal BS encoder could e changed on the fly permitting the employment of light BS implementation at the same activity saving performance. The proposed dynamic power management policy enales power states which dynamically increase the attery lifetime in a portale device. The effectiveness of the proposed approach has een demonstrated y discrete-time simulations [1] in ANSI C of the dynamic power manager and an accurate attery model, which consider oth the discharge and recovery effect [9]. A complete BS encoder operates at 50 MHz with 32-lines, which implies an information demand rate of 1.6Git/sec. This circuit saves the 30% in toggle activity operating in us capacitance etween 2pF and 4pF (typical values for off-chip lines in the target technology). The Run Time DPM manager, which aim is the increasing of attery lifetime, permits a transmission rate of 500Kit/sec, operating in a Pentium IV ased platform. The attery lifetime is increased up to a 10%. The employed su-optimal encoder increases the range of allowed us capacitance for a convenient use of the BS approach. The su-optimal us switch encoder, 4

5 controlled y an efficient dynamic power management system, represents a good design - performance trade off. The paper is organized as follows. Section 2 introduces the BS mechanism. The BS VLSI circuit implementation is explained in section 3. Section 4 illustrates the DPM policy for communication channels which use the BS encoder/decoder. Simulation results indicate the activity savings for BS mechanism oth for complete and reduced architecture in section 5. Moreover, this section presented the gain in attery lifetime using the proposed approach for a run time DPM. Section 6 investigated y means of Synopsys tools possile enhancement in VLSI design, performing power estimation and static timing analysis (STA). Lastly, section 7 is reserved for our conclusion and point of discussions. 2.0 The Bus-Switch Mechanism In principle, the BS technique can e logically expressed as a four-step process: 1. A large us is divided into several identical clusters of M (cluster depth) lines each. 2. Each M-line us is coded y reordering the input lines using a particular reordering pattern 3. A tentative data encoding is otained y applying to the swapped M lines a fixed coding function. 4. The process is repeated M! times from step 2 until the optimal reordering pattern is found, that minimizes the output switching activity in the encoded data of the whole us. In the following a formal definition of the process is given. Let (t) e input data word to the us encoder and B opt (t) the encoded data word on the us, at clock cycle t. The single its of any M-it data word x(t) will e indicated as x(t)(0), x(t)(1),, x(t)(m-1) Definition 1. A reordering pattern p(t) is an ordered set of M indices i 0 i M-1, associated with clock cycle t. Given a data word x(t), the swap operator S w with reordering pattern p is a cominational logic function producing a swapped data word y(t) = S w ( x(t), p(t) ), such that : y(t)(0) = x(t)( i 0 ), y(t)(1) = x(t)( i 1 ),..,.. y(t)(m-1) = x(t)( i M-1 ). As an example, if p(t) = "1,2,3,0" and x(t) = "0100", then S w ( x(t), p(t) ) = "1000". Note that each reordering pattern p(t) has a unique inverse p -1 (t), such that x(t) = Sw [( Sw ( x(t),p(t) ), p -1 (t)]. Examples of reordering patterns and their inverse are shown in Tale 1. Definition 2. A coding function is a cominational logic function producing a data word B(t), applying swapping to (t) and employing any other words resulting from input or output oservation. 5

6 Definition 3. The optimal reordering pattern p opt (t) is the reordering pattern that minimizes the switching H B opt t "1! B t, where H is the Hamming distance from previous transmission [ ] activity ( ) ( ) B opt (t - 1) and the coding function result, varying the reordering pattern. Figure 2 illustrates the activity savings, stimulating the us with inary and multimedia enchmarks and employing the following coding and decoding function: B ( ) ( t) = S ( ( t), p( t )" S B( t ), p ( t) W ( t) = S S B( t ), p ( t) w w [( ( )" B( t ), p ( t) ] w The us switch mechanism implicates several design performance trade-off: The pattern has to e transmitted onto extra lines for the exact decoding. Since the pattern employees few additional lines, a known us encoding could e used (Bus Invert, Adaptive Bus Invert, etc.) for further activity savings. The us switch encoder (BSE) grows in complexity increasing the cluster depth M. In particular, the optimal BS allows M! different patterns. This issue suggests the employment of a reduced and optimized su-set of reordering patterns, decreasing the hardware complexity. Figure 2 shows how a reduced and optimized pattern set (M=4 and 16 patterns BS4X (16)) does not affect relevant performance degradation with respect to the optimal scheme (OPT-BS4X (24)). The process of patterns selection could e on-line or off-line (Figure 2) driven y the activity savings. The activity savings do not significantly change, varying the us input lines (Figure 3). The off-chip uses represent the ideal field of application for the BS mechanism. The physical implementation, in 130nm low-leakage technology, suggests a convenient use of BS systems in uses with loads from 2 to 4pF, typical values for off-chip uses [8]. There are several degrees of freedom for choosing the coding function. As example we illustrated the changes in the micro-architecture using the coding functions illustrated in Tale The BS VLSI design implementation. This section illustrates the Bus Switch VLSI circuit implementation, starting from the ottom level architecture to the top. 3.1 Encoder The reordering patterns can e sequentially generated y a finite state machine (FSM) very similar to a inary counter. The direct inary representation of a reordering pattern is a vector of M inary numers each ranging from 0 to M-1, therefore requiring M log2 M its. The swap operation is performed y a set of multiplexers as in Fig. 4 and 5. Referring to M = 4, the 8-it pattern is partitioned into four 2-it numers, namely A, B, C, D in the Figure. 4. 6

7 Coding function I is directly the swapped word. Coding functions II and III are implemented y a twin swap unit, illustrated in Figure. 6; the conversion from a reordering pattern to its inverse is directly implemented y a dedicated two-level cominational logic unit PConv. A fully sequential implementation of a BS decoder would require the unit to perform M! sequential attempts efore selecting the est pattern and corresponding encoded word. This would imply an operating clock frequency at least M! times faster than the us operating frequency. More conveniently, a partially or fully parallel implementation can e pursued, employing L units, each performing M! / L attempts. In the following we will refer to such solution as an L-way parallel architecture. The corresponding architecture for the single unit is shown in Figure. 7. PatGen is the FSM that generates the set of allowed pattern to e tried; H produces the Hamming distance etween two words y performing a population count after XOR-ing. The Cmp unit compares the actual Hamming distance measured with the temporary minimum. When all the patterns have een tried and the minimum distance found, the threshold unit stores the pattern, the encoded word and the distance value on output registers. Figure 8 shows the top view of the encoder architecture. A special attention is deserved y the pattern transmission over the us. Though a direct representation requires M log2 M its, the actual numer of valid patterns is at most M! in a full pattern set, and even less in a reduced pattern set. Therefore, y introducing a dedicated cominational compressor transforming the direct representation into a symolic inary representation, the extra-lines to transmit the patterns must e at most log2 M!. In addition, in order to minimize the switching activity in those extra lines, a conventional Bus Invert (BI) coding is used on them. 3.2 Decoder When using coding function I, the decoder architecture is directly the one depicted in the top part of Figure 9. The PConv cominational lock performs the pattern conversion to otain the inverse pattern. In addition, a BI decoding unit and a cominational de-compressor elaorate the extra-lines dedicated to pattern transmission, to reconstruct the direct representation of the transmitted pattern. Figure 10 and 11 show the architecture of the decoder for coding functions II and III, respectively. 4.0 The power management policy for communication channels. We explained in two different and independent ways, how the BS-ased communication channels increased the attery lifetime in a multi-processor system. The theoretical approach, formalizes the prolem accordantly with the current scientific literature on DPM. The practical point of view helps the system engineers for an easy implementation. The suoptimal BS approach considers a reduced set of trials, which implicates a circuit with a decreased area and energy dissipation. This set of trials represents the BSE current configuration. The proposed software controlled DPM policy simulates the BS-encoder with every possile configuration, estimating the attery lifetime. This issue represents the common point for the following susections. The RT-DPM policy considers a set of possile configurations for encoding the input stream, searching for the est, which minimize the attery s discharge rate parameter, directly dependent from the us transition activity. In this section we considered an L-line us, divided into identical clusters of M-lines each. 7

8 4.1 Practical Realization of the proposed DPM policy. The proposed DPM policy is essentially ased on run time software controller strategy. The comined hardware software co-design permits an easy implementation in multi-processor systems ased on us switch approach. These are the essential requirements: 1. The RTL-Model of a su-optimal Bus Switch Encoder / Decoder. Experimental results indicate for cluster depth M=4 a minimum pattern set of R=8 different reordering patterns. 2. The RTL-Model of a BS-Driver, which transmits the current configuration at every BS encoder in the system. 3. An original su set of reordering patterns coming from an off-line analysis (I). This analysis selects the most used patterns, which represent the initial set. 4. Software BS-model used for simulating the attery lifetime. This ANSI C code needs to e the fastest implementation. Some compiler optimizations for timing can e used. 5. A software model of the considered attery. This model has to take account of the discharge rate and recovery effects. The discharge rate will depends on the total switching activity, measured y the BS-simulator. This parameter will e linked with the dynamic power only. The static current does not depend of the BS configuration, so it will e neglected. The recovery effect depends on the us idle time. The estimated traffic rate in each considered us is used for calculating the recovery effect parameter. The current literature indicates this parameter strongly dependent from the actual attery charge (attery state) 5. A real time clock for measurements. Alternatively, a cycle accurate ISS simulator can e used. The DPM policy admits a numer of power states (that is configurations) identical to the possile cominations of I patterns taken R y R. S ( I % & # = ' R$ I! R!( " I! R)! = (4.1.1) The DPM manager makes S trials, measuring the total switching activity. This activity permits the discharge rate parameter calculation. In particular, each channel has a percentage of activity as the actual activity / maximum activity ratio (see 4.2.1). The discharge rate parameter is the percentage of switching activity with respect the total activity in whole uses (see 4.2.2). The discrete-time simulation permits the attery simulation in order to calculate the total lifetime. The attery state represents the internal charge. The ANSI C code elow shows the attery simulation, which depends on the calculated discharge rate and recovery effects. The attery is unloaded when the internal state is zero. After S trials, the DPM manager identified the est configuration updating, y BS-drivers, the BS encoders in the system. 8

9 void sim_step(attery *p) { doule num; } num = uniform(); // Generate a random real positive numer less than 1.0 if ( num < p->discharge_rate) p->current_state = p->current_state - 1; // The attery lost charge units else if ( num < *(p->recovery+p->current_state)) // The recovery effect depends on actual state p->current_state = p->current_state + 1; // The attery recovers charge 4.2 Formal Approach to the proposed DPM policy. The software controlled DPM approach enales novel con-figurations of the emedded system, in order to increase the attery lifetime. This susection introduces the methodology for controlling, via software, the power dissipation in multiprocessor systems, which use the BS mechanism for low energy interconnections (Figure 12). The BS encoder performs trials, growing in numers with factorial law, depending on the input lines in the cluster. A reduced and optimized set of reordering patterns does not significantly affect activity savings, in oth on-line and off-line configuration modes. Let us consider an L-line us, divided into identical cluster of M-lines each. The initial pattern set implicates M! different permutations. We operate with an initial decreased set of I reordering patterns ( I! M! ) starting from an off-line analysis. Moreover, in order to reduce the hardware, the effective BSE uses R different patterns ( R! I ).The proposed DPM policy considers a much reduced set of BSconfigurations, depending on the possile cominations of su-set input patterns (see 4.1.1). The proposed DPM policy admits S different power states, for each channel, which implicates different us transition density varying the input traffic. Let us assume an initial S power state for channel : 0 The power manager (Figure 13) analyzes N different S KN transmissions; represents the power state at step k. This system performs S different trials, employing a software BS model, measuring the transition density: $ ( S ) us _ activity = = max_ us _ activity L # ~ i= 1 n x i ~ ( N " T, S ) N " L (4.2.1) The BS system, which employees the current configuration S ~ encodes the input traffic at xi rate 1/T, introducing a numer of transitions n in the generic i-th us line. The attery s discharge rate parameter used in [9] is strongly dependent from the total transition density. If the system admits B different channels: 9

10 disch arg erate = B " = 1 # ~ ( S KN) B (4.2.2) The charge recovery state depends on us idle time, during the time interval [0, NT].Since the recovery effect does not depend on the us transition activity, the power state at step k+1 minimizes the discharge rate only: B B B [ ]! ( S )" [ S k + N S k + M ] S ~ min ~ 1 1 ~ # ( 1), ( 1), L, S L, = 1 (4.2.3) 5.0 Simulation Results. 5.1 The complete BS system. The RTL architectural description of complete BS encoder has een translated in a 90nm technology lirary at 50 MHz. This frequency represents the minimum latency for a 4-Way encoder in a 32-it lines and cluster depth 4 (BS-Type III). In these operative conditions the proposed encoder performs an activity savings more than 20% with respect the un-coded transmission (Tale 3). We considered the transmission of inaries and multimedia data at clock rate; these enchmarks derive from a Linux distriution. The use of a reduced pattern set, from an off-line analysis, does not significantly changes the performance as illustrated in Tale 4 and Figure 2. The 50 MHz clock permits an operative transmission at 1.6Git/sec. 5.2 The DPM policy, which employees a su-optimal BS system. The proposed DPM policy changes on the fly the encoder current configuration, in order to increase the attery lifetime, in a multi-processor system. We derived an analytical model of the attery ehavior, which considered oth the Recovery and Rate Capacity effects [9]. These effects depend on the us idle time and the transition density related to the current configuration. The simulations consider the transmission of inary and multimedia streams with an idle time uniformly distriuted in [0, NT/10]. In particular, a 32-lines system us has een encoded with the BS mechanism, which employed the coding function (III), cluster depth 4 and R=8 different patterns in an original set of I=11 (BS4X (11), S=165). The BS current configuration is updated every N=20 transmissions (slots). The analyzed-slots / updated-slots ratio has een fixed to 20:20. The attery model considers 3000 charge units, with a time constant of 97.5msec. The RT-DPM achieves an increased attery lifetime up to 10% with respect a BS-ased interconnect system without power management policies (Tale 5). These enchmarks have een simulated in ST200 emedded core platform at 400 MHz from ST Microelectronics. The time for profiling (~60msec) limited the communication channels andwidth up to 10 Kiloit/sec. A more attractive communication andwidth could e reached operating with a different analyzed-slots / updated-slots ratio. For example, operating with a ratio of 20:500 (updates the state every 500 slots) the Pentium IV core processor executes the run time power manager in less than 1 micro second, permitting an operating frequency of 500 Kiloit/s. 10

11 6.0 BS Efficiency measured y means of Synopsys Tools. The efficiency of the proposed us encoding scheme for low-power has een possile, exploring the RTL alignment with ANSI C ehavioral model y Synopsys VCS and custom PLIs. Additionally, the convenience with respect to the known us encoding approaches has een validated measuring the BS encoder power dissipation y Synopsys Power Compiler. In particular, we calculated the gain in energy compared to the un-coded transmission in a typical off-chip communication scenario: the PCI local us. Finally, the real implementation cannot neglect the impact of critical timing arcs, which represents the actual frequency cutoff for a convenient use of BS approach. Primetime tool help us to explore timing critical paths in order to extend the BS field-of-application. 6.1 VCS validated the ehavioral ANSI C BS-model. The activity savings illustrated in Tale 3 and 4 derives from a ANSI C us switch model, which analyzes enchmarks used in Linux OS: LaTeX distriution, Berkeley Spice, Gcc compiler and samples of Jpeg, MP3 and AVI files. The RTL validation compared the produced waveform with respect to the C model. In particular we compared the sequence of reordering pattern and the output us versus time. The circuit model (Verilog) needs particular interfaces for stimulating the us accesses during enchmarks (PLIs). VCS validated with success our RTL model for us switch encoding. 6.2 Power Compiler demonstrated the efficiency of coding The efficiency of coding could e demonstrated, calculating the energy savings per cycles with respect an un-coded transmission. The proposed enchmarks have een used also for gate level simulation, in order to estimate the encoder power consumption. The total alance of average energy saving per us cycle is therefore: E saved = 0.5 switching_reduction C us V dd 2 energy_overhead Where energy overhead represents the BS encoder energy dissipation; the total energy saving percentage is expressed y the ratio E % = (0.5 C us V dd 2 E saved ) / (0.5 C us V dd 2 ) 100% A value of E % lower than 100% means that the BS is effective in reducing the total energy consumed per us cycle, while E % greater than 100% means that the us capacitance is so small that the energy overhead of the encoder dominates and the BS technique is inappropriate. Referring to the 90nm implementations of BS-III (32-it us, 4-it cluster size, 16 patterns) we can show the dependency of the E % from the us line capacitance, and compare it with typical applications. Fig. 14 shows the results for the 4-way implementation. We considered the typical PCI us electrical specifications: VDD=5 Volts. 6.3 Primetime explored time critical paths for increasing the maximum allowed us frequency. BS encoder represents a time critical circuit, due the presence of a secondary fast clock (used y Patgen), with respect the us cycle. Additionally, the huge numer of multiplexing 11

12 elements introduced a cut-off frequency hard to overcome. This susection summarizes the main results in static timing analysis (STA) y means of Synopsys Primetime Tool. Figure 15 illustrates the used BSE architecture with 2 pipeline stages and employing the Type III coding and decoding functions. As far as the pipeline architecture is concerned, coding function I and II permits pipelines, instead BS-III allows only a maximum one stage pipeline due the presence of B(t-1). Figure 16 represents the time critical path in a BSE translated in 90nm technology lirary from ST Microelectronics. The STA (Tale 6) concluded how the massive multiplexing (Swap Unit) implicates time critical arcs which represent one of the most limitations on an increased operative frequency. For this reason, a possile research could investigate on custom lirary cells for performing swapping operations. Additionally, the module for Hamming distance, which represents the 33% of the considered worst path, requires timing optimizations. 7.0 Conclusions The Bus Switch mechanism represents an interesting us encoding scheme for low-power, operating in a off chip wide system us. The multi processor environment represents the optimal field of application for encoding the data y our proposed approach. The hardware complexity could e reduced with a sustantially unchanged performance, ut increasing the minimal us capacitance for convenient utilization. This last issue permits a wide use for the proposed solutions in particular for increasing the attery lifetime in a portale device y an appropriate dynamic power management policy. The proposed run time policy permits an interesting activity savings with a data rate aligned with actual low-power us solution [3]. The BS approach might represent the starting point for energy efficient and high data rate multi-processor networks. References [1] L. Benini, A. Bogliolo and G. De Micheli Dynamic Power Management of Electronic Systems in Int. Conf on Computer-Aided Design (1998) [2] L. Benini, A. Macii, E. Macii, M. Poncino and R. Scarsi Architectures and Synthesis Algorithms for Power-Efficient Bus Interfaces IEEE. Trans. on Computer-Aided Design Vol.19, No.9 (2000) [3] K. Lahiri and A. ~Raughunathan Communication Based Power Management in IEEE Design and Test of Computers (2002) [4] J. Lorch and A. Smith Software Strategies for Portale Computer Energy Management in IEEE Personal Communications (1998) [5] Y. Lu and G. De Micheli Comparing System-Level Power Management policies in IEEE Design and Test of Computers (2001) [6] Y. Lu, T. Simunic and G. De Micheli Software Controlled Power Management [7] F. Najm Transition Density: A new measure of Activity in Digital Circuits in IEEE Transaction on Computer-Aided Design Vol.12, No.2 (1993) [8] M. Olivieri, F. Pappalardo and G. Visalli Bus Switch coding for reducing power dissipation in off-chip uses IEEE Transaction on Very Large Scale Integration, Vol 12, No 12 Decemer 2004 [9] D. Panigrahi, C. Chiasserini, S. Dey, R. Rao, A. Raughunathan and K. Lahiri Battery Life Estimation of Moile Emedded Systems in 14th International Conference VLSI Design (2001) [10] R. Siegmund, C. Kretzschmar, and D. Muller Adaptive Bus Encoding Technique for Switching Activity Reduced Data Transfer over Wide System Buses Proceeding of PATMOS (2000) [11] M. R. Stan and W.P. Burleson Bus-Invert coding for low-power I/O IEEE Transaction on VLSI Systems Vol.3 pp49-58 (1995) [12] G. Visalli and F. Pappalardo Process and device for reducing the us switching activity and computer program therefore US Application Patent

13 Tales P p Tale1 examples of pattern and inverse pattern BS- Type Encoding Function Decoding Function ( ) [( ( )" B( t ), p ( t) ] [( ( )" B( t ), p ( t) ] I. B( t) = SW ( ( t), p( t ) ( t) = SW B( t), p ( t) II. B( t) = SW ( ( t), p( t )" SW ( ( t ), p ( t ) ( t) = S w S w ( t ), p ( t) III. B( t) = S ( ( t), p( t )" S B( t ), p ( t) ( t) = S S B( t ), p ( t) W w ( ) Tale 2 different BS types, varying the coding-decoding functions w w Files BS I BS II BS III LaTeX 6.64 % % % Spice 4.30 % % % Gcc 5.90 % % % Jpeg % % % Mp % % % Avi 2.74 % 3.30 % % Tale 3 switching activity reduction of BS, referring to the three coding functions proposed. Bus width=32, M=4 Files BS I BS II BS III LaTeX 7.14 % % % Spice 5.16 % % % Gcc 6.47 % % % Jpeg % % % Mp % % % Avi 4.80 % 3.54 % % Tale 4 switching activity reduction of BS, assuming a reduced reordering pattern set (16 over 24 possile patterns). Bus width=32, M=4 13

14 Benchmark Battery Lifetime (sec) Battery Lifetime Gain % (no RT-DPM) (sec) (RT-BSE) Latex % Spice % Gcc % Jpeg % Mp % Avi % Tale 5 the increased attery lifetime, using a run-time DPM ased on BS approach Module Latency (ns) Percentage to fast clock Swap Unit 0.500ns 10.0% H (Hamming) 1.650ns 33.0% PConv (Pattern Conversion) 0.475ns 9.5 % Threshold Unit 0.340ns 6.8% Patgen 0.440ns 8.8% Network Delay 1.000ns 20.00% Other 0.595ns 11.9% TABLE 6 TIMING REPORT FOR 2-PIPE BS AT 90NM (FAST CLOCK 5 NS) Figures Processor Core Vs. Bus-Clock Clock Rate (MHz) DX2 486DX4 P-100 P-150 P-200 PII-300 PII-400 PII-500 PIII-600 PIII-700 PIII-800 PIV-1G PIV-1.5G Bus-Clock Processor Figure 1 the roadmap for us-speed in the Intel s family processors in the last decade 14

15 Figure 2 the Bus Switch Activity performance (Lines=32 Cluster depth=4) Figure 3 the BS activity savings, varying the us input lines, compared to the known algorithms Figure 4 implementation of the swap operation (M=4). The asic swap ox Figure 5 implementation of the swap operation (M=4). The complete swap unit Figure 6 twin swap unit for the implementation of coding functions II and III Figure 7 architecture of the single unit inside the encoder 15

16 Figure 8 the L-way BS encoder Figure 9 the BS decoder (Type I) Figure 10 the BS decoder (Type II) Figure 11 the BS decoder (Type III) Figure 12 a multi-processor architecture, with BSased communication channels Figure 13 the run-time software-controlled power management system 16

17 4-way 16 patterns 90nm implementation E% LaTeX Spice Gcc Jpeg MP3 AVI Reference Bus capacitance [pf] Figure 14 the minimum us capacitance for convenient BS at 90 nm Figure 15 the 2-pipe stages BS encoder (Type III): 32lines, 4 ways and 16 optimized patterns 17

18 Figure 16 BS critical path at 90nm and 20ns clock cycle, using Primetime 18