Lecture 2: Basic FPGA Fabric. James C. Hoe Department of ECE Carnegie Mellon University
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1 Lecture 2: Basic FPGA Fabric James. Hoe Department of EE arnegie Mellon University F17 L02 S1, James. Hoe, MU/EE/ALM, 2017
2 Housekeeping Your goal today: know enough to build a basic FPGA (even if not a very good one) Notices omplete survey on Blackboard, due noon, 9/5 Handout #2: lab 0, due noon, 9/8 Make friends, make teams, due noon, 9/8 Readings h 1, Reconfigurable omputing skim h 13&14 if interested skim databooks referenced for more details F17 L02 S2, James. Hoe, MU/EE/ALM, 2017
3 Before FPGA there was GA (AB) (X+Y) V GND F17 L02 S3, James. Hoe, MU/EE/ALM, 2017 A B X Y
4 Idea behind Gate Arrays Mass produce identical gate array wafers Finish into any design by custom metal layers (2) so called Mask Programmable GA (MPGA) reduced design effort (more automation, no layout) reduced mask and fab cost faster fab turn around Proliferation of ASI design starts don t need volume for economy of scale small design team could keep up with Moore s law F17 L02 S4, James. Hoe, MU/EE/ALM, 2017 Of course, not as efficient as full custom or standard cell designs
5 How about no mask, no fab? i.e., field programmable Again, mass produce identical devices but this time fully finalized Then what can be changed? SRAM EPROM (anti)fuse bits {1,0} {1,0} {1,0} connections pass gate mux {1,0} diode {1,0} A B F17 L02 S5, James. Hoe, MU/EE/ALM, 2017 A B A B programmable vs reprogrammable
6 F17 L02 S6, James. Hoe, MU/EE/ALM, 2017 Reconfigurable Logic Arbitrary logic (combinational and sequential) can be formed by wiring up enough NANDs or muxes Lookup table as universal logic primitive arbitrary n input function from 2 n entry table this is 8 by 1 bit memory f(,0, ) f(,1, ) f(0,0,0) f(0,0,1) f(1,1,0) f(1,1,1) X 0 f(,x, ) 1 Shannon expansion AB f(a,b,)
7 Size of Lookup Tables (aka LUTs) n input function from 2 n entry LUT ount only the 6T SRAM cells, an n LUT has 6 2 n T Some points of reference 2 input NAND = 4T 3 input NAND =6T 3 input full adder (a, b, c in ) s = a b c in = 8T c out = bc in +ac in +ab =18T 10 input 5 bit adder = 130T M.S. flip flop=16t (compare to 2 LUTs per latch) F17 L02 S7, James. Hoe, MU/EE/ALM, 2017 n LUT T count
8 hoosing LUT Granularity Small LUTs + fast propagation delay a given fxn consumes many LUTs (comes with wiring cost and delay) high interpretation overhead if too small Big LUTs slower propagation delay + a given fxn consumes fewer LUTs high interpretation overhead if too large (and fxn has exploitable structure) wastage if not all input are used in a LUT Where is the sweetspot? F17 L02 S8, James. Hoe, MU/EE/ALM, 2017
9 1980 s Xilinx LUT based onfigurable Logic Block (in a sketch) D A B 3 LUT 3 LUT X g(a,b,) {2,1,0} Y h(a,b,,d) {2,1,0} FF f(a,b,) {1,0} (also latch mode) 2 fxns (f & g) of 3 inputs OR 1 fxn (h) of 4 inputs hardwired FFs (too expensive to fake with LUTs) Just 10s of these in the earliest FPGAs F17 L02 S9, James. Hoe, MU/EE/ALM, 2017
10 ontemporary Xilinx LB Architecture each 6LUT is two 5LUTs LUTs can also be used as small SRAMs or shift register special paths for addition and multiplexer 2 slices per LB Largest devices (many $K each) have several 100K slices [Figure 2 3: 7 Series FPGAs LB User Guide] F17 L02 S10, James. Hoe, MU/EE/ALM, 2017
11 Even oarser Logic Blocks? So called oarse Grain Reconfigurable Arrays (GRAs) based on complete adders or ALUs native arithmetic units have low interpretation overhead if you are doing arithmetic poor fit if you are working with narrow data or bitlevel manipulations Even coarser is to use many tiny processors still a spatial computing paradigm not programmed with RTLs converging with software multicores F17 L02 S11, James. Hoe, MU/EE/ALM, 2017 More on this later in term
12 Mapping Logic To LUTs Start from primary output and input to registers, cover logic graph with cuts of less than K input edges K cuts corresponding to K LUT realizable functions [Figure 13.1: Reconfigurable omputing: The Theory and Practice of FPGA Based omputation ] F17 L02 S12, James. Hoe, MU/EE/ALM, 2017
13 Placement F17 L02 S13, James. Hoe, MU/EE/ALM, 2017 [Vivado Implementation Screenshot]
14 and Route F17 L02 S14, James. Hoe, MU/EE/ALM, 2017 [Vivado Implementation Screenshot]
15 PLA style onfigurable Routing AND OR?????? I 0 I 1 I n 1 O 0 O 1 O m F17 L02 S15, James. Hoe, MU/EE/ALM, 2017
16 Island Style Routing Architecture LB islands in sea of interconnects Flexible routing to support ASI style netlists Note regularity in structure F17 L02 S16, James. Hoe, MU/EE/ALM, 2017
17 Switch Block onfigurable Routing (1980s Xilinx simplified) B LB onnection Block F17 L02 S17, James. Hoe, MU/EE/ALM, 2017
18 Reconfigurable Routing is Expensive! Routing resource area is on par with logic Each configurable connection is area of configuration bit area of configurable connection And don t forget propagation delay Too much: cost for everyone who doesn t need it Too little: congestion leaves unreachable LBs unused worse for larger arrays/designs (why?) buy a $10K FPGA and only get to use 70%? F17 L02 S18, James. Hoe, MU/EE/ALM, 2017
19 Rent s Rule T g p T = number of inputs and outputs g = number of internal components p typically between 0.5 (regular) and 0.8 (random) In a square, perimeter=4 area 0.5 unless regular, I/O signals grow faster than available routes exiting a design area Need hierarchy of progressively longer additional routing resources long routes also reduce delay when going far F17 L02 S19, James. Hoe, MU/EE/ALM, 2017
20 Virtex II Routing Architecture 8 internal fast connects from LUT to LUT within a LB Switch Matrix connects to 1 LB 16 Direct onnections to 8 nearest switches Double Lines to 1 st or 2 nd switch (40 track) Hex lines to 3 rd or 6 th switch (120 per track) Long lines spanning device (24 per track) Later architectures extended in reach and in diagonals F17 L02 S20, James. Hoe, MU/EE/ALM, 2017 Separate, dedicated clock trees
![FPGAs: omplete Data Sheet] 18 643](/docs-images/82/85305169/images/21-1.jpg "F17 L02 S21, James.")
21 Virtex II Routing Architecture [Figure 48: Virtex II Platform FPGAs: omplete Data Sheet] F17 L02 S21, James. Hoe, MU/EE/ALM, 2017
22 Virtex II Routing Architecture [Figure 49: Virtex II Platform FPGAs: omplete Data Sheet] F17 L02 S22, James. Hoe, MU/EE/ALM, 2017
23 Latest in Routing Hierarchy Virtex7 Stacked Silicon Interconnect (SSI), 2011 Longest routes go across dies carried on interposer No change to design tool and abstraction [Figure 1, Stacked & Loaded: Xilinx SSI, 28 Gbps I/O Yield Amazing FPGAs, Xcell, Q1 2011] F17 L02 S23, James. Hoe, MU/EE/ALM, 2017
24 F17 L02 S24, James. Hoe, MU/EE/ALM, 2017 Altera Stratix X HyperFlex Long routes need buffered repeaters; very long routes need pipelining Add (bypassable) pipeline registers throughout RTL designs have to be pipelined explicitly to benefit; high level synthesized designs leverage directly a high freq strategy e.g., 0.5xlogic at 2xfreq for perf. parity [Figure 2: Understanding How the New HyperFlex Architecture Enables Next Generation High Performance Systems]
25 Don t Forget onfigurable I/O In/Out Dout {1,0} {1,0} {1,0} {fast,slow} {1,0} FF PAD Din {1,0} F17 L02 S25, James. Hoe, MU/EE/ALM, 2017 I/O Block real devices more complicated modern devices support special signaling and protocols
26 Putting it all together: An Universal ASI programmable routing I programmable lookup tables (LUT) and flip flops (FF) aka soft logic or fabric I/O pins Interconnect LUT FF F17 L02 S26, James. Hoe, MU/EE/ALM, 2017
27 Bitstream defines the chip After power up, SRAM FPGA loads bitstream from somewhere before becoming the chip a bonus feature for sensitive devices that need to forget what it does Many built in loading options Non trivial amount of time; must control reset timing and sequence with the rest of the system Reverse engineering concerns ameliorated by encryption proprietary knowledge F17 L02 S27, James. Hoe, MU/EE/ALM, 2017
28 Setting onfiguration Bits Behind the scene infrastructure doesn t need to be fast (usually offline) simpler/cheaper the better (at least used to be) ould organize bits into addressable SRAM or EPROM array very basic technology serial external interface to save on I/O pins row F17 L02 S28, James. Hoe, MU/EE/ALM, 2017 column
29 Serial Scan SRAM based config. bits can be setup as one or many scan chains on very slow config. clock φ 1 no addressing overhead all minimum sized devices φ 1 φ 1 φ 1 φ 1 At power up config manager handshake externally (various options, serial, parallel ROM, PI E,...) F17 L02 S29, James. Hoe, MU/EE/ALM, 2017 φ 1 φ 1 Full fledged config. architecture in modern devices to support scale and features φ 1
30 Modern onfiguration Architecture e.g., Stratix 10 Secure Device Manager triple redundant secure processor each sector managed by its own processor [Figure 2: Intel Stratix 10 Secure Device Manager Provides Best in lass FPGA and So Security ] F17 L02 S30, James. Hoe, MU/EE/ALM, 2017
31 Parting Thoughts Today, you can use an FPGA without knowing any of this stuff Basing this lecture on Xilinx vs Altera wouldn t change the big picture You can find a lot of specific details on line (databooks and research papers) So far still just the basic fabric more next time Also didn t say anything about design tools F17 L02 S31, James. Hoe, MU/EE/ALM, 2017
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