Glitch Reduction and CAD Algorithm Noise in FPGAs. Warren Shum

Transcription

1 Glitch Reduction and CAD Algorithm Noise in FPGAs by Warren Shum A thesis submitted in conformity with the requirements for the degree of Master of Applied Science Graduate Department of Electrical and Computer Engineering University of Toronto Copyright c 2011 by Warren Shum

2 Abstract Glitch Reduction and CAD Algorithm Noise in FPGAs Warren Shum Master of Applied Science Graduate Department of Electrical and Computer Engineering University of Toronto 2011 This thesis presents two contributions to the FPGA CAD domain. First, a study of glitch power in a commercial FPGA is presented, showing that glitch power in FPGAs is significant. A CAD algorithm is presented that reduces glitch power at the post-routing stage by taking advantage of don t-cares in the logic functions of the circuit. This method comes at no cost to area or performance. The second contribution of this thesis is a study of FPGA CAD algorithm noise random choices which can have an unpredictable effect on the circuit as a whole. An analysis of noise in the logic synthesis, technology mapping, and placement stages is presented. A series of early performance and power metrics is proposed, in an effort to find the best circuit implementation in the noise space. ii

3 Acknowledgements First and foremost, I would like to thank Professor Jason Anderson for supervising my thesis research, and for guiding me along with good ideas and encouragement. I would also like to thank Professors Jonathan Rose, Vaughn Betz, and Olivier Trescases, for reviewing this work and serving on my defence committee. I am also grateful to my parents, for supporting me in all my academic endeavors. Thanks to my fellow research group members: Marcel, Bill, Jason L., James, Andrew, Mark, Steven, Ahmed, Victor, Stefan, Alex, Kevin, and my office mates in PT477. I appreciate the feedback on my work, the sporting activities, as well as just sharing conversation. Thanks to the staff at SciNet for their technical support. I thank NSERC and OGS for financial support throughout my degree. iii

4 Contents 1 Introduction Field-Programmable Gate Arrays Glitch Power CAD Algorithm Noise Glitch Power and Don t-cares in FPGAs Introduction FPGA Architecture Glitch Power in FPGAs Previous Work on Glitch Reduction in FPGAs Don t-cares in Logic Circuits Glitch Power Analysis Analysis of Don t-cares Conclusion Glitch Reduction Using Don t-cares Introduction Glitch Reduction Algorithm Computing the Don t-cares for a LUT Scanning the Input Vectors Setting the Don t-cares iv

5 3.2.4 Iterative Flow Methodology Results Fanout Splitting Conclusion FPGA CAD Algorithm Noise Introduction CAD Flow Stages Logic Synthesis Technology Mapping Placement and Routing Methodology Noise Measurement: Before Place and Route Noise Measurement: After Place and Route Conclusion Early Timing and Power Prediction With Noise Introduction Previous Work on Early Delay/Power Prediction Delay Prediction Varying pin delays Logic, routing and constant factors Maximum/scaled metrics Power Prediction Packing Methodology Results v

6 5.8 Conclusion Conclusions Summary Glitch Reduction CAD Algorithm Noise Future Work Glitch Reduction CAD Algorithm Noise A Circuit Delay/Power Statistics With Noise 78 A.1 Individual Design Noise Results Bibliography 78 vi

7 List of Tables 2.1 Glitch example truth table for a logic function with inputs abc and output f. A possible example of cares is given (care = Y, don t-care = N ) Percentage of dynamic power from glitches Percentage of simulated local LUT input states corresponding to don t-cares Standard deviation of noise (before place-and-route) Standard deviation of noise (after place-and-route) Average percentile of top circuits with isolated model parameters Average benefit of prediction models A.1 Critical path delay statistics by circuit A.2 Dynamic power statistics by circuit vii

8 List of Figures 2.1 (a) Logic blocks and routing in an island-style FPGA architecture. (b) Example of a 3-input LUT (look-up-table) with truth table in Table Example waveform showing a glitch on the output of a LUT f with truth table given in Table (a) Example of SDCs (left) and ODCs (right). (b) Miter circuit used in don t-care analysis [Mish 05] Example: before glitch reduction. (a) LUT with don t-care SRAM bit shaded. (b) Simulation waveform Example: after glitch reduction. (a) LUT with altered don t-care SRAM bit shaded. (b) Simulation waveform with glitches removed A cluster of don t-cares Experimental flow (a) Dynamic power reduction vs. baseline (default) don t-care settings and worst-case settings. (b) Glitch power reduction vs. baseline (default) don t-care settings and worst-case settings Average vote bias (a) Power per signal vs. fanout. (b) Normalized don t-cares per node vs. fanout Fanout splitting Stratix III adaptive logic module (ALM) [Alteb] viii

9 3.10 Dynamic power reduction from fanout splitting FPGA CAD flow Example of an And-Inverter Graph (AIG) Example of an AIG before balancing (logic levels shown in parentheses) Examples of balanced AIGs Example of AIG rewriting Number of circuits vs. normalized nodes/level (balancing noise) Number of circuits vs. normalized nodes/level (rewriting noise) Number of circuits vs. normalized nodes/level (refactoring noise) Number of circuits vs. normalized nodes/level (depth-oriented mapping noise) Number of circuits vs. normalized nodes/level (area-oriented mapping noise) Number of circuits vs. normalized nodes/level (all noise) Number of circuits vs. normalized delay Number of circuits vs. normalized dynamic power Synthesis noise: (a) Number of circuits vs. normalized delay. (b) Number of circuits vs. normalized power Delay rank of circuits under synthesis noise averaged across 4 and 5 placement seeds Technology mapping noise: (a) Number of circuits vs. normalized delay. (b) Number of circuits vs. normalized power Slow and fast inputs on lookup tables Example for the pin utilization timing model Example for the pin order timing model ix

10 5.4 Probability of finding the top circuit vs. percentage of top modeled circuits considered (delay) Percentile of predicted top circuits (delay) Probability of finding the top circuit vs. percentage of top modeled circuits considered (power) Percentile of predicted top circuits (power) x

11 Chapter 1 Introduction 1.1 Field-Programmable Gate Arrays Field-programmable gate arrays (FPGAs) are user-configurable logic devices capable of implementing digital circuits. These devices are used in a wide variety of areas including communications, automotive, industrial and consumer markets. The appeal of FPGAs versus application-specific integrated circuits (ASICs) is that they allow the user to avoid the high cost of chip fabrication, as well as they reduce time-to-market. FPGAs allow a hardware designer to prototype their design quickly, while an ASIC design would take more time and money to repair, should an error be found. Mask set costs at 45nm can cost as much as $2M [Fran 10], a cost high enough to drive away all but the highestvolume applications. To create an FPGA implementation of a design, a hardware engineer will typically use a hardware description language (HDL), such as Verilog or VHDL. A series of computeraided design (CAD) tools transform the HDL into a digital circuit that can be programmed onto the FPGA. A typical sequence of steps in the CAD flow is as follows: Logic Synthesis: The logic functions needed to implement the circuit are derived and optimized. 1

12 Chapter 1. Introduction 2 Technology Mapping: The logic functions are mapped into the logic elements specific to the target device architecture. Packing: The logic elements are grouped into larger units corresponding to the target device architecture. Placement: The mapped logic elements are placed into physical locations on the target device. Routing: The proper connections are made between the logic elements using the programmable routing network. The quality of the resulting circuit depends on the quality of the tools used to generate it. Quality can be measured in terms of area, performance and power. It is here that FPGAs fall short of ASICs the area, performance and dynamic power gaps between them have been estimated at 40x, 4x and 12x, respectively [Kuon 07]. By studying existing CAD algorithms and exploring new ones, FPGAs can close the gap with ASICs and attract a larger portion of the digital logic market. 1.2 Glitch Power As mentioned previously, one area for improvement in FPGAs is power consumption. Power can be reduced through efforts at various stages: the architectural level, the circuit level, or the CAD level (which will be the focus here). In particular, glitch power (the power dissipated by unnecessary signal transitions) is an attractive target for reduction since it comprises from 4% to 73% of total dynamic power, with an average of 22.6% [Lamo 08]. We present two contributions in this area, the results of which have been published [Shum 11]: 1. An analysis of glitch power in commercial FPGAs.

13 Chapter 1. Introduction 3 2. A CAD approach for reducing glitch power at no cost to area or performance. Chapter 2 provides background on FPGA glitch power. It begins with a description of how glitches occur in FPGAs, and some previous works on how to reduce glitch power. To motivate our research, we present our own analysis on glitch power in commercial FPGAs. Our results show an average of 26% of dynamic power from glitches. This chapter also describes don t-cares in logic functions, which will be used in the glitch reduction algorithm. We show that the average occurrence of don t-cares under simulation is sufficient to supply ample opportunities for our algorithm. Chapter 3 presents an algorithm for glitch power reduction which can be performed post-routing, incurring zero area and performance cost. The algorithm takes advantage of don t-care bits in the truth tables of functions in a circuit, setting them to values which minimize the amount of glitch power dissipated. The algorithm is tested with a commercial FPGA CAD tool suite and architecture, and shows an average glitch power reduction of 13.7%, and an average dynamic power reduction of 4.0%. 1.3 CAD Algorithm Noise Given the tremendous challenge of solving modern-day CAD problems, the algorithms used for these problems generally use heuristics to seek a reasonable solution in an acceptable amount of time. In the course of exploring the vast solution space of these problems, there is often a need to choose between two or more alternatives that appear to have the same quality. Such choices, although seemingly innocuous at the time of selection, can have ripple effects on future choices, causing the final quality of the circuit to vary if different choices are made. We label these variations as noise. We present the following contributions in this area:

14 Chapter 1. Introduction 4 1. An analysis of a series of logic synthesis and technology mapping algorithms, exposing potential sources of noise that have not been studied before. 2. Experimental results on the amount of noise present in several CAD algorithms, in terms of critical path delay and dynamic power. The concept of power noise is also a new contribution which has not been previously studied. 3. A method for predicting the best circuits in terms of performance and power in the presence of noise. Chapter 4 introduces the concept of CAD algorithm noise. We expose hidden sources of noise in the logic synthesis and technology mapping algorithms of the academic CAD tool ABC [Berk 06]. We present the results of our noise analysis, showing the effects of random choices in thousands of circuit compilations. The results of the noise injection show a standard deviation of as much as 3.3% in critical path delay, and 3.7% in dynamic power. Chapter 5 presents a solution to the variance in circuit quality produced by CAD algorithm noise. The idea is to perform several synthesis and mapping runs of a circuit (using different seeds) and use early timing and power metrics to predict the best one(s) to advance to the placement and routing stages. This would save the time that would be spent on a large number of place-and-route runs. In this chapter, a wide array of early timing prediction models are evaluated, including several approaches to estimating logic and routing delays. For power prediction, two fast simulation models are used, as well as information from the packing stage of the CAD flow. The application of these prediction models in a commercial FPGA leads to an average benefit of up to 1.8% in delay and 1.8% in power compared to the average noise-injected circuit. Chapter 6 concludes the work. We summarize the contributions of the previous chap-

15 Chapter 1. Introduction 5 ters and present possible extensions and related research topics for future work.

16 Chapter 2 Glitch Power and Don t-cares in FPGAs 2.1 Introduction Power in FPGAs can be divided into two categories: static power and dynamic power. Static power is due to current leakage in transistors. Dynamic power is a result of signal transitions between logic-0 and logic-1. These transitions can be split into two types: functional transitions and glitches. Functional transitions are those which are necessary for the correct operation of the circuit. Glitches, on the other hand, are transitions that arise from unbalanced delays to the inputs of a logic gate, causing the gate s output to transition briefly to an intermediate state. Although glitches do not adversely affect the functionality of a synchronous circuit (as they settle before the next clock edge), they have a significant effect on power consumption. Using an academic FPGA model, glitch power has been estimated to comprise from 4% to 73% of total dynamic power, with an average of 22.6% [Lamo 08]. This is a significant motivator for the reduction of glitch power. As a means of reducing glitch power, we seek to take advantage of don t-cares in a circuit. Don t-cares are an important concept in logic synthesis and are frequently 6

17 Chapter 2. Glitch Power and Don t-cares in FPGAs 7 used for the optimization of logic circuits. A don t-care of a logic function within a larger circuit is an input state for which the function s output can be either logic-0 or logic-1, without affecting the circuit s correctness. Don t-cares can come from external constraints or from within the circuit itself. An external constraint may be specified by the designer (e.g. asserting that a certain input combination will never be applied). A logic function within a circuit may also have don t-cares due to its surrounding logic, for example, if the logic feeding the function s fanins can never satisfy a certain input combination, or if the function s output does not affect the circuit s primary outputs under certain circumstances. This chapter is organized as follows. Section 2.2 gives a brief overview of basic FPGA architecture. Section 2.3 describes how glitches occur in FPGAs. Section 2.4 summarizes some previous works on FPGA glitch reduction. Section 2.5 describes don t-cares and how they can be found. Section 2.6 gives our analysis of glitch power, while Section 2.7 gives our analysis of don t-cares. Section 2.8 summarizes the chapter. 2.2 FPGA Architecture Before presenting our glitch analysis and glitch reduction method, it is important to recap some basic FPGA architecture and terminology. Fig. 2.1(a) shows a section of a typical island-style FPGA architecture. It is composed of logic blocks connected to one another through a programmable routing network. Programmable routing switches (shown as x s in Fig. 2.1(a)) allow pins on logic blocks to be programmably connected to pre-fabricated metal wire segments, and also allow wire segments to be programmably connected with one another to form routing paths. Inside the logic blocks, logic functions are implemented using look-up-tables (LUTs). An example is shown in Fig. 2.1(b). A k-input LUT can implement any logic function of up to k variables. In essence, a LUT is a hardware implementation of a truth table, where

18 Chapter 2. Glitch Power and Don t-cares in FPGAs 8 (a) (b) Figure 2.1: (a) Logic blocks and routing in an island-style FPGA architecture. (b) Example of a 3-input LUT (look-up-table) with truth table in Table 2.1. the output value for each minterm is held in an SRAM configuration cell (bit). A k-input LUT requires 2 k configuration bits. For this work, we target an FPGA that contains 6- input LUTs, which are typical of modern commercial FPGA architectures [Altec, Xili]. 2.3 Glitch Power in FPGAs The dynamic power consumed by an FPGA can be modeled by the formula P dyn = 1 2 n i=1 S i C i fv 2 dd (2.1) where n is the number of nets in the circuit, S i is the switching activity of net i, C i is the capacitance of net i, f is the frequency of the circuit, and V dd is the supply voltage. The glitch reduction algorithm presented in this work aims to lower the switching activity as a means of reducing dynamic power. As a result of the differences in delays through the routing network and LUTs themselves, signals arriving at LUT inputs may transition at different times, leading to glitches.

19 Chapter 2. Glitch Power and Don t-cares in FPGAs 9 Figure 2.2: Example waveform showing a glitch on the output of a LUT f with truth table given in Table 2.1. abc f Care Y Y Y Y N Y N Y Table 2.1: Glitch example truth table for a logic function with inputs abc and output f. A possible example of cares is given (care = Y, don t-care = N ) An example is shown in Fig This LUT implements the 3-input function given in Table 2.1. Consider the case where the inputs transition from Ideally, the output f would remain constant at 0. However, varying arrival times on the inputs may cause an input transition sequence such as , causing f to make a transition rather than remaining at 0. This leads to extra power consumed by the LUT and any of its fanouts that propagate the glitch. Furthermore, the glitch is propagated through the FPGA interconnect which presents a high capacitive load due to its long metal wire segments and programmable (buffered) routing switches. Prior work has shown, in fact, that interconnect accounts for 60% of total FPGA dynamic power [Shan 02].

20 Chapter 2. Glitch Power and Don t-cares in FPGAs Previous Work on Glitch Reduction in FPGAs Glitch reduction techniques can be applied at various stages in the CAD flow. Since glitches are caused by unbalanced path delays to LUT inputs, it is natural to design algorithms that attempt to balance the delays. This can be done at the technology mapping stage [Chen 07b], in which the mapping is chosen based on glitch-aware switching activities. Another approach operates at the routing stage [Dinh 09], in which the faster-arriving inputs to a LUT are delayed by extending their path through the routing network. Delay balancing can also be done at the architectural level. The work in [Lamo 08] inserts programmable delay elements to balance the arrival times of signals at LUT inputs. However, these approaches all incur an area or performance cost. Some works use flip-flop insertion or pipelining to break up deep combinational logic paths which are the root of high glitch power. Circuits with higher degrees of pipelining tend to have lower glitch power because they have fewer logic levels, thus reducing the opportunity for delay imbalance [Wilt 04]. Flip-flops with shifted-phase clocks can be inserted to block the propagation of glitches [Lim 05]. Another work in [Czaj 07] uses negative edge-triggered flip-flops in a similar fashion, but without the extra cost of generating additional clock signals. It is also possible to apply retiming to the circuit by moving flip-flops to block glitches [Fisc 05]. Our work draws inspiration from hazard-free logic synthesis techniques for asynchronous circuits, such as [Lin 95]. In asynchronous circuits, glitches (hazards) cannot be tolerated because they may produce incorrect behavior (consider, for example, the disasterous effect of a glitch on a handshaking signal). Our work is different in that while hazards are tolerable from a functionality standpoint, it is beneficial to remove them to reduce power consumption. A key feature of the work presented here is that it has no impact on the rest of the design flow. It is applied after placement and routing, and as a consequence, the algorithm has no cost in terms of performance or area. Other methods incur additional

21 Chapter 2. Glitch Power and Don t-cares in FPGAs 11 area/delay from the inclusion of delay elements, registers and extra routing resources, as well as disrupting the synthesis and layout of the circuit in an unpredictable way. Our approach maintains the results of the existing compilation while only making changes to the don t-cares within LUT truth table configuration bits. This zero-overhead method is a highly desirable quality not shared by previous glitch reduction approaches. 2.5 Don t-cares in Logic Circuits To prevent glitches, we take advantage of don t-cares. These are entries in the truth table where a LUT s output can be set as either logic-0 or logic-1 without affecting the correctness of the circuit. Don t-cares fall into two categories: satisfiability don t-cares (SDCs) and observability don t-cares (ODCs) [Mish 09]. SDCs occur when a particular input pattern can never occur on the inputs to a LUT. In the example shown in Fig. 2.3(a), the inputs a = 0, b = 1 will never occur. ODCs occur when the output of a LUT cannot propagate to the circuit s primary outputs. In the example, the output of f2 has no effect when c = 0. In this work, we leverage the don t-care analysis capabilities of the ABC logic synthesis network developed at UC Berkeley [Berk 06]. ABC incorporates Boolean satisfiability (SAT)-based complete don t-care analysis that can be used to determine the don t-care minterms for a given LUT in a technology mapped FPGA circuit [Mish 05]. To find the don t-cares for a given LUT, f, ABC uses a miter circuit, as illustrated in Fig. 2.3(b). As shown, two instances of LUT f and (some of) its surrounding circuitry are created the surrounding circuitry is shown as a shaded region in the figure. In one instance, f s output is in true form; in the other instance, f s output is inverted. The outputs of the two instances are exclusive-or ed with one another, with the XOR gate outputs being fed into a wide OR gate. The final OR gate produces an output logic signal C(x) for a given input vector x.

22 Chapter 2. Glitch Power and Don t-cares in FPGAs 12 (a) (b) Figure 2.3: (a) Example of SDCs (left) and ODCs (right). (b) Miter circuit used in don t-care analysis [Mish 05]. For an input vector x to the miter in Fig. 2.3(b), one can compute a local input vector y to LUT f. For any such x where C(x) is logic-1, y is a care minterm of LUT f; that is, LUT f affects the circuit outputs for input vector x. The basic approach taken in [Mish 05] is to use a fast vector-based simulation as well as SAT to find all vectors, x, where C(x) evaluates to logic-1, yielding the complete care set for LUT f. This provides a general picture of the don t-care analysis approach and the reader is referred to [Mish 05] for full details. Don t-cares have recently been used for area reduction in FPGA circuits [Mish 09]. 2.6 Glitch Power Analysis To motivate the need for glitch reduction, we examine the amount of glitch power dissipated by 20 MCNC benchmark designs. These designs were fully compiled using Altera Quartus 10.1, targeting 65nm Stratix III devices [Alteb]. ModelSim 6.3e was then used to perform a functional (zero-delay) and timing simulation of each circuit using 5000 random input vectors, producing two switching activity (VCD) files. The VCD files contain a record of every transition of every net in the circuit. The dynamic power was then computed using Quartus PowerPlay Altera s power analysis tool. The glitch filtering setting was enabled, as it only filters glitches that are too short to occur in an actual

23 Chapter 2. Glitch Power and Don t-cares in FPGAs 13 Circuit % glitch Circuit % glitch alu ex5p 41.6 apex frisc 10.7 apex misex bigkey 29.6 pdc 36.7 clma 24.2 s des 45.4 s diffeq 5.8 s dsip 29.9 seq 26.2 elliptic 12.2 spla 33.2 ex tseng 17.5 Average 26.0 Table 2.2: Percentage of dynamic power from glitches. FPGA. We only consider the core dynamic power that is, no static power and no I/O power. This was done in order to avoid skewing the results with power components unrelated to glitching. The glitch power was computed as the difference in dynamic power between the functional and timing simulations. The results are shown in Table 2.2. The percentage of dynamic power due to glitches ranges from 5.8% to 45.4%, with an average of 26.0%, which is similar to that reported in the academic FPGA context [Lamo 08]. This makes glitches an attractive target for power reduction in commercial FPGAs. We do not believe any prior published work has analyzed glitch power in a commercial FPGA. 2.7 Analysis of Don t-cares In order to evaluate the potential for a don t-care-based glitch reduction algorithm, we analyzed every local input vector seen by each LUT in each circuit across its timing simulation. This was done by taking the simulation output VCD generated by ModelSim and inputting it to ABC. In ABC, we traverse the simulation vectors for each LUT, and count the number of local input vectors to that LUT which correspond to its don t-cares. The percentage of such LUT input states which were don t-cares is shown in Table 2.3.

24 Chapter 2. Glitch Power and Don t-cares in FPGAs 14 Circuit % inputs DC Circuit % inputs DC alu ex5p 36.2 apex2 7.4 frisc 5.2 apex misex bigkey 3.7 pdc 37.2 clma 32.4 s des 0.8 s diffeq 3.9 s dsip 4.6 seq 7.6 elliptic 0.7 spla 33.8 ex tseng 12.4 Average 15.1 Table 2.3: Percentage of simulated local LUT input states corresponding to don t-cares. The percentages vary from 0.8% to 37.2%, with an average of 15.1%. This tells us that not only do circuits contain an abundance of don t-cares, but also that, surprising, these don t-cares are often traversed in circuit operation. In other words, a LUT s don t-care minterms are frequently visited under vector stimulus. The visits to such don t-care minterms may potentially lead to additional unnecessary toggles on LUT outputs. We can thus potentially reduce glitches through don t-care settings, which is the core idea of our approach (which will be described in the next chapter). 2.8 Conclusion In this chapter, we introduced basic FPGA architecture and gave an introduction to power consumption in FPGAs. We summarized some previous works in the area of glitch reduction. We described how glitches are generated, and presented our own analysis of glitch power consumption in commercial FPGAs. Glitch power was found to comprise an average of 26.0% of total dynamic power. We also explained logical don t-cares and how they can be found, as well as analyzing how often they occur in circuits. It was found that an average of 15.1% of visited LUT input states are don t-cares. Together, these results indicate that glitch power is a good target for power reduction, and that

25 Chapter 2. Glitch Power and Don t-cares in FPGAs 15 don t-cares are prevalent enough to enable a don t-care based glitch reduction algorithm. This algorithm will be presented in the next chapter.

26 Chapter 3 Glitch Reduction Using Don t-cares 3.1 Introduction In this chapter, we present a glitch reduction optimization algorithm based on don tcares. It sets the output values for the don t-cares of logic functions in such a way that reduces the amount of glitching. This process is performed after placement and routing, using timing simulation data to guide the algorithm. Relative to prior published FPGA glitch reduction techniques, our approach is entirely new, and leverages the ability to re-program FPGA logic functions without altering the placement and routing. Since the placement and routing are maintained, this optimization has zero cost in terms of area and delay, and can be executed after timing closure is completed. Section 3.2 describes the new algorithm for glitch reduction. Section 3.3 describes the methodology for testing the algorithm. Section 3.4 shows the power reduction results, and Section 3.5 summarizes the chapter. 3.2 Glitch Reduction Algorithm We begin with an example to illustrate how don t-cares can be used to prevent glitches. The general idea is to simulate the circuit, then traverse the simulation vectors for each 16

27 Chapter 3. Glitch Reduction Using Don t-cares 17 (a) (b) Figure 3.1: Example: before glitch reduction. (a) LUT with don t-care SRAM bit shaded. (b) Simulation waveform.

28 Chapter 3. Glitch Reduction Using Don t-cares 18 LUT, focusing on vectors corresponding to don t-cares. We keep a count of the number of instances for each don t-care when we would prefer setting it to logic-0 or logic-1 (based on the care outputs surrounding it). We will refer to these counts as votes. When the end of the simulation vectors is reached, we set the don t-cares to the value (logic-0 or logic-1) corresponding to the more popular vote. Figs. 3.1(a) and 3.1(b) show an example of a LUT and its simulation waveform. Let us assume that the truth table row for abc = 100 corresponds to a don t-care, found using the method described in Section 2.5. We illustrate the don t-care by shading its SRAM configuration bit in Fig. 3.1(a). We also assume that the don t-care bit is currently set to logic-1 an arbitrary choice. We initialize the vote counts to 0 (vote0 = 0, vote1 = 0). Now, we traverse the waveform of Fig. 3.1(b) from left to right, stopping when we encounter an input corresponding to a don t-care (DC). In this case, we encounter the don t-care input abc = 100 in the second time step. We then consider the previous LUT output and the next LUT output. In this case, we see that they are both logic-0. If we were to change the output for abc = 100 to logic-0 instead of logic-1, we would be able to prevent two glitch transitions on f. Therefore, we increment the vote counter for logic-0 (vote0 = 1, vote1 = 0). In the fourth time step, we encounter another don tcare flanked by two logic-0 outputs. We increment the vote counter for logic-0 again (vote0 = 2, vote1 = 0). At the sixth time step, we see the the neighboring outputs of this don t-care instance are logic-0 and logic-1. In this case, there would be one transition on f whether the don t-care is set to logic-0 or logic-1. Therefore, no change is made to the vote counts (vote0 = 2, vote1 = 0). At this point, we have exhausted the simulation waveform. We set the don t-care bit to logic-0, since vote0 is greater than vote1. The resulting LUT and waveform are shown in Figs. 3.2(a) and 3.2(b). We can see that four glitch transitions have been eliminated on output f. A more formal expression of the glitch reduction algorithm is shown in Algorithm 1.

29 Chapter 3. Glitch Reduction Using Don t-cares 19 (a) (b) Figure 3.2: Example: after glitch reduction. (a) LUT with altered don t-care SRAM bit shaded. (b) Simulation waveform with glitches removed.

30 Chapter 3. Glitch Reduction Using Don t-cares 20 It takes a placed and routed netlist as its input. We represent the netlist as a graph G(V, E), where V is the set of vertices (LUTs) and E is the set of edges (routing wires). The algorithm also takes a value change dump (VCD) file containing the results of a timing simulation of the circuit. The simulation vectors are denoted as S, where the i th local input vector to LUT n is denoted as S n [i]. A timing simulation is needed rather than a functional one because glitches arise from delay mismatches, which will only appear under timing simulation. The algorithm iterates through each LUT in the netlist, progressing from shallower levels to deeper ones. This order is used because glitches prevented on shallower LUTs will be prevented from propagating to deeper LUTs, thus saving more power. Within each level, the LUTs are examined in descending order of power consumption. This prioritizes the LUTs with the greatest potential savings. For each LUT, the following steps are performed: 1. Compute the don t-cares of the LUT. 2. Scan the input vectors. 3. Set the values of the don t-cares Computing the Don t-cares for a LUT As described previously in Section 2.5, we use ABC s SAT-based don t-care analysis to compute the inputs states (minterms) for the particular LUT which are don t cares (Algorithm 1, line 3). DC is the set of don t-care input states Scanning the Input Vectors The sequence of local input vectors to the LUT (denoted S n ) is extracted from the timing simulation VCD file. These input vectors are examined in order (line 5). When an input

31 Chapter 3. Glitch Reduction Using Don t-cares 21 Algorithm 1 Glitch reduction algorithm. Input: a netlist G(V, E) with simulation vectors S Output: a netlist with modified LUT functions 1: for each LUT n V in order of priority do 2: {1. Compute the don t-cares of the LUT} 3: DC = compute dont cares(n) 4: {2. Scan the input vectors} 5: for i = 0 to size(s n ) do 6: if S n [i] DC then 7: prev previous care output 8: next next care output 9: if prev = 0 and next = 0 then 10: V otes0(s n [i]) V otes0(s n [i]) : else if prev = 1 and next = 1 then 12: V otes1(s n [i]) V otes1(s n [i]) : end if 14: end if 15: end for 16: {3. Set the values of the don t-cares and update netlist} 17: for each don t-care d DC do 18: if V otes0(d) > V otes1(d) then 19: assign 0 as the output of d 20: else if V otes1(d) > V otes0(d) then 21: assign 1 as the output of d 22: end if 23: end for 24: end for vector S n [i] corresponding to a don t-care is reached (line 6), we look at the closest states in the past and future that correspond to care input vectors (lines 7-8). We use this information to decide whether this don t-care should be set to a logic-0, logic-1, or whether there is no preference. If the closest past and future cares are identical (both logic-0 or both logic-1) then the don t-care should be set to the same value. Otherwise, there is no preference. For each don t-care minterm, a count of votes is kept, indicating how many times in the simulation it would be beneficial to set it to a logic-0 or logic-1 (lines 9-12). This process is repeated for each input vector S n [i] in the full simulation time (lines 5-15). Consider again the example shown in Fig. 2.2 and Table 2.1. Suppose that for input S n [i] = 100, the LUT output is a don t-care. This means that even though it is assigned to logic-1 in the truth table, we can assign it to logic-0 or logic-1 without affecting the

32 Chapter 3. Glitch Reduction Using Don t-cares 22 Figure 3.3: A cluster of don t-cares. functionality of the circuit. In this case, we see a glitch on f making a transition as the inputs transition Looking at the closest care states before and after input 100, we see that they both output a logic-0. Therefore, the algorithm votes for the output of 100 to be logic-0. It is possible that the simulation data may include a long contiguous cluster of don tcares. In these cases, the more desirable state could be the opposite of the one that would be chosen by this algorithm. For example, it may be beneficial to set a particular don t-care to logic-0 within a cluster of logic-0 s (don t-cares) in between two logic-1 s (cares) rather than attempting to set the entire cluster to logic-1. This situation is illustrated in Figure The fourth time step shows a don t-care surrounded by other don t-cares which have high vote0 (i.e. they will be set to 0). Therefore, we can see that setting this DC to 0 would be preferable. However, the algorithm would set it to 1, as the nearest cares are both 1. This would cause a glitch. Fortunately, experimental data shows that such long clusters are uncommon. The average length of don t-care clusters in the benchmark set is 3.5. This justifies our use of the closest care input vectors Setting the Don t-cares When the end of the input vectors is reached, each don t-care is set to the value with more votes (unless the votes are tied, in which case nothing is done the choice is arbitrary).

33 Chapter 3. Glitch Reduction Using Don t-cares 23 The loop at lines walks through each don t-care d DC (the set of don t-care minterms) and checks whether logic-0 or 1 has a majority of votes. The netlist is updated accordingly before proceeding to the next LUT. This is critical because changing the logic function of one LUT can affect the don t-cares of other LUTs, due to incompatibility between don t-cares [Mish 09]. By ensuring that the don t-cares are computed using the most recent information, the circuit is guaranteed to remain functionally-equivalent to the original Iterative Flow Following the modification of the circuit, the simulation results become outdated, due to the changes to the LUT functions. Therefore, we repeat the simulation using the modified circuit after performing glitch reduction on the full circuit. The algorithm is then repeated. In practice, the majority of the glitch reduction occurs within the first three iterations. It is important to note that the loop of the iterative flow does not involve re-running placement and routing. This is vital for two main reasons. First, the results of the existing compilation will be preserved, so there is no interference with timing closure. Second, the delays within the circuit will be kept the same, thus minimizing the amount of change to the simulation vectors. This allows the algorithm to converge quickly. The algorithm runtime is on the order of minutes for the benchmarks used. Although the iterative process employs a timing simulation, the fact that this algorithm is performed after place-and-route mitigates the issue of runtime. We envision a usage scenario in which the designer runs this algorithm as part of a final pass after timing closure has been achieved. Since no modifications are made to the circuit s timing characteristics, timing closure is preserved.

34 Chapter 3. Glitch Reduction Using Don t-cares 24 Figure 3.4: Experimental flow. 3.3 Methodology We perform our glitch reduction algorithm on 20 MCNC benchmark circuits. The experimental methodology was chosen to include commercial CAD tools wherever possible, to evaluate the efficacy of the algorithm on real-world FPGAs. The flow is shown in Fig We perform a full compilation using Quartus II 10.1 (synthesis, placement and routing) targeting the Altera Stratix III 65nm FPGA family [Alteb]. This is followed by a timing simulation using ModelSim SE 6.3e. For each circuit, 5000 random input vectors are applied. We use a set of custom scripts to transform the simulation netlist generated by Quartus into BLIF format, which can then be read into ABC, where the glitch reduction is performed. Combinational equivalence checking (command cec in ABC [Mish 06c]) is used after the glitch reduction step to ensure that the functionality of the circuit remains the same. The output from ABC is used to modify the configuration bits in the simulation netlist, thus ensuring that the placement and routing remain identical. Three passes of the optimization loop are performed. Experiments show that very few changes, if any, are made after this point (i.e. further iterations have virtually no effect). The power measurements are performed using Quartus PowerPlay.

35 Chapter 3. Glitch Reduction Using Don t-cares 25 (a) (b) Figure 3.5: (a) Dynamic power reduction vs. baseline (default) don t-care settings and worst-case settings. (b) Glitch power reduction vs. baseline (default) don t-care settings and worst-case settings.

36 Chapter 3. Glitch Reduction Using Don t-cares Results The leftmost bars in Fig. 3.5(a) (vs. baseline) represent the percentage reduction in total core dynamic power after performing the glitch reduction algorithm. Immediately, we can see that about half of the circuits benefit from the algorithm. The average reduction is 4.0%, with a peak of 12.5%. Fig. 3.5(b) shows the corresponding reduction in glitch power. The average reduction is 13.7%, with a peak of 49.0%. Naturally, the amount of power reduction possible is based on the amount of glitching present and the number of don t-cares available. While the overall average power reductions are relatively modest, we believe they will interest FPGA vendors and power-sensitive FPGA customers, as they come at no cost to performance or area. For some circuits, over 10% power reduction can be achieved essentially for free. It is also interesting to look at the optimized power vs. the worst case don t-care settings possible, as illustrated by the rightmost bars in Fig. 3.5 (vs. worst-case). In this experiment, we set the don t-cares to the opposite of how they would normally be set by our optimization algorithm, to examine the potential worst-case glitch power arising from don t-cares. Here, we see an average total dynamic power savings of 9.8% and a peak savings of 30.8% (Fig. 3.5(a)). These results show that don t-care settings can potentially have a large impact on power if set to sub-optimal values. The varied results in Fig. 3.5 can be correlated with the glitch power and don t-care data in Tables 2.2 and 2.3. For instance, des had a high glitch power in Table 2.2, yet we did not observe a significant power reduction for this circuit. However, in Table 2.3, we see that it had only 0.8% of LUT inputs as don t-cares, thus reducing the number of opportunities for optimization. On the other hand, pdc had a high amount of glitching as well as ample don t-cares, thus allowing it to be greatly improved by the algorithm 12.5% dynamic power reduction. We also examined the bias of votes cast on each don t-care minterm in each LUT in each circuit. The average results are shown in Fig The bias is defined as the

37 Chapter 3. Glitch Reduction Using Don t-cares 27 Figure 3.6: Average vote bias. percentage of votes that were cast for the more popular setting, whether logic-0 or logic- 1. Bias is calculated for each don t-care individually and averaged across the circuit. As shown in the figure, the bias value tends to be in the % range, indicating that there usually exists a highly preferable setting for a particular don t-care minterm in a LUT. This is an important observation because it indicates that our don t-care settings are providing a benefit most of the time (as opposed to the case of a bias around 50%, which would imply that selecting either logic-0 or logic-1 for the don t-care minterm is equally good). These observations suggest that there usually exists a value for each don t-care (either 0 or 1) that is much better than the other, meaning that one can pick don t-care logic values with a high degree of confidence. The relationship between don t-cares, power and fanout presents a challenge to the glitch reduction algorithm. Fanout is closely related to interconnect capacitance, and interconnect can represent 60% of total FPGA dynamic power, on average [Shan 02]. Fig. 3.7(a) shows logic signal power consumption versus fanout, averaged across all signals in all circuits. Observe that, as expected, average signal power increases with fanout, due to the increase in capacitance. We also examined, for each signal, the fraction of minterms in its driving LUT that were don t-cares, and averaged this across all signals

38 Chapter 3. Glitch Reduction Using Don t-cares 28 (a) (b) Figure 3.7: (a) Power per signal vs. fanout. (b) Normalized don t-cares per node vs. fanout. Figure 3.8: Fanout splitting. of a given fanout in all circuits. The results are shown in Fig. 3.7(b). While the results are noisy for high fanout (due to a small sample size for such fanouts), we see that, in general, high fanout signals have fewer don t-cares in their driving LUTs than low fanout signals. The rationale for this is that high fanout signals are more likely to be used by at least one of their fanouts, decreasing ODCs for such signals. Essentially, we have two competing trends in that it is desirable to reduce the power of high fanout signals (as they consume significant power), yet such signals exhibit fewer don t-care opportunities.

39 Chapter 3. Glitch Reduction Using Don t-cares 29 Figure 3.9: Stratix III adaptive logic module (ALM) [Alteb] Fanout Splitting Based on the trend of high-fanout signals having fewer don t-cares, it seemed reasonable to examine this as a potential area for improvement. Consider a LUT f 1 with fanout LUTs F O 1...F O n. Suppose that LUTs F O 1...F O n 1 do not care about the value of f 1 when its input is x, but F O n does care about it. Then x is a care for f 1, thereby reducing the amount of don t-care optimization opportunities, even though only one of its fanouts uses it. A possible solution to this problem is to duplicate LUT f 1, creating f 2, and transferring fanout F O n from f 1 to f 2. This would increase the amount of don t-cares on f 1, since x would now be a don t-care. In general, f 1 can be split into two LUTs, f 1 and f 2 (i.e. we redistribute the fanout of f 1, moving some of its fanout to f 2 ). Each LUT now has more don t-care opportunities, since the cares generated by fanouts of f 1 are no longer present in f 2, and vice versa. An example is given in Fig The LUT f 1 has four fanouts which have care set 1 (illustrated by the hatch marks as a subset of the truth table). In other words, if no other fanouts existed besides those four, the overall care set of f 1 would be care set 1. The fifth fanout has care set 2. The overall care set of f 1 is the union of these care sets. By splitting the fanout of f 1 among two new LUTs, f 1 and f 2, we can create two

40 Chapter 3. Glitch Reduction Using Don t-cares 30 Figure 3.10: Dynamic power reduction from fanout splitting. LUTs with smaller cares sets and therefore more don t-care optimization opportunities. However, this incurs a power cost in duplicating the LUT and some routing resources. The fanin routing would have to be duplicated for the new LUT. This would add to the capacitance of these fanin signals. Fortunately, the Stratix III architecture [Alteb] provides us with a way to mitigate this cost. The Adaptive Logic Module (ALM) shown in Fig. 3.9 is essentially a pairing of two LUTs. By co-locating f 1 and f 2 in the same ALM, we can virtually eliminate the cost of routing to an entirely new LUT. This is because the routing to one LUT is shared with the routing to the other. This is a special opportunity offered by the Stratix III architecture. Figure 3.10 shows the dynamic power reduction resulting from fanout splitting. Some circuits could not be placed and routed after fanout splitting due to illegal placement constraints. This is because pairing certain LUTs into a single ALM may cause issues with the compatibility between the LUTs. Unfortunately, the possible power reduction is quite low, aside from a 5% reduction on alu4. Several circuits even show an increase