psasic Timing Generator

Transcription

1 psasic Timing Generator Fukun Tang psasic Design Review July University of Chicago 1

2 Diagram of 40Gs/s Sampling Chip CLOCK (80MHz) IN(1:32) Timing Generator with 2 DLLs interleaved PD CP LF φ1 φ250 PD: Phase Detector CP: Charge Pump LF: Loop Filter CC: Coarse Counter CU: Control Unit CC clr Coarse_Data Vth Ex_trig Sampling Cells Freeze CU CTRL_bus C1 ADC1 C250 ADC250 Rd250 Rd001 ADC_Data 2

3 Requirements of Timing Generator 80MHz input clock. 125 sampling control signals 50ps delay time per cell. Delay tuning range of delay >10% for DLL in next version. 50% duty-cycle (If we can) True differential (If we can) 1.2V Voltage 3

4 Principle of Timing Generator Input Clock: 80MHz (T=12.5ns) Output clock phases: 125/Cycle Time delay per phase: 50ps Voltage controlled time delay φ1 φ125 Clock (80MHz) VCp VCn 50ps Not scaled timing diagram 4

5 Track-and and-hold Timing & Sampling Bandwidth Analog input pulse: Tr=Tf=Tw=100ps Rt Switches of half a switch-chain are sequentially on for tracking, the rest of switches are sequentially off for holding. φ1 φ2 φ1 φ2 φ track hold φ125 φ1-φ125 In Rt Cin Rs Out Cs Analog Bandwidth is determined by a simplified 2-pole system Sampled Pulse 5

6 Current Starved Single-ended ended Voltage-Controlled Delay Cell Driver/buffer To sampling switch To next delay cell A Single Delay Cell VCDL stage Restoration stage 6

7 VCDL Simulation Results (125 Cells) 7

8 Phase Outputs from cell-116 to cell-124 8

9 Cell Layout Single delay cell 4 of 125 cells 8 x 15 microns 1.2mm x 15 microns 9

10 Voltage-Delay (V-D) Chart Delay with post layout is 30% longer than schematic simulation!!! Post Layout Simulation 10Gsps: Delay time 13.9Gsps: Schematic Simulation Control Voltage 10

11 Discussion of Sampling Window Sampling window and input bandwidth. Minimum sampling window and sampling time constant Sampling window control logic 11

12 Sampling Window and Analog Input Bandwidth Die Package pin Rt Analog bandwidth can be modeled as a simplified 2-pole system In Rt Cin Rs Out Cs Cin=Cpkg + Cpad + Csw_on_all + Csw_off_all Cs 12

13 Minimum Sampling Window and Sampling Time Constant Sampling time constant (RonCs( RonCs) Switch on-resistance (Ron) Minimum sampling window: (Tw_min)= 2.2RonCs Ron Δt If Ron = 4k, C = 40f. RonCs = 160ps Tw_min = 2.2RonCs = 352ps 7 sampling steps (50ps each) Assuming 2Tw_min used, then Tw should be set at lest 14 sampling steps (700ps). Δt 13

14 Window Control Logic NAND gate: A sample 14-input and gate can be used to set sampling window. ---disadvantage: Two many stages of circuitry to make AND14, each tap t have to drive 14 loads φn Φn+14 (2) dff: -- disadvantage: too much layout area used. φn Φn+14 CK R φn Φn+14 Tw 14

15 Summary Schematic and post layout simulations have been done. Post layout simulation showed a sampling rate of 10Gsps to 14Gsps can be achieved without interleaving. Same VCDL cell has been used for 2-GHz 2 voltage controlled ring oscillator (see Emilien s talk). 125-cell schematic and layout blocks are available for top-level design. 15

16 Thank you for your review 16

17 Backup Slides Why Not Differential VCDL? 17

18 Schematic and Layout of Replica Diff. Delay Cell A Single Replica Differential Delay Cell Restoration Dummy Load 18

19 Schematic Simulation for 125 Cells V-D Chart Delay time 20Gsps: 50pS Controlled Voltage 19

20 Post Layout Simulation (Never Work!) DL1 DL2 DLn DL125 50ps Fail Fail Unequaled parasitic capacitance in layout causes delay difference in positive and negative nodes of each cell. If accumulated delay difference is greater than 50ps in a chain of 125 cells, the delay chain went to malfunction. There is no way to tune the layout for such tight matching! 20

21 Backup Slide-2 Input Analog Bandwidth, Sampling Time Constant and Minimum Sampling Window 21

22 Modeling of Input Bus and Sampling Cells With Sampling Window of 3.25ns (64 cells) Cin 64 cells in tracking, (3.2ns sampling window). R64=4k/64 = 62 ohm C64 = 4k * 40f = 2.5pF Cin = 2pF Terminator = 50 ohms Cin=Cpkg + Cpad + Csw_on_all + Csw_off_all 22

23 Modeling of Input Bus and Sampling Cells With Sampling Window of 640ps (13 cells) Cin 13 cells in tracking (640ps sampling window). R64 = 4k/13 = 300 ohm C64 = 13 * 40f = 0.5pF Cin = 2pF Terminator = 50 ohms Cin=Cpkg + Cpad + Csw_on_all + Csw_off_all 23

24 Comparison of Simulation Results 640ps window 3.2ns window Input Step Current 508ps 765ps Sampling Cell Step Response Input Bus Step Response 24

25 From Step Response Simulations: Sampling cell with 640ps sampling window, it has a rise time (10%-90%) of 508ps, equivalent to an analog bandwidth of 689MHz. Sampling with 3.2ns sampling window, it has a rise time of 765ps, equivalent to an analog bandwidth of 457MHz. We need simulate our circuits to evaluate our design for input analog bandwidth 25