Solar Power for Small Hall
|
|
|
- Adelia Lee
- 6 years ago
- Views:
Transcription
1 Solar Power for Small Hall [image from The university is interested in installing a Solar Power Generating Facility on the roof of Small Hall. Project not official at university level yet, but SPS + Dept. are kickstarting project: Meeting Tuesday this week at 6:30pm in Small Hall conference room. Determine which solar technology to use. How much electrical power can we expect to get. Final budget for project is not finalized. Paid for from Green Fees (i.e. your money). Installation will occur during or immediately after renovation of Small Hall.
2 VMEC Summer Internship Program Virginia Micro-Electronics Consortium summer program: May-August, weeks of paid research work. Juniors and Seniors Participating universities: W&M, UVA, VirginiaTech, VCU, ODU, GMU, Virginia. Military. Inst. Participating companies: Micron Technology, BAE Systems. DEADLINE: October 31, Website:
3 Outline: 1. Timing noise Flip-Flops Flops Signal races, glitches FPGA example ( assign bad) 2. Synchronous circuits and memory Logic gate example 3. Flip-Flop Flop memory RS-latch example 4. D and JK flip-flops flops Flip-flops in FPGAs 5. Synchronous circuit design with FPGAs FPGA example ( always good). Parallel circuit design with FPGAs.
4 Timing noise Amplitude Noise A digital circuit is very immune to amplitude noise, since it can only have two values (Low or High, True or False, 0 or 1). Digital electronics circuits typically have error rates smaller than 1 part in 10 9 (no error correction). Timing Noise Just like an analog circuit, a digital circuit can experience timing noise. Fortunately, good clocks are cheap and easily available, and a good design will eliminate the effects of timing noise. Timing issues/errors can easily produce amplitude noise (bit errors).
5 Signal Race The timing delays produced by wires and logic gates can produce unwanted (illogical) outputs. Example: 3-input NAND gate A AB B C Y A B C Time ideal Y
6 Signal Race The timing delays produced by wires and logic gates can produce unwanted (illogical) outputs. Example: 3-input NAND gate A AB B C Y A B C AB resulting Y 2x gate delay Time If gate delays are too long output pulse could disappear
7 Signal Race The timing delays produced by wires and logic gates can produce unwanted (illogical) outputs. Example: 3-input NAND gate A AB B C Y A B C AB actual Y 2x gate delay Time Pulse is shorter than expected and delayed
8 A B B A Signal Race with Glitch AB AB [diagram courtesy of Altera Inc.] Y XOR A B Y L L L L H H H L H H H L A B A B Inverter delay Inverter delay + component differences Time resulting resulting resulting AB AB Y [Figure adapted from Principles of Electronics: Analog & Digital by L. R. Fortney]
9 A B B A Signal Race with Glitch AB AB [diagram courtesy of Altera Inc.] Y XOR A B Y L L L L H H H L H H H L A B A B Time real real real AB AB Y [Figure adapted from Principles of Electronics: Analog & Digital by L. R. Fortney]
10 Glitches with FPGAs Quartus II will simulate glitches glitches
11 Asynchronous Design Asynchronous design requires very careful attention to signal delays to avoid producing glitches and other spurious signals. Glitches will produce false data and can produce very wrong results e.g. a glitch on the most-significant-bit will produce a factor of 2 error. Asynchronous design design can can produce very very fast fast digital digital circuits, but but is is generally avoided due due to to more more difficult difficult design. design.
12 Synchronous Design The use of memory and a clock can eliminate signal races and glitches. A B AB flip flop clock C in flip flop out Y clock Basic flip-flop flop operation The flip-flop will record and output the value at the input if the clock is HIGH. If the clock goes LOW, then the flip-flop does not change its value or output. Glitches are eliminated if 1. The clock HIGH and LOW times are longer than any gate delays. 2. The inputs are synchronized to the clock.
13 A B C Synchronous Timing AB flip flop flip flop clock Y clock clock A B C Flip-flop AB Flip-flop C resulting Y 2x gate delay Time Guaranteed minimum signal pulse
14 D-type Edge-Triggered Flip-Flop Flop Generally, the flip-flop changes state on a clock signal edge, not the level. The flip-flop takes the value just before the clock edge. clock D t s t h S or PRE Q input D Q output For 74LS74: minimum t s = 20 ns minimum t h = 5 ns clock Q R or CLR [Texas Instruments 74LS74 flip-flop datasheet] Note: A flip-flop saves information (i.e. 1 bit); it does not modify it.
15 D-type Edge-Triggered Flip-Flop Flop Generally, the flip-flop changes state on a clock signal edge, not the level. The flip-flop takes the value just before the clock edge. clock D t s t h rising-edge trigger S or PRE Q input D Q output For 74LS74: minimum t s = 20 ns minimum t h = 5 ns clock Q R or CLR [Texas Instruments 74LS74 flip-flop datasheet] Note: A flip-flop saves information (i.e. 1 bit); it does not modify it.
16 A B C clock Synchronous Timing (revisited) AB flip flop flip flop clock clock Y A B C Flip-flop AB Time Flip-flop C resulting Y
17 How does a flip-flop flop work? Basic flip-flop: the SR latch Logic table Q 0 = value before S&R changes R = 0 & S = 0: S = 0 & assume Q = 0 Q = 1. S = 0 & assume Q = 1 Q = 1. R = 0 & assume Q = 0 Q = 1. R = 0 & assume Q = 1 Q = 1.
18 How does a flip-flop flop work? Basic flip-flop: the SR latch Logic table Q 0 = value before S&R changes R = 0 & S = 0: S = 0 & assume Q = 0 Q = 1. S = 0 & assume Q = 1 Q = 1. R = 0 & assume Q = 0 Q = 1. R = 0 & assume Q = 1 Q = 1. consistent R=0 & S=0 Q=1 & Q=1
19 How does a flip-flop flop work? Basic flip-flop: the SR latch Logic table Q 0 = value before S&R changes R = 0 & S = 1: S = 1 & assume Q = 0 Q = 1. S = 1 & assume Q = 1 Q = 0. R = 0 & assume Q = 0 Q = 1. R = 0 & assume Q = 1 Q = 1.
20 How does a flip-flop flop work? Basic flip-flop: the SR latch Logic table Q 0 = value before S&R changes R = 0 & S = 1: S = 1 & assume Q = 0 Q = 1. S = 1 & assume Q = 1 Q = 0. R = 0 & assume Q = 0 Q = 1. R = 0 & assume Q = 1 Q = 1. consistent R=0 & S=1 Q=0 & Q=1
21 How does a flip-flop flop work? Basic flip-flop: the SR latch Logic table Q 0 = value before S&R changes R = 1 & S = 0: The opposite of R = 0 & S = 1 by symmetry.
22 How does a flip-flop flop work? Basic flip-flop: the SR latch Logic table Q 0 = value before S&R changes R = 1 & S = 1: S = 1 & assume Q = 0 Q = 1. S = 1 & assume Q = 1 Q = 0. R = 1 & assume Q = 0 Q = 1. R = 1 & assume Q = 1 Q = 0.
23 How does a flip-flop flop work? Basic flip-flop: the SR latch Logic table Q 0 = value before S&R changes R = 1 & S = 1: S = 1 & assume Q = 0 Q = 1. S = 1 & assume Q = 1 Q = 0. R = 1 & assume Q = 0 Q = 1. R = 1 & assume Q = 1 Q = 0. consistent R=1 & S=1 Q=1 & Q=0 consistent R=1 & S=1 Q=0 & Q=1
24 How does a flip-flop flop work? Basic flip-flop: the SR latch Logic table Q 0 = value before S&R changes R = 1 & S = 1: S = 1 & assume Q = 0 Q = 1. S = 1 & assume Q = 1 Q = 0. R = 1 & assume Q = 0 Q = 1. R = 1 & assume Q = 1 Q = 0. consistent R=1 & S=1 Q=1 & Q=0 consistent R=1 & S=1 Q=0 & Q=1 Two settings are possible i.e. flip-flop flop keeps its state.
25 SR Latch Switch Debouncer SR latch flip-flops are not used much for memory, but they are used for debouncing switches. Switch Bounce: When a switch is toggled it will not go smoothly from HIGH to LOW, or vice versa. Volts bouncing switch Volts debounced switch time time R +5V R
26 Clocked D-type D Latch S Logic table R Clock Circuit Analysis: C = 1 & D = 1 S = 0 & R = 1. C = 1 & D = 0 S = 1 & R = 0. C = 0 & D = 1 S = 1 & R = 1. C = 0 & D = 0 S = 1 & R = 1.
27 Clocked D-type D Latch S Logic table R Clock Circuit Analysis: C = 1 & D = 1 S = 0 & R = 1. C = 1 & D = 0 S = 1 & R = 0. C = 0 & D = 1 S = 1 & R = 1. C = 0 & D = 0 S = 1 & R = 1. Clock HIGH: D sets the flip-flop state Clock LOW: flip-flop state is locked
28 Clocked D-type D Latch input D Q output Logic table clock Q Clock Circuit Analysis: C = 1 & D = 1 S = 0 & R = 1. C = 1 & D = 0 S = 1 & R = 0. C = 0 & D = 1 S = 1 & R = 1. C = 0 & D = 0 S = 1 & R = 1. Clock HIGH: D sets the flip-flop state Clock LOW: flip-flop state is locked
29 Master-Slave D-type D Flip-Flop Flop Note: The flip-flop triggers on a the falling edge of the clock.
30 74LS74 D-type D edge-triggered flip-flop flop [Texas Instruments 74LS74 flip-flop datasheet] Both PRE and CLR behave like S and R inputs, respectively, on the SR latch. IMPORTANT: Both PRE and CLR must be high for normal D-type operation. Note: The flip-flop triggers on the rising edge of the clock.
31 74LS74 D-type D edge-triggered flip-flop flop input D PRE Q output [Texas Instruments 74LS74 flip-flop datasheet] clock CLR Q Both PRE and CLR behave like S and R inputs, respectively, on the SR latch. IMPORTANT: Both PRE and CLR must be high for normal D-type operation. Note: The flip-flop triggers on the rising edge of the clock.
32 JK-type flip-flop flop Logic table for clock falling edge input J Q output J K Q n+1 clock input K C Q 0 0 Q n Q n JK-type flip-flops are used in counters.
33 Flip-flops in FPGAs Architecture of a single Logic Element inputs clock signals LUT CLOCK triggers Memory (a few bits) global local outputs feedback Frequently a D-type D Flip-Flop Flop FPGAs are already set-up for synchronous circuit designs
34 Flip-flops in FPGAs Architecture of a single Logic Element inputs clock signals LUT CLOCK triggers Memory (a few bits) global local outputs feedback Frequently a D-type D Flip-Flop Flop FPGAs are already set-up for synchronous circuit designs
35 Synchronous programming in Verilog (I)
36 Synchronous programming in Verilog (I) Clock variable output register (i.e. flip-flop flop memory )
37 Synchronous programming in Verilog (I) Clock variable output register (i.e. flip-flop flop memory ) Read as as always at at the positive clock edge do do the following always is is the the core core command for for synchronous programming, it it should should be be used used as as frequently as as possible. assign should should be be used used as as little little as as possible. It It is is only only useful useful for for DCtype type signals (signals that that don t don t t change). DC-
38 Synchronous programming in Verilog (II) Quartus II circuit simulation
39 Synchronous programming in Verilog (II) Quartus II circuit simulation Clock Line No more glitches
40 How did the FPGA implement the circuit? Tools > Netlists > Technology Map Viewer
41 How did the FPGA implement the circuit? Tools > Netlists > Technology Map Viewer D-type edge-triggered flip-flops flops
42 Always use always _ A. Stummer, U. of Toronto.
43 Parallel programming in Verilog The always structure is used for exploiting the parallel processing features of the FPGA. Parallel processing must almost always be synchronous if several processes exchange data. Parallel and Sequential processing examples: Sequential (negedge clock) begin a = b; c = a; end Parallel always@ (negedge clock) begin a <= b; c <= a; end
44 Parallel programming in Verilog The always structure is used for exploiting the parallel processing features of the FPGA. Parallel processing must almost always be synchronous if several processes exchange data. Parallel and Sequential processing examples: Sequential (negedge clock) begin a = b; c = a; end Parallel always@ (negedge clock) begin a <= b; c <= a; end executed simultaneously c = b a = b c = a (previous value)
YEDITEPE UNIVERSITY DEPARTMENT OF COMPUTER ENGINEERING. EXPERIMENT VIII: FLIP-FLOPS, COUNTERS 2014 Fall
YEDITEPE UNIVERSITY DEPARTMENT OF COMPUTER ENGINEERING EXPERIMENT VIII: FLIP-FLOPS, COUNTERS 2014 Fall Objective: - Dealing with the operation of simple sequential devices. Learning invalid condition in
DIGITAL CIRCUIT COMBINATORIAL LOGIC
DIGITAL CIRCUIT COMBINATORIAL LOGIC Logic levels: one zero true false high low CMOS logic levels: 1 => 0.7 V DD 0.4 V DD = noise margin 0 =< 0.3 V DD Positive logic: high = 1 = true low = 0 = false Negative
Sequential Digital Design. Laboratory Manual. Experiment #3. Flip Flop Storage Elements
The Islamic University of Gaza Engineering Faculty Department of Computer Engineering Spring 2018 ECOM 2022 Khaleel I. Shaheen Sequential Digital Design Laboratory Manual Experiment #3 Flip Flop Storage
Timing Pulses. Important element of laboratory electronics. Pulses can control logical sequences with precise timing.
Timing Pulses Important element of laboratory electronics Pulses can control logical sequences with precise timing. If your detector sees a charged particle or a photon, you might want to signal a clock
RS flip-flop using NOR gate
RS flip-flop using NOR gate Triggering and triggering methods Triggering : Applying train of pulses, to set or reset the memory cell is known as Triggering. Triggering methods:- There are basically two
Lecture 8: Sequential Logic
Lecture 8: Sequential Logic Last lecture discussed how we can use digital electronics to do combinatorial logic we designed circuits that gave an immediate output when presented with a given set of inputs
Experiment 8 Introduction to Latches and Flip-Flops and registers
Experiment 8 Introduction to Latches and Flip-Flops and registers Introduction: The logic circuits that have been used until now were combinational logic circuits since the output of the device depends
EE292: Fundamentals of ECE
EE292: Fundamentals of ECE Fall 2012 TTh 10:00-11:15 SEB 1242 Lecture 23 121120 http://www.ee.unlv.edu/~b1morris/ee292/ 2 Outline Review Combinatorial Logic Sequential Logic 3 Combinatorial Logic Circuits
DEPARTMENT OF ELECTRICAL &ELECTRONICS ENGINEERING DIGITAL DESIGN
DEPARTMENT OF ELECTRICAL &ELECTRONICS ENGINEERING DIGITAL DESIGN Assoc. Prof. Dr. Burak Kelleci Spring 2018 OUTLINE Synchronous Logic Circuits Latch Flip-Flop Timing Counters Shift Register Synchronous
DIGITAL CIRCUIT LOGIC UNIT 11: SEQUENTIAL CIRCUITS (LATCHES AND FLIP-FLOPS)
DIGITAL CIRCUIT LOGIC UNIT 11: SEQUENTIAL CIRCUITS (LATCHES AND FLIP-FLOPS) 1 iclicker Question 16 What should be the MUX inputs to implement the following function? (4 minutes) f A, B, C = m(0,2,5,6,7)
Sequential Logic and Clocked Circuits
Sequential Logic and Clocked Circuits Clock or Timing Device Input Variables State or Memory Element Combinational Logic Elements From combinational logic, we move on to sequential logic. Sequential logic
COE 202: Digital Logic Design Sequential Circuits Part 1. Dr. Ahmad Almulhem ahmadsm AT kfupm Phone: Office:
COE 202: Digital Logic Design Sequential Circuits Part 1 Dr. Ahmad Almulhem Email: ahmadsm AT kfupm Phone: 860-7554 Office: 22-324 Objectives Sequential Circuits Memory Elements Latches Flip-Flops Combinational
Digital Logic Design Sequential Circuits. Dr. Basem ElHalawany
Digital Logic Design Sequential Circuits Dr. Basem ElHalawany Combinational vs Sequential inputs X Combinational Circuits outputs Z A combinational circuit: At any time, outputs depends only on inputs
EMT 125 Digital Electronic Principles I CHAPTER 6 : FLIP-FLOP
EMT 125 Digital Electronic Principles I CHAPTER 6 : FLIP-FLOP 1 Chapter Overview Latches Gated Latches Edge-triggered flip-flops Master-slave flip-flops Flip-flop operating characteristics Flip-flop applications
Logic Design. Flip Flops, Registers and Counters
Logic Design Flip Flops, Registers and Counters Introduction Combinational circuits: value of each output depends only on the values of inputs Sequential Circuits: values of outputs depend on inputs and
Chapter 6 Digital Circuit 6-5 Department of Mechanical Engineering
MEMS1082 Chapter 6 Digital Circuit 6-5 General digital system D Flip-Flops, The D flip-flop is a modification of the clocked SR flip-flop. The D input goes directly into the S input and the complement
Unit 11. Latches and Flip-Flops
Unit 11 Latches and Flip-Flops 1 Combinational Circuits A combinational circuit consists of logic gates whose outputs, at any time, are determined by combining the values of the inputs. For n input variables,
(CSC-3501) Lecture 7 (07 Feb 2008) Seung-Jong Park (Jay) CSC S.J. Park. Announcement
Seung-Jong Park (Jay) http://www.csc.lsu.edu/~sjpark Computer Architecture (CSC-3501) Lecture 7 (07 Feb 2008) 1 Announcement 2 1 Combinational vs. Sequential Logic Combinational Logic Memoryless Outputs
LAB #4 SEQUENTIAL LOGIC CIRCUIT
LAB #4 SEQUENTIAL LOGIC CIRCUIT OBJECTIVES 1. To learn how basic sequential logic circuit works 2. To test and investigate the operation of various latch and flip flop circuits INTRODUCTIONS Sequential
Introduction to Sequential Circuits
Introduction to Sequential Circuits COE 202 Digital Logic Design Dr. Muhamed Mudawar King Fahd University of Petroleum and Minerals Presentation Outline Introduction to Sequential Circuits Synchronous
LATCHES & FLIP-FLOP. Chapter 7
LATCHES & FLIP-FLOP Chapter 7 INTRODUCTION Latch and flip flops are categorized as bistable devices which have two stable states,called SET and RESET. They can retain either of this states indefinitely
Unit 9 Latches and Flip-Flops. Dept. of Electrical and Computer Eng., NCTU 1
Unit 9 Latches and Flip-Flops Dept. of Electrical and Computer Eng., NCTU 1 9.1 Introduction Dept. of Electrical and Computer Eng., NCTU 2 What is the characteristic of sequential circuits in contrast
Final Exam review: chapter 4 and 5. Supplement 3 and 4
Final Exam review: chapter 4 and 5. Supplement 3 and 4 1. A new type of synchronous flip-flop has the following characteristic table. Find the corresponding excitation table with don t cares used as much
RS flip-flop using NOR gate
RS flip-flop using NOR gate Triggering and triggering methods Triggering : Applying train of pulses, to set or reset the memory cell is known as Triggering. Triggering methods:- There are basically two
cascading flip-flops for proper operation clock skew Hardware description languages and sequential logic
equential logic equential circuits simple circuits with feedback latches edge-triggered flip-flops Timing methodologies cascading flip-flops for proper operation clock skew Basic registers shift registers
Digital Fundamentals. Lab 5 Latches & Flip-Flops CETT Name: Date:
Richland College School of Engineering & Technology Rev. 0 B. Donham Rev. 1 (7/2003) J. Horne Rev. 2 (1/2008) J. Bradbury Rev. 3 (7/2015) J. Bradbury Digital Fundamentals CETT 1425 Lab 5 Latches & Flip-Flops
DIGITAL SYSTEM FUNDAMENTALS (ECE421) DIGITAL ELECTRONICS FUNDAMENTAL (ECE422) LATCHES and FLIP-FLOPS
COURSE / CODE DIGITAL SYSTEM FUNDAMENTALS (ECE421) DIGITAL ELECTRONICS FUNDAMENTAL (ECE422) LATCHES and FLIP-FLOPS In the same way that logic gates are the building blocks of combinatorial circuits, latches
Physics 323. Experiment # 10 - Digital Circuits
Physics 323 Experiment # 10 - Digital Circuits Purpose This is a brief introduction to digital (logic) circuits using both combinational and sequential logic. The basic building blocks will be the Transistor
CPS311 Lecture: Sequential Circuits
CPS311 Lecture: Sequential Circuits Last revised August 4, 2015 Objectives: 1. To introduce asynchronous and synchronous flip-flops (latches and pulsetriggered, plus asynchronous preset/clear) 2. To introduce
Chapter. Synchronous Sequential Circuits
Chapter 5 Synchronous Sequential Circuits Logic Circuits- Review Logic Circuits 2 Combinational Circuits Consists of logic gates whose outputs are determined from the current combination of inputs. Performs
Chapter 5 Synchronous Sequential Logic
Chapter 5 Synchronous Sequential Logic Chih-Tsun Huang ( 黃稚存 ) http://nthucad.cs.nthu.edu.tw/~cthuang/ Department of Computer Science National Tsing Hua University Outline Introduction Storage Elements:
More on Flip-Flops Digital Design and Computer Architecture: ARM Edition 2015 Chapter 3 <98> 98
More on Flip-Flops Digital Design and Computer Architecture: ARM Edition 2015 Chapter 3 98 Review: Bit Storage SR latch S (set) Q R (reset) Level-sensitive SR latch S S1 C R R1 Q D C S R D latch Q
Topics of Discussion
Digital Circuits II VHDL for Digital System Design Practical Considerations References: 1) Text Book: Digital Electronics, 9 th editon, by William Kleitz, published by Pearson Spring 2015 Paul I-Hai Lin,
DIGITAL ELECTRONICS MCQs
DIGITAL ELECTRONICS MCQs 1. A 8-bit serial in / parallel out shift register contains the value 8, clock signal(s) will be required to shift the value completely out of the register. A. 1 B. 2 C. 4 D. 8
Computer Science 324 Computer Architecture Mount Holyoke College Fall Topic Notes: Sequential Circuits
Computer Science 324 Computer Architecture Mount Holyoke College Fall 2007 opic Notes: Sequential Circuits Let s think about how life can be bad for a circuit. Edge Detection Consider this one: What is
Chapter 8 Sequential Circuits
Philadelphia University Faculty of Information Technology Department of Computer Science Computer Logic Design By 1 Chapter 8 Sequential Circuits 1 Classification of Combinational Logic 3 Sequential circuits
INTRODUCTION TO SEQUENTIAL CIRCUITS
NOTE: Explanation Refer Class Notes Digital Circuits(15EECC203) INTRODUCTION TO SEQUENTIAL CIRCUITS by Nagaraj Vannal, Asst.Professor, School of Electronics Engineering, K.L.E. Technological University,
CHAPTER 1 LATCHES & FLIP-FLOPS
CHAPTER 1 LATCHES & FLIP-FLOPS 1 Outcome After learning this chapter, student should be able to; Recognize the difference between latches and flipflops Analyze the operation of the flip flop Draw the output
Flip-Flops and Sequential Circuit Design
Flip-Flops and Sequential Circuit Design ECE 52 Summer 29 Reading ssignment Brown and Vranesic 7 Flip-Flops, Registers, Counters and a Simple Processor 7.5 T Flip-Flop 7.5. Configurable Flip-Flops 7.6
Flip-Flops. Because of this the state of the latch may keep changing in circuits with feedback as long as the clock pulse remains active.
Flip-Flops Objectives The objectives of this lesson are to study: 1. Latches versus Flip-Flops 2. Master-Slave Flip-Flops 3. Timing Analysis of Master-Slave Flip-Flops 4. Different Types of Master-Slave
Rangkaian Sekuensial. Flip-flop
Rangkaian Sekuensial Rangkaian Sekuensial Flip-flop Combinational versus Sequential Functions Logic functions are categorized as being either combinational (sometimes referred to as combinatorial) or sequential.
3 Flip-Flops. The latch is a logic block that has 2 stable states (0) or (1). The RS latch can be forced to hold a 1 when the Set line is asserted.
3 Flip-Flops Flip-flops and latches are digital memory circuits that can remain in the state in which they were set even after the input signals have been removed. This means that the circuits have a memory
Sequential Design Basics
Sequential Design Basics Lecture 2 topics A review of devices that hold state A review of Latches A review of Flip-Flops Unit of text Set-Reset Latch/Flip-Flops/D latch/ Edge triggered D Flip-Flop 8/22/22
CHAPTER 11 LATCHES AND FLIP-FLOPS
CHAPTER 11 1/25 LATCHES AND FLIP-FLOPS This chapter in the book includes: Objectives Study Guide 11.1 Introduction 11.2 Set-Reset Latch 11.3 Gated D Latch 11.4 Edge-Triggered D Flip-Flop 11.5 S-R Flip-Flop
Chapter 2. Digital Circuits
Chapter 2. Digital Circuits Logic gates Flip-flops FF registers IC registers Data bus Encoders/Decoders Multiplexers Troubleshooting digital circuits Most contents of this chapter were covered in 88-217
Logic and Computer Design Fundamentals. Chapter 7. Registers and Counters
Logic and Computer Design Fundamentals Chapter 7 Registers and Counters Registers Register a collection of binary storage elements In theory, a register is sequential logic which can be defined by a state
Computer Science 324 Computer Architecture Mount Holyoke College Fall Topic Notes: Sequential Circuits
Computer Science 324 Computer Architecture Mount Holyoke College Fall 2009 opic Notes: Sequential Circuits Let s think about how life can be bad for a circuit. Edge Detection Consider this one: What is
MODEL QUESTIONS WITH ANSWERS THIRD SEMESTER B.TECH DEGREE EXAMINATION DECEMBER CS 203: Switching Theory and Logic Design. Time: 3 Hrs Marks: 100
MODEL QUESTIONS WITH ANSWERS THIRD SEMESTER B.TECH DEGREE EXAMINATION DECEMBER 2016 CS 203: Switching Theory and Logic Design Time: 3 Hrs Marks: 100 PART A ( Answer All Questions Each carries 3 Marks )
Switching Circuits & Logic Design
Switching Circuits & Logic Design Jie-Hong oland Jiang 江介宏 Department of Electrical Engineering National Taiwan University Fall 22 Latches and Flip-Flops http://www3.niaid.nih.gov/topics/malaria/lifecycle.htm
AIM: To study and verify the truth table of logic gates
EXPERIMENT: 1- LOGIC GATES AIM: To study and verify the truth table of logic gates LEARNING OBJECTIVE: Identify various Logic gates and their output. COMPONENTS REQUIRED: KL-31001 Digital Logic Lab( Main
MODU LE DAY. Class-A, B, AB and C amplifiers - basic concepts, power, efficiency Basic concepts of Feedback and Oscillation. Day 1
DAY MODU LE TOPIC QUESTIONS Day 1 Day 2 Day 3 Day 4 I Class-A, B, AB and C amplifiers - basic concepts, power, efficiency Basic concepts of Feedback and Oscillation Phase Shift Wein Bridge oscillators.
Introduction. NAND Gate Latch. Digital Logic Design 1 FLIP-FLOP. Digital Logic Design 1
2007 Introduction BK TP.HCM FLIP-FLOP So far we have seen Combinational Logic The output(s) depends only on the current values of the input variables Here we will look at Sequential Logic circuits The
Sequential Circuits. Output depends only and immediately on the inputs Have no memory (dependence on past values of the inputs)
Sequential Circuits Combinational circuits Output depends only and immediately on the inputs Have no memory (dependence on past values of the inputs) Sequential circuits Combination circuits with memory
LAB 7. Latches & Flip Flops
بسام عب د الكريم جاد هللا النبريص Bass am Ak J Alnabr iss Islamic University of Gaza Faculty of Engineering Computer Engineering Dept. Digital Design Lab : ECOM 2112 Fall 2016 Eng. Bassam Nabriss LAB 7
Other Flip-Flops. Lecture 27 1
Other Flip-Flops Other types of flip-flops can be constructed by using the D flip-flop and external logic. Two flip-flops less widely used in the design of digital systems are the JK and T flip-flops.
D Latch (Transparent Latch)
D Latch (Transparent Latch) -One way to eliminate the undesirable condition of the indeterminate state in the SR latch is to ensure that inputs S and R are never equal to 1 at the same time. This is done
ELCT201: DIGITAL LOGIC DESIGN
ELCT201: DIGITAL LOGIC DESIGN Dr. Eng. Haitham Omran, haitham.omran@guc.edu.eg Dr. Eng. Wassim Alexan, wassim.joseph@guc.edu.eg Lecture 7 Following the slides of Dr. Ahmed H. Madian محرم 1439 ه Winter
ENGN3213 Digital Systems and Microprocessors Sequential Circuits
ENGN3213 Digital Systems and Microprocessors Sequential Circuits 1 ENGN3213: Digital Systems and Microprocessors L#9-10 Why have sequential circuits? Sequential systems are time sequential devices - many
Logic. Andrew Mark Allen March 4, 2012
Logic Andrew Mark Allen - 05370299 March 4, 2012 Abstract NAND gates and inverters were used to construct several different logic gates whose operations were investigate under various inputs. Then the
Flip-Flops and Related Devices. Wen-Hung Liao, Ph.D. 4/11/2001
Flip-Flops and Related Devices Wen-Hung Liao, Ph.D. 4/11/2001 Objectives Recognize the various IEEE/ANSI flip-flop symbols. Use state transition diagrams to describe counter operation. Use flip-flops in
Asynchronous (Ripple) Counters
Circuits for counting events are frequently used in computers and other digital systems. Since a counter circuit must remember its past states, it has to possess memory. The chapter about flip-flops introduced
Clocks. Sequential Logic. A clock is a free-running signal with a cycle time.
Clocks A clock is a free-running signal with a cycle time. A clock may be either high or low, and alternates between the two states. The length of time the clock is high before changing states is its high
Sequential Logic Circuits
Sequential Logic Circuits By Dr. M. Hebaishy Digital Logic Design Ch- Rem.!) Types of Logic Circuits Combinational Logic Memoryless Outputs determined by current values of inputs Sequential Logic Has memory
Last time, we saw how latches can be used as memory in a circuit
Flip-Flops Last time, we saw how latches can be used as memory in a circuit Latches introduce new problems: We need to know when to enable a latch We also need to quickly disable a latch In other words,
Digital Fundamentals: A Systems Approach
Digital Fundamentals: A Systems Approach Counters Chapter 8 A System: Digital Clock Digital Clock: Counter Logic Diagram Digital Clock: Hours Counter & Decoders Finite State Machines Moore machine: One
Chapter 11 Latches and Flip-Flops
Chapter 11 Latches and Flip-Flops SKEE1223 igital Electronics Mun im/arif/izam FKE, Universiti Teknologi Malaysia ecember 8, 2015 Types of Logic Circuits Combinational logic: Output depends solely on the
SEMESTER ONE EXAMINATIONS 2002
SEMESTER ONE EXAMINATIONS 2002 EE101 Digital Electronics Solutions Question 1. An assembly line has 3 failsafe sensors and 1 emergency shutdown switch. The Line should keep moving unless any of the following
Name: Date: Suggested Reading Chapter 7, Digital Systems, Principals and Applications; Tocci
Richland College Engineering Technology Rev. 0 B. Donham Rev. 1 (7/2003) J. Horne Rev. 2 (1/2008) J. Bradbury Digital Fundamentals CETT 1425 Lab 7 Asynchronous Ripple Counters Name: Date: Objectives: To
Chapter 5 Flip-Flops and Related Devices
Chapter 5 Flip-Flops and Related Devices Chapter 5 Objectives Selected areas covered in this chapter: Constructing/analyzing operation of latch flip-flops made from NAND or NOR gates. Differences of synchronous/asynchronous
Synchronous Sequential Logic. Chapter 5
Synchronous Sequential Logic Chapter 5 5-1 Introduction Combinational circuits contains no memory elements the outputs depends on the inputs Synchronous Sequential Logic 5-2 5-2 Sequential Circuits Sequential
Review of Flip-Flop. Divya Aggarwal. Student, Department of Physics and Astro-Physics, University of Delhi, New Delhi. their state.
pp. 4-9 Krishi Sanskriti Publications http://www.krishisanskriti.org/jbaer.html Review of Flip-Flop Divya Aggarwal Student, Department of Physics and Astro-Physics, University of Delhi, New Delhi Abstract:
L14: Quiz Information and Final Project Kickoff. L14: Spring 2004 Introductory Digital Systems Laboratory
L14: Quiz Information and Final Project Kickoff 1 Quiz Quiz Review on Monday, March 29 by TAs 7:30 P.M. to 9:30 P.M. Room 34-101 Quiz will be Closed Book on March 31 st (during class time, Location, Walker
Digital Fundamentals: A Systems Approach
Digital Fundamentals: A Systems Approach Latches, Flip-Flops, and Timers Chapter 6 Traffic Signal Control Traffic Signal Control: State Diagram Traffic Signal Control: Block Diagram Traffic Signal Control:
Chapter 6. Flip-Flops and Simple Flip-Flop Applications
Chapter 6 Flip-Flops and Simple Flip-Flop Applications Basic bistable element It is a circuit having two stable conditions (states). It can be used to store binary symbols. J. C. Huang, 2004 Digital Logic
Name Of The Experiment: Sequential circuit design Latch, Flip-flop and Registers
EEE 304 Experiment No. 07 Name Of The Experiment: Sequential circuit design Latch, Flip-flop and Registers Important: Submit your Prelab at the beginning of the lab. Prelab 1: Construct a S-R Latch and
EET2411 DIGITAL ELECTRONICS
5-8 Clocked D Flip-FlopFlop One data input. The output changes to the value of the input at either the positive going or negative going clock trigger. May be implemented with a J-K FF by tying the J input
Chapter 5 Sequential Circuits
Logic and Computer Design Fundamentals Chapter 5 Sequential Circuits Part 2 Sequential Circuit Design Charles Kime & Thomas Kaminski 28 Pearson Education, Inc. (Hyperlinks are active in View Show mode)
SEQUENTIAL LOGIC. Satish Chandra Assistant Professor Department of Physics P P N College, Kanpur
SEQUENTIAL LOGIC Satish Chandra Assistant Professor Department of Physics P P N College, Kanpur www.satish0402.weebly.com OSCILLATORS Oscillators is an amplifier which derives its input from output. Oscillators
Lecture 7: Sequential Networks
Lecture 7: Sequential Networks CSE 14: Components and Design Techniques for Digital Systems Spring 214 CK Cheng, Diba Mirza Dept. of Computer Science and Engineering University of California, San Diego
NH 67, Karur Trichy Highways, Puliyur C.F, Karur District UNIT-III SEQUENTIAL CIRCUITS
NH 67, Karur Trichy Highways, Puliyur C.F, 639 114 Karur District DEPARTMENT OF ELETRONICS AND COMMUNICATION ENGINEERING COURSE NOTES SUBJECT: DIGITAL ELECTRONICS CLASS: II YEAR ECE SUBJECT CODE: EC2203
REPEAT EXAMINATIONS 2002
REPEAT EXAMINATIONS 2002 EE101 Digital Electronics Solutions Question 1. An engine has 4 fail-safe sensors. The engine should keep running unless any of the following conditions arise: o If sensor 2 is
FE REVIEW LOGIC. The AND gate. The OR gate A B AB A B A B 0 1 1
FE REVIEW LOGIC The AD gate f A, B AB The AD gates output will achieve its active state, ACTIVE HIGH, when BOTH of its inputs achieve their active state, ACTIVE E HIGH. A B AB f ( A, B) AB m (3) The OR
UNIT III. Combinational Circuit- Block Diagram. Sequential Circuit- Block Diagram
UNIT III INTRODUCTION In combinational logic circuits, the outputs at any instant of time depend only on the input signals present at that time. For a change in input, the output occurs immediately. Combinational
Unit-5 Sequential Circuits - 1
Unit-5 Sequential Circuits - 1 1. With the help of block diagram, explain the working of a JK Master-Slave flip flop. 2. Differentiate between combinational circuit and sequential circuit. 3. Explain Schmitt
A clock is a free-running signal with a cycle time. A clock may be either high or low, and alternates between the two states.
Clocks A clock is a free-running signal with a cycle time. A clock may be either high or low, and alternates between the two states. 1 The length of time the clock is high before changing states is its
The outputs are formed by a combinational logic function of the inputs to the circuit or the values stored in the flip-flops (or both).
1 The outputs are formed by a combinational logic function of the inputs to the circuit or the values stored in the flip-flops (or both). The value that is stored in a flip-flop when the clock pulse occurs
Report on 4-bit Counter design Report- 1, 2. Report on D- Flipflop. Course project for ECE533
Report on 4-bit Counter design Report- 1, 2. Report on D- Flipflop Course project for ECE533 I. Objective: REPORT-I The objective of this project is to design a 4-bit counter and implement it into a chip
Chapter 5: Synchronous Sequential Logic
Chapter 5: Synchronous Sequential Logic NCNU_2016_DD_5_1 Digital systems may contain memory for storing information. Combinational circuits contains no memory elements the outputs depends only on the inputs
Chapter 4: One-Shots, Counters, and Clocks
Chapter 4: One-Shots, Counters, and Clocks I. The Monostable Multivibrator (One-Shot) The timing pulse is one of the most common elements of laboratory electronics. Pulses can control logical sequences
Sri Vidya College of Engineering And Technology. Virudhunagar Department of Electrical and Electronics Engineering
Sri Vidya College of Engineering And Technology Virudhunagar 626 005 Department of Electrical and Electronics Engineering Year/ Semester/ Class : II/ III/ EEE Academic Year: 2017-2018 Subject Code/ Name:
CHAPTER 6 COUNTERS & REGISTERS
CHAPTER 6 COUNTERS & REGISTERS 6.1 Asynchronous Counter 6.2 Synchronous Counter 6.3 State Machine 6.4 Basic Shift Register 6.5 Serial In/Serial Out Shift Register 6.6 Serial In/Parallel Out Shift Register
Department of Electrical and Computer Engineering Mid-Term Examination Winter 2012
1 McGill University Faculty of Engineering ECSE-221B Introduction to Computer Engineering Department of Electrical and Computer Engineering Mid-Term Examination Winter 2012 Examiner: Rola Harmouche Date:
Feedback Sequential Circuits
Feedback Sequential Circuits sequential circuit output depends on 1. current inputs 2. past sequence of inputs current state feedback sequential circuit uses ordinary gates and feedback loops to create
The basic logic gates are the inverter (or NOT gate), the AND gate, the OR gate and the exclusive-or gate (XOR). If you put an inverter in front of
1 The basic logic gates are the inverter (or NOT gate), the AND gate, the OR gate and the exclusive-or gate (XOR). If you put an inverter in front of the AND gate, you get the NAND gate etc. 2 One of the
Combinational / Sequential Logic
Digital Circuit Design and Language Combinational / Sequential Logic Chang, Ik Joon Kyunghee University Combinational Logic + The outputs are determined by the present inputs + Consist of input/output
EKT 121/4 ELEKTRONIK DIGIT 1
EKT 2/4 ELEKTRONIK DIGIT Kolej Universiti Kejuruteraan Utara Malaysia Sequential Logic Circuits - COUNTERS - LATCHES (review) S-R R Latch S-R R Latch Active-LOW input INPUTS OUTPUTS S R Q Q COMMENTS Q
Synchronous Sequential Logic
Synchronous Sequential Logic ( 范倫達 ), Ph. D. Department of Computer Science National Chiao Tung University Taiwan, R.O.C. Fall, 2017 ldvan@cs.nctu.edu.tw http://www.cs.nctu.edu.tw/~ldvan/ Outlines Sequential
Sequential Digital Design. Laboratory Manual. Experiment #7. Counters
The Islamic University of Gaza Engineering Faculty Department of Computer Engineering Spring 2018 ECOM 2022 Khaleel I. Shaheen Sequential Digital Design Laboratory Manual Experiment #7 Counters Objectives
Software Engineering 2DA4. Slides 9: Asynchronous Sequential Circuits
Software Engineering 2DA4 Slides 9: Asynchronous Sequential Circuits Dr. Ryan Leduc Department of Computing and Software McMaster University Material based on S. Brown and Z. Vranesic, Fundamentals of
Laboratory 1 - Introduction to Digital Electronics and Lab Equipment (Logic Analyzers, Digital Oscilloscope, and FPGA-based Labkit)
Massachusetts Institute of Technology Department of Electrical Engineering and Computer Science 6. - Introductory Digital Systems Laboratory (Spring 006) Laboratory - Introduction to Digital Electronics