CSC Muon Trigger. Jay Hauser. Director s Review Fermilab, Apr 30, Outline

Transcription

1 CSC Muon Trigger Jay Hauser Director s Review Fermilab, Apr 30, 2002 Outline The CSC muon trigger design Project scope Fall 2000 prototype test Pre-production prototype to be tested Summer 03 Conclusions Jay Hauser, Fermilab Director s Review, Apr. 30,

2 CMS Endcap Muon System 3 or 4 stations Each CSC chamber has six planes: 1. Radial cathode strips for precision muon position and bend direction measurement 2. Anode wires for timing (bunch ID) and non-bend position measurement Jay Hauser, Fermilab Director s Review, Apr. 30,

3 Geometric Coverage ME4 descoped Jay Hauser, Fermilab Director s Review, Apr. 30,

4 Trigger requirements Cathode LCT Identify cathode track segment. P t trigger based on angle of LCT For P t threshold of GeV requires Dp/p < 30% (in order to limit single muon trigger rate in Level-1 to a few KHz) Track hits must be located to within ½ strip width in each chamber layer Anode LCT Form anode track segment. Tag bunch crossing of track segment with > 92 % efficiency per chamber Jay Hauser, Fermilab Director s Review, Apr. 30,

5 CSC Trigger Efficiency vs. P T Trigger threshold defined at 90% efficiency Sharper turn-on for better P T resolution Require ME1 for good P T resolution 1.2 < h < 2.4 Jay Hauser, Fermilab Director s Review, Apr. 30,

6 CSC Trigger Efficiency vs. h Loose: 2 or more stations including ME1 in endcap, but any two in DT/CSC overlap region ~97% efficiency Tight: 3 or more stations including ME1 in endcap and MB1 in DT/CSC overlap ~70% efficiency but better P T resolution Jay Hauser, Fermilab Director s Review, Apr. 30,

7 CSC Single Muon Rate h < 2.1 Require tight track conditions ( e» 70%) to get acceptable rate from standalone CSC trigger Multiply by 5 for L = Rate must be less than few khz Jay Hauser, Fermilab Director s Review, Apr. 30,

8 Endcap Muon Trigger Primitive Generation Clock Control Board Slow Control Muon Sector Receiver Lev-1 Trigger Trigger-Timing-Control D T D T D T D T D T C M T D T D T D T D M M M M M M M M M M C P M M M M M M M M C B B B B B B B B B B B C B B B B B B B B O N T R O L L E R Trig Motherboard 1 of 5 1 of 5 DAQ Motherboard Readout Data Peripheral Crate on iron disk DDU Board FED Crate in XSC55 CFEB CFEB CFEB CFEB CFEB Cathode Front-end Board 1 of 2 LV Distribution Board LVDB ALCT 1 of 24 Anode LCT Board CSC Anode Front-end Board Jay Hauser, Fermilab Director s Review, Apr. 30,

9 Trigger Motherboard (TMB) Source of CSC trigger primitives for 1 chamber: sent on backplane to Muon Port Card (MPC) Other functions: Generates Cathode LCT trigger with input from CFEB (comparator) Matches ALCT and CLCT; sends anode hits to DMB. Input connectors From 5 CFEB s Main FPGA (on back) XILINX XCV1000E Mezzanine board Input connectors From ALCT Jay Hauser, Fermilab Director s Review, Apr. 30,

10 CSC Sectors Data Mapping Jay Hauser, Fermilab Director s Review, Apr. 30,

11 On-Chamber Trigger Primitives Strip FE cards FE FE LCT Wire LCT card Wire FE cards CSC Muon Trigger Scheme RIM RPC Interface Module Trigger Motherboard LCT TMB Combination of all 3 Muon Systems Muon Port Card Jay Hauser, Fermilab Director s Review, Apr. 30, PC 2µ / chamber In counting house RPC 4µ OPTICAL DT 4µ Sector Receiver SR 3µ / port card Global µ Trigger 3-D Track-Finding and Measurement 3µ / sector CSC Muon Sorter 4µ 4µ Sector Processor SP Global L1

12 Scope of CSC Trigger Project Baselined with 24 crates, reduced to 6 in 1998, now 1: Prototype version tested Fall 2000: Board MPC Sector Receiver Sector Processor Clock and Control Board CSC Muon Sorter # units Responsibility Rice UCLA Florida Rice Rice New version (SR/SP combined) Board MPC SR/SP Clock and Control Board CSC Muon Sorter # units Responsibility Rice Florida Rice Rice Crates, Backplanes 6 Florida Crates, Backplanes 1 Florida DDU readout 1 Florida/Ohio State DDU readout 1 Florida/Ohio State Jay Hauser, Fermilab Director s Review, Apr. 30,

13 Prototype Test in Fall 2000 Muon Port Card produces CSC muon segment data Data sent over Giga-bit optical link Sector Receiver receives and formats data Formatted data sent over backplane Sector Processor links CSC muon segments into track, assigns P T, f, h Hardware operated at full 40 MHz speed Results compared bit-for-bit with simulation Perfect agreement attained Jay Hauser, Fermilab Director s Review, Apr. 30,

14 Track Finder Prototype FY 2000 focus was on producing and testing a Track Finder prototype: DAQ System (VME, Bit3 Controller, PC running Windows NT) Items produced: Backplane (Florida) Sector Processor (Florida) Muon Port Card (Rice) Clock and Control Board (Rice) Sector Receiver (UCLA) Test software support (all) FIFO Port Card FIFO 100m Optical Links FIFO Sector Receiver FIFO Custom Back plane FIFO Sector Processor FIFO Results included in Trigger TDR (Oct. 2000): > Input data bits loaded into Port Card or SR > Data clocked through MPC SR SP at full speed > Results examined for validity Jay Hauser, Fermilab Director s Review, Apr. 30,

15 Muon Port Card Prototype VME Interface Optical links Main FPGA on Daughter Card Jay Hauser, Fermilab Director s Review, Apr. 30,

16 Sector Receiver Prototype Optical Receivers and HP Glinks UCLA SRAM LUTs Front FPGAs Back FPGAs Jay Hauser, Fermilab Director s Review, Apr. 30,

17 Sector Processor Prototype Final Selection Unit XCV150BG352 Extrapolation Units XCV400BG560 Florida 12 layers 10K vias 17 FPGAs 12 SRAMs 25 buffers Assignment Units XCV50BG256 & 2M x 8 SRAM Track Assemblers 256k x 16 SRAM Bunch Crossing Analyzer XCV50BG256 Jay Hauser, Fermilab Director s Review, Apr. 30,

18 Bit3 VME Interface 1st Track-Finder Crate Tests Custom Backplane Clock Control Muon Port Card (Florida) Board (Rice) (Rice): Sector Processor (Florida): Sector Receiver (UCLA): Prototype crate for original six crate design tests very successful but latency too high -- New design in m optical fibers Jay Hauser, Fermilab Director s Review, Apr. 30,

19 Clock and Control Board Muon Sorter From Trigger Timing Control To Global Trigger BIT3 Controller New EMU Trigger Design: U. Florida Track-Finder Track-Finder crate (1.6 Gbits/s optical links) SR / SP SR / SP SR / SP SR SR / / SP SP SR / SP MS CCB SR / SP SR / SP SR / SP SR / SP SR / SP SR / SP SP 2002 Card (3 Sector Receivers + Sector Processor) (60 sector) From MPC (chamber 4) From MPC (chamber 3) From MPC (chamber 2) From MPC (chamber 1B) From MPC (chamber 1A) To DAQ Power consumption : ~ 1000W per crate 16 optical connections per SP Custom backplane for SP «CCB and MS connections Jay Hauser, Fermilab Director s Review, Apr. 30,

20 New 1-Crate 1 Design Meets Latency Requirement First prototype dataflow From Muon Port Cards Pre-production prototype data flow From Muon Port Cards Optical receivers Front FPGAs Lookup tables Channel link transmitters Sector Receiver st.1 Sector Receiver st.2,3 Sector Receiver st SR/SP board Optical receivers Front FPGAs Lookup tables Bunch crossing analyzer (not implemented) To DT Latency Channel link receivers Bunch crossing analyzer (not implemented) Extrapolation units 9 Track Assembler units (memory) Final selection unit 3 best out of 9 Pt precalculation for best 3 muons Pt assignment (memory) Sector Processor Latency Sector Processor FPGA Extrapolation units 9 Track Assembler units Pt precalculation for 9 muons Output multiplexor Pt assignment (memory) Final selection unit 3 best out of 9 Total: 21 BX To Muon Sorter Total: 7 BX To Muon Sorter Jay Hauser, Fermilab Director s Review, Apr. 30,

21 MPC (Muon Port Card) Description of CSC Trigger System Elements Source of muon segment data from chambers SR/SP (Sector Receiver/Sector Processor) Links segments into tracks with known momentum CCB (Clock & Control Board) Clocking and interface to global control system CSC Muon Sorter Collects tracks for transmission to Global Muon Trigger Track Finder crate backplane DDU (Detector-Dependant Unit) For readout, used for diagnostics for the trigger Jay Hauser, Fermilab Director s Review, Apr. 30,

22 New MPC Design (Rice) 9U x 400 MM BOARD VME INTERFACE VME J1 CONNECTOR UCLA MEZZANINE CARD (XCV600E) CCB CCB 3 OPTICAL CABLES TO SECTOR PROCESSOR FINISAR FTRJ OPTICAL TRANSCEIVERS OPTO OPTO OPTO SER SER SER CCB INTERFACE SORTING LOGIC INPUT AND OUTPUT FIFO TMB_1 TMB_2 TMB_3 TMB_4 TMB_5 TMB_6 TMB_7 TMB_8 CUSTOM PERIPHERAL BACKPLANE TLK2501 SERIALIZERS FPGA TMB_9 SN74GTLP18612 GTLP TRANSCEIVERS Jay Hauser, Fermilab Director s Review, Apr. 30,

23 Optical Link Radiation Tests Three serializers: up to 270 krad TID. No permanent damage or SEU Two Finisar optical modules: No errors up to 70 krad. Failed at ~70kRad (well above ~10 krad TID inner CSC dose for 10 years) -- Rice Jay Hauser, Fermilab Director s Review, Apr. 30,

24 EEPROM Indicators TLK2501 Transceiver Sector Processor 2002 Board Layout Phi Global LUT Eta Global LUT Phi Local LUT DC-DC Converter EEPROM EEPROM VME/CCB FPGA Front FPGA From CCB DDU FPGA Optical Transceiver Main FPGA Mezzanine Card PT LUT To MS TRANSITION BOARD WITH LVDS TRANSCEIVERS TO/ FROM BARREL Jay Hauser, Fermilab Director s Review, Apr. 30,

25 ME1 SR LUT Triad FRONT FPGA A18 C3 PHIL LUT 256K x 18 Flow Through SRAM CLCT PAT# - 4 Q - 4 Phi_L -10 CLCT_ID - 8 PhiB_L - 6 L/R -1 PhiB_L - 6 Phi_L - 2 CSC_ID - 4 WG_ID - 7 ETAG LUT 512K x 18 Flow Through SRAM PhiB_G - 5 Eta_G - 7 MAIN FPGA A11 CSC_ID 4 WG_ID 7 CSC ID - 4 CLK40P1 C3 D16 C2 C4 D12 CLK40P2 16 Bit Trans ceiver Phi_L - 10 WG_ID - 5 CSC_ID - 4 PHIG LUT 512K x 36 Flow Through SRAM 16 Bit Phi_G -12 Phi_DT - 12 To DT C2 Trans ceiver CLK40 Legend: A Address Lines D - Data Lines C Control Lines CLK Clock 45 synchronous memories for conversion of 15 track segments >64 MB per board Need high VME bandwidth, broadcast capability to identical chips, and crate broadcast capability to SPs CLK40 Jay Hauser, Fermilab Director s Review, Apr. 30,

26 ME2/ ME4 STUBS 9xD24 9xD5 3xD1 Main Sector Processor FPGA MAIN FPGA C3 3xD12 + 4xD1 MUX ME1 STUBS 6xD24 6xD9 2xD1 3xA22 3xC4 PT PT LUT 3xD8 3xD8 DT STUBS 2xD25 D8 TRAN 3xD8 3xC1 DDU INT CCB & VME INT C2 C4 D32 C2 C9 CLK40 A8 D16 C1 C3 CFG ROM Legend: G Number of Signal Groups GxAn G Groups of n Address Lines GxCn G Groups of n Control Lines GxDn - G Groups of n Data Lines TRAN - Transceiver CCB&VME Int Combined CCB and VME Interface CFG ROM Configuration ROM CLK40 Clock 40 MHz DDU- INT Readout Interface Placed on mezzanine card Firmware written in Verilog++ and implemented in ORCA as well Latency only 4 BX Jay Hauser, Fermilab Director s Review, Apr. 30,

27 CCB for Track Finder Crate Same CCB for peripheral and Track Finder crates 20 sets (main 9U board + Altera-based mezzanine card) have been fabricated so far 15 boards are assembled and tested 2 boards will be used for Track Finder tests (UF & Rice) TTCrx mezzanine board Jay Hauser, Fermilab Director s Review, Apr. 30,

28 Sorter FPGA TMB 1 DFF MUX 4 PIPELINE MUON 1 MUX DFF MUON 1 VME FIFO A FIFO_B MUON 1 VME DFF MUX 4 PIPELINE MUON 2 DFF MUON 2 VME FIFO A FIFO_B MUON 2 TMB 2 TMB 9 DFF VME MUON 3 VME SORTER 3 OUT OF FIFO_B MUON 3 CCB CCB INTERFACE 9 VME WINNER Jay Hauser, Fermilab Director s Review, Apr. 30,

29 CSC Track Finder Backplane Standard VME 64x J1/P1 backplane A24/D16 (but D32 possible using address lines) Standard VME J2/P2 backplane SRSP 1 SRSP 2 SRSP 3 SRSP 4 SRSP 5 SRSP 6 Clock and control Muon sorter SRSP 7 SRSP 8 SRSP 9 SRSP 10 SRSP 11 SRSP 12 Signals specified, routing to commence Custom GTLP 6U backplane Jay Hauser, Fermilab Director s Review, Apr. 30,

30 Mirror CSC DAQ Path OSU now plans 20 slices to equalize bandwidth 15 optical fibers CSC DDU designed by Ohio State Univ. 36 Sector Processors send L1 data 12 optical fibers DDU SLINK + 1 Jay Hauser, Fermilab Director s Review, Apr. 30,

31 CSC Trigger Status/Plans Prototype 1 tests now complete Prototype 2 and production follow EMU components to optimize technology MPC, SP, CCC modules, backplane* milestones: Apr-02 Prototype 2 designs done Freeze CSC-DT interface Determine DDU compatibility with OSU module for EMU Nov-02 Prototype 2 construction done Apr-03 Prototype 2 testing done Sep-03 Final designs done Oct-04 Production done Apr-05 Installation done (*backplane schedule ~3 months ahead of above dates to provide platform for testing and integration) Muon Sorter module: only 1, design by Jan-04 Jay Hauser, Fermilab Director s Review, Apr. 30,

32 CSC 02 Milestones Syst. Item Action Date Status Comment CSC Bckpl Specified Dec-01 Done OK CSC Bckpl Proto done Jun-02 Delay: Aug-02 OK CSC CCB Proto done Jun-02 Delay: Aug-02 OK CSC SR/SP Proto done Sep-02 Delay: Nov-02 OK CSC Bckpl Proto tested Sep-02 Delay: Apr-03 OK CSC MPC Proto done Sep-02 OK CSC CCB Proto tested Sep-02 Delay: Apr-03 OK Jay Hauser, Fermilab Director s Review, Apr. 30,

33 Personnel Professors Darin Acosta (Florida), Robert Cousins (UCLA), Jay Hauser (UCLA), Paul Padley (Rice) Postdocs Song Ming Wang (Florida), Benn Tannenbaum (UCLA), Slava Valouev (UCLA) Students Bobby Scurlock (Florida),Jason Mumford (UCLA) Engineers JK (UCLA), Alex Madorsky (Florida), Mike Matveev (Rice), Ted Nussbaum (Rice) Collaborating engineers (all PNPI) Victor Golovtsov, Lev Uvarov Jay Hauser, Fermilab Director s Review, Apr. 30,

34 Coordination and Oversight Four institutions: Rice, UCLA, UF, UW Central link to all documentation: Monthly progress reports Videoconferences ~6 weeks 2-day meetings 3x or 4x per year, rotate between Rice, UCLA, and UF, minutes posted UF, March 22-23, 2002 UCLA, Dec , 2001 Rice, Aug 14-15, 2001 etc Jay Hauser, Fermilab Director s Review, Apr. 30,

35 Conclusions First Track Finder system prototyped successfully in Fall 2000 Exact match to CMS OO simulation package Second generation pre-production prototype is well underway with significant improvements Present and future activities 2001: R&D on optical links, FPGA logic, memory look-ups, backplane technology, and DAQ readout 2002: build the 2 nd generation prototype 2003: test with multiple CSC chambers, cosmic rays and/or structured beam, tweaks for final design (if necessary) 2004: full production 2005: installation No trouble expected: all-digital system with off-the-shelf components, well-defined internal and external interfaces, and a stable and capable engineering team Jay Hauser, Fermilab Director s Review, Apr. 30,