Supplementary Information for manuscript of

Transcription

1 Supplementary Information for manuscript of Mechanical Chameleon through Dynamic Real-Time Plasmonic Tuning Guoping Wang 1, 2,+,*, Xuechen Chen 1, +, Sheng Liu 2, Chingping Wong 3, Sheng Chu 1,* 1. State key laboratory for optoelectronics materials and technology & School of physics and engineering, Sun Yat-Sen University; Guangzhou , PR China; 2. School of Power and Mechanical Engineering, Wuhan University, Wuhan , PR China; 3. School of Materials Science and Engineering, Georgia Institute of Technology, Atlanta, GA ,USA. +, These authors contributed equally to this work; *,Corresponding authors: Sheng Chu: Guoping Wang:

2 Supplementary Information 1. SEM image of the AAO template used to create SiO 2 nano-holes. Figure S1 SEM image of AAO used for etching template. Scale bar: 100 nm. 2. The interface between AAO and SiO 2 Figure S2 SEM image of AAO and SiO 2 interface. Scale bar: 100 nm.

3 3. Photo of AAO and sample with nanostructures deposite Figure S3 Top: Photo image of the AAO. Bottom left: SiO 2 nano-holes array after deposition of nanoparticles, which appears reddish colour. Bottom right: photo of a packaged device. 4. The electrochemistry properties of the electrode Figure S4 CV curve of the nanodome electrode.

4 5. Flexible plasmonic cell device The flexible device was made on ITO/PET substrate using similar procedures described in the main text. The device can moderately change colour with the external voltage, as shown in Fig. S5. Figure S5 Photos of the flexible EC device before and after 1 V electrodeposition for 1 s. 6. Endurance characteristics of the device Fig. S6 shows the transmission characteristics of the device after more than 200 cycles of operation. In each cycle, the device was programmed for 1 s, and stayed for 1 s, and then erased for 1 s to return to original state. Figure S6 Endurance characteristics of the plasmonic cell device

5 7. TEM image of the nanodomes Figure S7 TEM image of the nanodomes. Scale bar: 100 nm 8. EDS spectra for samples in Fig. 3 a. Sample 1: no Ag signal was found cps/ev In Ca C O Mg Na Al Si In Ca kev Figure S8a EDS spectrum of the sample 1.

6 Table S1a Composition of overall elements in sample 1. Element Series unn. C norm.c Atom. C Error (1 Sigma) [wt.%] [wt.%] [at.%] [wt.%] Carbon K-series Oxygen K-series Sodium K-series Magnesium K-series Aluminium K-series Silicon K-series Calcium K-series Indium L-series Gold M-series b. Sample 2: Ag signal detected. Figure S8 b EDS spectrum of the sample 2. Table S1b Composition of and Ag elements in sample 2. Element Series unn. C norm.c Atom. C Error (1 Sigma) [wt.%] [wt.%] [at.%] [wt.%] Silver L-series Gold M-series

7 c. Sample 3: More Ag detected. cps/ev In Ag Ca C O Al Mg Si Ag In Ca kev Figure S8c EDS spectrum of the sample 3 Table S1c Composition of and Ag elements in sample 3. Element Series unn. C norm.c Atom. C Error (1 Sigma) [wt.%] [wt.%] [at.%] [wt.%] Silver L-series Gold M-series

8 d. Sample 4: continue increase of Ag cps/ev In Ag C O Ca Al Mg Si Ag In Ca kev Figure S8d EDS spectrum of the sample 4. Table S1d Composition of and Ag elements in sample 4. Element Series unn. C norm.c Atom. C Error (1 Sigma) [wt.%] [wt.%] [at.%] [wt.%] Silver L-series Gold M-series The shift of peak wavelength due to the shape of the nanodomes: The extinction cross section is expressed as:δ /. Here the maximum cross section happens when λ 0. Here is the situation: the aspect ratio change will induce the change of, and then to maintain 0, λ needs to be changed

9 accordingly, leading to the change of peak wavelength. First of all, the increase of Rz (deposition of Ag shell) makes ρ 1 / increase, in turn, it makes increase. Hence, decrease. Finally, in the equation λ 0, λ needs to be increased to maintain 0. Here the typical dependence of λ on wavelength is shown in Figure S9. It is and obvious that λ will blueshift to make λ increase. In other words, when R Z increases due to Ag deposition, the extinction cross-section peak blueshifts. Figure S9 Dependence of λ on wavelength. 10. Structure of the automatic mechanic chameleon The all-automatic mechanic chameleon s structure is shown in Figure S10. The top part is a 3D printed plastic chameleon and the bottom part is the walking and control segments of the system. Due to the limitation of colour sensors and control circuits, the body of chameleon was divided into the front and back parts. They are controlled

10 by their own colour sensors and driving circuit. Figure S10 Structure of the automatic mechanic chameleon 11. Mechanic chameleon driving system design

11 Figure S11 Operational mechanism and circuit diagram of the main control circuits. 12. Driving circuit of the 10 by 10 fast display design In the demonstration of a 10 by 10 fast display screen, we need to drive the 100 devices simultaneously. This exceeds the maximum I/O channel number of market available micro-controller. As a result, 74hc595 shift register is used to expand the I/O channel numbers to meet the control requirements. Figure S12 Integrated driving circuit for the EC display. the driving circuit consists of the following parts: (1) External Crystal Oscillator In order to make ATmega16 clock accurate, its external clock access 8 MHz crystal oscillator. (2) JTAG Programmer

12 Programming with CodeVisionAVR V software, and downloading the program into the ATmega16 through the JTAG Program. (3) Expanding the I/O Ports Of Atmega16 With 74hc595 shift register we can easily extend ATmega16 I/O ports.74hc595 contains a serial shift input port and a parallel eight bits output port, through which it can turn a 8-bits consecutive high/low level input signal into 8 synchronous output signals after 8 clock cycles, namely controlling eightplasmonic cells separately and synchronously. So controlling 100 EC devices needs 13 hc595: Num.(74hc595) =Num.(ECs) Num.(Synchronous Output Ports) = = 12.5 The part of the 74HC595 pins introduction is shown as Table S2. A SER(pin14) connects to an I/O port, so 13 HC595 SERs need 13 I/O ports. The clock input(pin11,pin12) connect to 2 I/O ports.the 13 HC595 clock input sharing the same pins only need 2 I/O ports. Therefore, extended circuit can control 100 plasmonic cells separately and synchronously, costing 13+2=15 I/O ports only that less than the 32 I/O ports of ATmega16, meeting the requirements. Pins Rules SER(pin14, the serial data input) / QA QH / (pin15 and pin1-7,the parallel data output) SRCLK The shift register data flowing direction is (pin11, the shift register clock input) QA-->QB-->QC-->...-->QH at positive edge and remain still at negative edge. RCLK (pin12, the storage register clock input) The storage registers store shift register data at positive edge and remain still at

13 negative edge. Table S2 Part of the 74HC595 pins introduction (4) Operation Process Of A Single 74HC595 Fig. S13 The circuit about a single 74HC595 controlling 8 plasmonic cells s is shown as Figure S13 74HC595 control circuit The ATmega16 PD0 and PD1 output ports can control three working states, as shown in Table S3. 0 means low level and 1 means high level. ATmega16 Control Ports NMOS States Source States PD0 PD1 Qa Qb / 0 0 off off on off +VCC

14 1 0 off on -VCC Table S3 PD0 and PD1 ports control three working states After eight clock cycles, the input 8 bits data from SER serial port transfer to parallel output ports QA-QH, and if Qx(x is A-H) is high level 1 the corresponding branch NMOS will be on state, as shown in Table S4. HC595 Output Branch NMOS States Qx(x is A-H) Qy(y is 8-1) 0 off 1 on Table S4 Branches NMOS work states In combination with Table 2 and Table 3, the conclusion of a single plasmonic cell device operating progress is shown as Table S5. ATmega16 Control Ports Table S5 Branches units work states NMOS States Source States PD0 PD1 Qa Qb voltage HC595 Output Qx (x is A-H) Branch NMOS States Qy (y is 8-1) Plasmonic Cell States Colour deposition 0 0 off off 0 / / Stay 0 1 on off +VCC 1 0 off on -VCC 0 off Stay 1 on Brighten to max. 0 off Stay 1 on Colour stripping

15 (5) The Integrated Circuit Integrating the above parts, the circuit is shown as Fig. S13. Firstly, turning size 10 x10 character to high/low levels, programming into the corresponding part of program and downloading into ATmega16 through JTAG programmer. Secondly, through ATmega16 13 I/O ports (PA0-PA7 and PB0-PB4), under the control of shift register clock and storage register clock(connected to PD2 and PD3), spending the same cycles, we transfer 100 bits data to 100 parallel output pins of 13 HC595 devices(u5-u17). Lastly, using the Delay programming statement to make Mega16 output delay 1s, under the control of PD0 and PD1, we can realize the memory characteristics of plasmonic cells.