ECE 263 Digital Systems, Fall 2015

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ECE 263 Digital Systems, Fall 2015 REVIEW: FINALS MEMORY ROM, PROM, EPROM, EEPROM, FLASH RAM, DRAM, SRAM Design of a memory cell 1.

How does a Flash memory perform read, write and erase operation? Explain using a circuit. 3. Write the differences between RAM and ROM. 4.

A certain ROM has a capacity of 16Kb X 4b. How many WORDs are in the memory? How many bits are there per WORD?

Write a Verilog to design a 16 WORD x 16 BIT memory cell based on the following constraints: When Read/Write is high, contents of the memory are read from the address

Your top level entity should have Entity memory 16X16 is port (Address_IN: in std_logic_vector ( 3 downto 0); R_W : in std logic; CLK: in std_logic; DataIn: in

1 ECE 263 Digital Systems, Fall 2015 REVIEW: FINALS MEMORY ROM, PROM, EPROM, EEPROM, FLASH RAM, DRAM, SRAM Design of a memory cell 1. Draw circuits and write 2 differences and 2 similarities between DRAM and SRAM memories. 2. What is a Flash memory? How does a Flash memory perform read, write and erase operation? Explain using a circuit. 3. Write the differences between RAM and ROM. 4. Write the differences between ROM, PROM, EROM and EEROM. 5. How many data inputs, data outputs, and address inputs are needed for a 1024 B x 4B ROM? 6. A certain ROM has a capacity of 16Kb X 4b. How many WORDs are in the memory? How many bits are there per WORD? If a decoder is used, what will be the size of the decoder? 7. Write a Verilog to design a 16 WORD x 16 BIT memory cell based on the following constraints: When Read/Write is high, contents of the memory are read from the address through the 16 bit output bus. If Read/Write is low, new contents from 16 bit inputs are written into the memory on the positive edge of the clock. Your top level entity should have Entity memory 16X16 is port (Address_IN: in std_logic_vector ( 3 downto 0); R_W : in std logic; CLK: in std_logic; DataIn: in std_logic_vector ( 15 downto 0); DataOut: out std_logc_vector (15 downto 0)); End memory; --Address lines --Read and Write Signals -- Clock Signal -- 4 Bit Input Data -- 4 Bit output Data 8. A sequential circuit has one flip-flop and two inputs X and Y, and one output S. The circuit is described by the following input function: With D as the input to the D flop flop. (a) Draw the logic diagram of the circuit (b) Derive the state table (c) Derive the state diagram REVIEW FOR FINALS Page 1

9. Design a sequential circuit with two flip-flops A and B and one input X. When X=0, the circuit remains at the same state. When X=1, the circuit goes from 00 to 10.

2 9. Design a sequential circuit with two flip-flops A and B and one input X. When X=0, the circuit remains at the same state. When X=1, the circuit goes from 00 to 10. Again at 10, if X=1 it goes to 11. X=1 at 11 takes it to 01, and finally X=1 at 01 takes it back to Design a sequential circuit that can detect the input sequence 101. You will need to make a state diagram, a state table and the simplified next state logic (with flip flops) and the output logic. 11. Design a sequential circuit that can detect the input sequence 111. You will need to make a state diagram, a state table and the simplified next state logic (with flip flops) and the output logic Design a sequential circuit that can detect the input sequence You will need to make a state diagram, a state table and the simplified next state logic (with flip flops) and the output logic. 13. Design a MOD 8 counter using State Machine Techniques using D Flip Flops. 14. For the following problems (a) Make an encoding and a state table (b) Write the simplified output expression (c) Draw a logic circuit using D FFs. 15. Design a MOD 50 counter by cascading MOD 10 and MOD 5 counters. 16. Design a MOD 1000 counter by cascading three BCD counters. REVIEW FOR FINALS Page 2

3 17. Complete the memory waveforms. The memory writes the data when Address is selected, CLK is high and RW is low. Reads the data when RW is high, address is selected. REVIEW FOR FINALS Page 3

4 Complete the following waveforms assuming that the output changes at the negative edge of the CLK A sequential circuit with two D flip flops A and B, two inputs X and Y and one output Z is specified by the following input equations: + + Draw the logic diagram of the circuit Derive the state table REVIEW FOR FINALS Page 4

5 1. A sequential circuit with two D flip flops X and Y, one input A, and one output B are specified by the following input equations: + +. Draw the logic diagram of the circuit Derive the state table Draw the state diagram 2. Design a circuit to detect the sequence : Design a Vending Machine State Diagram as discussed in the class. The machine vends a candy after it receives 15c. For simplicity, you can assume that the machine never returns the change. Make sure to use Don t Care Conditions in KMPA to simplify the next state logic. 4. For Fig 1. : (a) Make a state assignment table for the circuit using 2-bit codes (b) Draw the encoded state tables. 5. For Fig 2: (d) Make a state assignment for the circuit using 3-bit codes for six states. (e) Draw the state table. FFs and Counters Set/Reset Active Low Latch Set/Reset Active High Latch D Latch from Set/Reset Latch Set/Reset Active High Flip Flop Set/Reset Active Low Flip Flop D Flip Flop (positive edge or negative edge) from D Latch JK Flip Flop Truth Table and Design using D FF. Difference between Latch and a Flip Flop. Ripple Counter, Synchronous Counter, Ring and Johnson Counter. REVIEW FOR FINALS Page 5

6 NOTE: We have used JK to design Ripple and Synchronous counters. This is done to make use of the Toggle feature. D FFs were used to Design Synchronous then Shift/Ring and Johnson counters. 6. Draw a synchronous counter (either using D FF or JK FF), which changes on the negative edge of the clock and has an active high reset. The counter will output 10 KHz signal when a 1 MHz clock is applied. Clearly label all the components. Write Verilog for the counter. 7. If each flip flop of a MOD 32 counter has a propagation delay (t pd) of 20ns and every other gates have a t pd of 10ns, find the maximum frequency for this counter, if: Synchronous counter is used Ripple counter is used Ring counter is used Johnson counter is used Solution: Maximum Delay for the synchronous counter is the delay of the slowest possible unit. For Ring and Johnson s counter that is the delay of 1FF. The maximum delay for the Synchronous JK FF is the delay of FF + the delay of the AND Gates, while delay of the Ripple depends on the number of FF s. Frequency for Johnson s and Ring counter=1/(20 ns) Frequency for Synchronous JK =1/(20ns+10ns) Frequency for Ripple Counter=1/(5 x 20ns) For MOD 32, Ripple and Synchronous counter uses 5 FFs, Ring Counter uses 32 FFs, while Johnson s counter uses 16 FFs. 8. Using 4 flip flops, clearly draw a Ripple, Synchronous, Ring and Johnson counters. Also write the respective MOD numbers and the counting sequence for Ring and Johnson counters. 9. Write Verilog for the above mentioned counters. 10. Use Verilog with an asynchronous high RESET to design a negative edge sensitive MOD 16 counter using JKFF. Also draw the frequency outputs. 11. Design a frequency divider circuit that will produce the following four output signal frequencies: 100 KHz, 10 KHz, 1 KHz and 100 Hz. 12. Draw a MOD 10/Decade counter using JKFF that changes at the negative edge of the clock and has a positive RESET. REVIEW FOR FINALS Page 6

7 13. Design a counter that can select between MOD 10 and MOD Design a synchronous MOD 16 up and down counter. The count direction is controlled by dir (0 is to count up). Write a Verilog for the above mentioned circuit. Complete the following waveforms assuming that the output changes at the negative edge of the CLK What is the MOD number for this circuit? Complete the following waveforms assuming that the output changes at the negative edge of the CLK. What is the MOD number for this circuit? Complete the following timing diagrams to prove that you can make a Flip-Flop using two latches. You are supposed to prove that the Flip-Flop switches at the negative edge of the clock. REVIEW FOR FINALS Page 7

8 In the following figure, A, B and D are D latches, and ALU is a 1 bit component. Write VERILOG for the module called ALUPIPE. For the following inputs, draw the response for a positive edge and a negative edge JK FF. Assume Q=0 initially. REVIEW FOR FINALS Page 8

9 Define setup and hold time. What happens if D is unstable at the rising edge, for a level high sensitive latch? What happens if D is unstable at the rising edge, for a positive edge flip-flop? Design a switch de-bounce circuit that gets rid of several output transitions as the switch is moved from contact position 1 to 2. Clearly mention and label the components and complete the truth table which proves the functionality. REVIEW FOR FINALS Page 9

10 X Y Z Set Reset Q NOT (Q) R Write applications of FFs. Q 1. Complete the output waveforms for following memory element. 3. What do you think will happen if D is unstable at the rising edge, for a level high sensitive latch? REVIEW FOR FINALS Page 10

11 4. What happens if D is unstable at the rising edge, for a positive edge flip-flop? 5. Apply the waveforms to the Set/Reset FFs as shown and determine the waveform at Q R Q CHAPTER 6 Q Half Adder and Full Adder circuits. Design of a 4 bit Ripple carry adder. Design of cout for 4 bit ripple carry adder. LOCATION DATA in HEX Values in Dec LOCATION DATA in HEX Values in Dec 1 E3 1 E Location A0 4 A Location 3-4 Design a HA only using the NOR gates. Design an ALU with certain function selected using select signal. Design of a 4 bit ALU. Design a FA using HA components. Design a FA using all NAND gates. Look at the circuit below. The circuit is slightly different than the one we used in class to make a full adder using half adder components. However, this circuit can still be implemented to make a full adder. So, solve the circuit and indicate which outputs on the right represent the sum and which represents the carry out. Also find and indicate the value for the remaining output. REVIEW FOR FINALS Page 11

12 Make a truth table for a subtracter circuit. For a 4 bit adder (including the sign bit), state the conditions that causes the overflow and design an overflow logic for this 4 bit adder circuit. CHAPTER 4 and CHAPTER 9 Verilog, Truth Tables and circuits for o MUX o DEMUX o DECODER o ENCODER o PRIORITY ENCODER o COMPARATOR Design a parallel to serial data transfer circuit Design of a security system. De Morgan s theorem Simplify and draw + + Simplify the logic function and design using 8 to 1 MUX as well as NAND gates. Also write a Verilog for the following program assuming you have a 8 to 1 MUX component. +.. Simplify the logic function and design using NOR gates REVIEW FOR FINALS Page 12

Chapter 6. Flip-Flops and Simple Flip-Flop Applications

Chapter 6. Flip-Flops and Simple Flip-Flop Applications Chapter 6 Flip-Flops and Simple Flip-Flop Applications Basic bistable element It is a circuit having two stable conditions (states). It can be used to store binary symbols. J. C. Huang, 2004 Digital Logic