Computer Organization and Components

Transcription

1 2 Course tructure Computer Organization and Components odule 4: emory Hierarchy odule : esign I5, fall 24 Lecture 2: equential esign F C Ö F2 C Ö2 F7b Lab: dicom F odule 2: C and ssembly Programming ssociate Professor, KTH oyal Institute of Technology ssistant esearch ngineer, University of California, Bereley F3 C Ö F4 C Ö2 F5 C Ö4 C Ö3 odule 5: I/O ystems Lab: nios2time F9 C Ö6 Fa C Ö uiz: processor design** F7a L2 lides version. C Ö C Ö7 Lab: nios2io Lab: nios2int Home lab: threads** C Ö9 Home lab: C odule 6: Parallel Processors and Programs odule 3: Processor esign F6 Home Lab: cache C Ö5 Fb F uiz: parallel ** **) Optional preparation for the written exam. o oral exam. 3 4 genda and egister Files I image=24&picture=staplade-stenar&large= cnowledgement: The structure and several of the good examples are derived from the boo igital esign and Computer rchitecture (23) by.. Harris and. L. Harris.

2 Combinational vs. equential 5 Bistability 6 Circuit without memory Combinational esign (previous lecture) Output depends only on the input. There is no memory. B C out + C in 2 3 What is the difference between these two circuits? nswer: one, but both circuits contain a cycle. What is the value of? otation convention: T-connections connect, four way connections do not. Circuit with memory equential esign (this lecture) epends on both current and prior input values. s a consequence, sequential logic has memory. Today, we will learn about: Flip-Flips egisters We will discuss other inds of memories in course module 4: emory hierarchy. nalysis by considering two cases: Case I: Case II: = = Both cases are stable. The circuit is bistable. This circuit has 2 stable s. Hence, it is a memory that can store bit of information. Problem: We cannot decide what to store (there is no input) Latch What is the behavior of this circuit? nalyze the 4 cases for and. is the T signal and is the T signal. If and are zero, the circuit remembers the previous value, called pre. We have a memory pre pre Problem. The awward case =, = results in that both and are zero. n latch can be implemented using different gates. This is the abstract symbol for an latch. Problem 2. ixes the issues of what and when updates are made. It is hard to design large circuits this way. 7 Latch The latch solves the problems with the latch. It has one data input, and a cloc input.? pre pre The symbol? means don t care. It is used to simplify truth tables (we can sip one row in this case). ometimes a symbol X or is used to describe don t care. ymbol describing a latch: lso called a transparent latch or level-sensitive latch. =, the latch is transparent ( flows through to ). =, the latch is opaque (the latch blocs data from flowing through).

3 9 Flip-Flop flip-flop is edge-triggered and not level-triggered. These symbols describe Flip-Flops. Condensed symbol in master out out The flip-flop (the standard flip-flop) copies to on the rising edge, and remembers its all other times. slave Case I: = The master is transparent and the slave is opaque. in flows to. cnowledgement: The structure and several of the good examples are derived from the boo igital esign and Computer rchitecture (23) by.. Harris and. L. Harris. Case II: = The slave is transparent and the master is opaque. flows to out. 2 esettable and nabled Flip-Flops resettable flip-flop resets the flip-flop to when a reset signal is active. The line above the signal name shows that the reset signal is active low: The reset is active on. T T n enabled flip-flop has an input. Its changes only when = and there is a raising cloc edge (Called W in the exercise). n -bit register consists of flip-flops that share the same cloc input. True or False physical / This resettable flip-flop is synchronously resettable, meaning that it resets on a rising cloc edge. It is is not asynchronously resettable where the reset is independent of the cloc. nswer: True 4-bit register built out of flip-flops (using condensed symbol notation) : 4 4 3: bstract form of a 4-bit register. egister ote that registers can also have enable signals, reset signals etc.

4 Problematic Circuits 3 Floating Values and Tri Buffers 4 Unstable circuit. Illegal value (X) = B = What is the value of? What is the value of? nswer: it oscillates. This circuit is called a ring oscillator. nswer: = X, called an unnown or illegal value. For example, when a wire is driven to both and at the same time. This situation is called contention. tri (or three-) buffer has high impedance if the output enable signal is not active. Commonly used in buses when connecting multiple chips. If the buffers are not enabled at the same time, contention is avoided. Z Z When the enable signal is not active, the output is said to be floating (using symbol Z). Output nable egister 5 egister File (/2) 6 xercise: Create a 2-bit register that has an output enable (O) input signal. If O = then is floating, else it the registers. O O register file can be used to read and write data using an address. Writing bits is done by giving write data to W3, write address to 3, and setting write enable W3 to. 2 3 W3 This is a multi-ported register file. Two read ports and one write port. eads and writes can be done in parallel. W3 2 eading bits from read data port is done by giving an -bit read address to. ame for the second read port (2 and 2).

5 7 egister File (2/2) 3 2 ecoder W3 W3 Can also be implemented using tri buffers (see exercises). 2 2 I xample: egister file with address depth = 2 (4 different addresses) and -bit words ( = ). cnowledgement: The structure and several of the good examples are derived from the boo igital esign and Computer rchitecture (23) by.. Harris and. L. Harris. egister-transfer Level - 9 Finite tate achines (Fs) 2 It is hard to analyze large asynchronous circuits that contain cycles. olution: esign synchronous sequential circuits, also called designing at the register-transfer level (TL), which means that combinational logic is combined with registers s are only updated on cloc edges Which of the following circuits are using TL design / sequential synchronous logic? ynchronous equential s can be defined as Fs oore achine (,, s) ext tate Output Combinational Circuit es, with no feedbac Combinational Circuit o, because of latch. Combinational Circuit o, has a cycle without register in the path ealy achine (,, s) ext tate Outputs can be directly dependent on the Output

6 2 22 imple ealy achine xample dge-triggered Timing ethodology How fast can we run a circuit? cloc init st 2nd 3rd B C B C delay = tprop + tcombinational + tsetup + tsew Time to propagate through the flip-flop or register. fter st, 2nd etc. positive cloc edge. ext tate Output ecessary time before the rising cloc edge. The longest delay in the combinational logic. race may occur when the values of elements depend on the relative speed of logic elements in the circuit. The cloc period must be shorter than the worst-case of delays in the circuit. ext tate Compensate for cloc sew: cloc signals reach elements at different time. The worst-case delay is computed for the feedbac loop through the logic. Output ummary evisions ome ey tae away points: Combinational vs. equential : Combinational logic has no memory, whereas sequential logic includes memory. vs. Flip-Flops vs. egisters vs. egister File Flip-flops are edge triggered, registers combine flip-flops, and register files uses addresses to access data. v. (24-9-) First version uploaded after the lecture. v. (24-9-5) Fixed a typo on page 7, Problem. hould be =, =. ynchronous vs. synchronous esign ynchronous esign maes design wor easier. ealy vs. oore achines Both are finite machines (Fs). oore machines depend only on the, whereas ealy machines depend on the and the input. Thans for listening!