Latches and Flip-Flops UNIT 11 LATCHES AND FLIP-FLOPS. How to Remember the Past? Recap: Two Types of Switching Circuits. Iris Hui-Ru Jiang Spring 2010

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1 atches and Flip-Flops UNI ACHE AN FI-FO 2 Contents et-eset latch Gated latch Edge-triggered flip-flop - flip-flop - flip-flop flip-flop Flip-flops with additional inputs eading Unit Iris Hui-u iang pring 2 ecap: wo ypes of witching Circuits How to emember the ast? 3 Combinational circuits (memoryless) Outputs depend only on present inputs X X 2 X n... Combinational circuit F equential circuits (with memory) Outputs depend on both present & past inputs Z = F(X, X 2,, X n ) In general, sequential ckts = combinational ckts + memory X X 2 X n (n-)... Combinational circuit F Memory element (n) Z = F(X, X 2,, X n, (n-)) 4 Feedback: the output of one of the gates is connected back into the input of another gate in the ckt so as to form a closed loop e.g., inverter with feedback : How fast does the circuit oscillate? A: etermined by the propagation delay of the inverter Feedback X Oscillation at inverter output X e.g., a feedback loop with two inverters wo stable states atch: basic memory unit (store bit) Now, the values can be kept t

2 et-eset (-) atch (/2) 6 5 et-eset atch - latch stable = set : ; : stable = reset : ; : - atch (2/2) Next-tate Equation 7 Cross-coupled form ' = = Unstable! Not allowed!! ' ' : eset : et 8 iming diagram (t) (t) (t) Operation (t +є) et to eset to -map Inputs not allowed (t) (t)(t) є є t t 2 t 3 t 4 t t +є t 3 +є є: 2 gate delay X X (t+є)=(t)+'(t)(t) Next-state equation: (Characteristic equation) + = +' under = (=, = not allowed)

3 Application: witch ebouncing Alternative Form with NAN-Gates 9 +V When a mechanical switch is opened or closed, switch contacts tend to vibrate before settling down ebounce with - latch e.g, when the switch is flipped from a to b Work only with a double throw switch ouble throw: switch between two contacts ingle throw: switch between one contact and open b a == unchanged - latch: active-low inputs for & + eset to et to Inputs not allowed ull down resistors witch at a Bounce at a witch between a and b Bounce at b witch at b Gated atch 2 Gated atch G G G G G + + = Update + = G + =G +G

4 Edge-riggered Flip-Flops 4 3 Edge-riggered Flip-Flop Output changes are aligned with clock edges ositive (rising-edge) trigger Negative (falling-edge) trigger ymbol ruth table ising-edge trigger Falling-edge trigger + + = iming diagram for falling-edge triggered ising Edge rigger 5 Construct from 2 gated latches 2 2 G 2 G Flip-Flop iming diagram 2 hold hold 2 hold =G 2 G : What s the difference between a latch and a?

5 - Flip Flop 7 Output changes at clock edges Construct from 2 latches Master lave 8 - Flip-Flop Operation operation No state change eset to (after active edge) et to (after active edge) Not allowed t t 2 t 3 t 4 t 5 Not an edge-triggered o not allow change while is low 9 - Flip-Flop Extension of - : jump to : clear to Master lave 2 Flip-Flop + atches & s + = + Clear to ump to oggle = =, oggle t p t p t p t t 2 t 3

6 2 Flip-Flop : oggle + = + = oggle t p t 4 t p 22 s with Additional Inputs Implementation t t 2 t 3 - based: = = = = oggle + = + = + based: input: + = = + Clock Clock with Clear and reset with Clock Enable Use additional inputs to set to an initial state independent of the clock e.g., asynchronous Clear and reset We want some Flip-flops to hold existing data even though the data input may be changing Gated clock: gate the clock by clock enable (CE) ClrN ren CE ren ClrN + x x - (not allowed) x x x x ClrN ren En in in CE,, x (no change) t t 2 t 3 t 4 + = = CE + CE in Normal eep whole cycle

7 Characteristic Equations for ummary ype + - latch or + = + ' ( = ) Gated latch -CE - + = G + G + = + = CE + CE' + = + + = Homework for Unit 27 roblems Homework #4: Units 9-- ue am May, 2 uiz #2: due day of Homework #4