Logic Design IS1200, spring 2015 Review Slides

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1 2 I2, spring 25 Review lides ssociate Professor, KTH Royal Institute of Technology ssistant Research ngineer, University of alifornia, erkeley genda I lides version. I 3 umber ystems (/3) ecimal and inary umbers 4 How can we represent numbers? ecimal umbers,2,3,,,9,,,,73,,, 375 = The base is. inary umbers, binary value is called a bit. This is what a computer system is using. Often, = true and = false 2 = = What is the number in decimal form? 3 I I

2 umber ystems (2/3) ytes, ibbles, Words,, L, 5 umber ystems (3/3) Hexadecimal umbers 6 It s quite tedious to work with only binary numbers Therefore, bits are grouped into bytes, each consisting of bits. msb lsb In a group of bits, the least significant bit (lsb) is to the right. The most significant bit (msb) is to the left. Within a word, the terms are the most significant byte () and the least significant byte (L). 4 bits (half a byte) is called a nibble. L icroprocessors use data in the size of words. 32-bit processor has 32-bit words, a 64-bit processor has 64-bit words. I 32-bit word re decimal numbers a good way to represent: ibbles? 6 5 ytes? Problem: ibbles cannot be identified directly in the byte. Hexadecimal umbers oined at I in 963. From Greek hexi (six) and Latin decem (ten). ource: Harris and Harris, 23. byte can hold 256 different values,, 2, 3, 4, 5, 6, 7,, 9,,,,,, F,,,, 9,,, The base is 6. lways two digits for each byte. One digit = one nibble. I 54 6 Logic Gates (/3), OR, OT, and UF 7 Logic Gates (2/3), OR, XOR, and XOR H OR OT. ote the mall bubble at the end. OR OT OR. OT The small circle (called a bubble) inverse the signal. OT is also called an inverter. UF Looks like not, but has no circle. uffer. Logically the same as a wire. Relevant from an analog point of view. XOR xclusive OR, pronounced ex-or. XOR xclusive OT OR. I I

3 Logic Gates (3/3) ulti-input Logic Gates 9 ombinational ircuit H Gates can be generalized to have more than two inputs. For instance: 3 gate with 3 inputs. OR5 OT OR gate with 5 inputs. XOR3 xclusive OR gate with 3 inputs. n -input XOR gate is also called a parity gate. It outputs when odd number of inputs are. = = = = = = = = This circuit is combinational because its outputs depend only on its inputs. The circuit is memoryless, that is, it has no memory. We will introduce memory in Lecture 2 Observe that this (rather useless) circuit always outputs. s a logic formula, this is called a tautology. I I oolean lgebra (/4) Truth Tables and um-of-products Form truth table with random output (we have seen them before). We can create a boolean expression from the truth table The of one or more variables is called a product. The line over a variable is called the complement and is the inverse of the variable (OT). ometimes a prime is used instead. can be written using no space or using a dot, e.g.!! OR is written using the symbol. This form is called sum-of-products (surprise!) I oolean lgebra (2/4) ome Theorems Theorem ual ame! = = Identity! = = ull lement! = = = Idempotency Involution! = = omplements! =! = ommutativity (!)! =!(!) (!)(!)=!() () = = () ssociativity () =! ()!()= istributivity = (!) ote! ot as traditional algebra = xercise: erive the simplest form of expression olution: = I H 2 ommutativity istributivity omplements (dual) Identity Indempotency (dual)

4 3 oolean lgebra (3/4) e organ s Theorem Theorem ual! 2! 3 = 2 3 = ( 2 3 ) (! 2! 3 ) Perfect Induction = Proof by xhaustion = Proof by ases = ugustus e organ ritish mathematician and logician (6 7). Important law. For O (omplementary metal oxide semiconductor), and OR gates are preferred over and OR gates. I 2 bits for the data input multiplexer can be seen as a simple switch, selecting which signal that should pass through the block. output One possible implementation. onvince yourself of its correctness! I I : multiplexer can be defined hierarchically. 4: multiplexer (4 inputs, output). The control signal selects which input bit that is sent to the output. ombinational locks (2/3) ultiplexers It s a 2: ultiplexer. 5 ombinational locks (/3) ultiplexers What is this? Proof by perfect induction. xhaustively show all cases in a truth table. ut how can we know that this theorem is true? = = = = = = ote that these two columns are equal Prove the e organ s Theorem for three variables The law shows that these gates are equivalent 4 oolean lgebra (4/4) Proof by Perfect Induction What is the output signal for the 4: multiplexer with these inputs? 2 3 =, =, 2=, 3=, =, = nswer: = I

5 7 ombinational locks (3/3) ecoders decoder has inputs and 2 outputs. sserts exactly one output. ecoder half adder has a carry out signal. 3 2 out Idea: hain adders together 2:4 decoder (2 inputs, 4 output). ote that only one signal is on each row. This is called one-hot. I 9 n -bit carry propagate adder (P) sums two -bit inputs. out ote the notation for a -bit bus. ee course book Prefix adder (advanced part) ven faster. Used in modern computers. in out out xercise: omplete the truth table I rithmetic ircuits and umbers (3/7) egative umbers, ign/agnitude 5 bits signed/magnitude numbers 6 = 2 7 = 2-6 = 2-7 = = = 2 hould be but 3 3 an we add two numbers using binary addition? 32-bit ripple-carry adder 3 3 Idea: Let msb represent the sign ( = negative, = positive) and the remaining bits the magnitude. This representation is called signed/magnitude numbers. Ripple-carry adder imple but slow. in How can we represent negative numbers? arry-lookahead adder Faster, divides into blocks. in Three common implementations of Ps are: out rithmetic ircuits and umbers (2/7) arry Propagate dders How can we add bigger numbers? H full adder has both carry out and carry in signals. 2 3 rithmetic ircuits and umbers (/7) Half and Full dders 2 2 = 2 = -3 Problem : inary addition does not work out I in 2 = and 2 = - Problem 2: trange effect; we have two numbers for zero... I 2

6 rithmetic ircuits and umbers (4/7) egative umbers, Two s omplement 2 rithmetic ircuits and umbers (5/7) egative umbers, Two s omplement 22 olution: Two s complement numbers Which patterns can we find in the following 3-bit two s complement numbers. Only one number represent (olution to problem ) ll negative numbers have msb set. This is called the sign bit. 2 = 2 = 2 = 2 2 = 3 2 = -4 2 = -3 2 = -2 2 = - Positive numbers are represented as usual. an represent one more negative number than positive numbers. egative numbers are listed in reverse order. I Why is it called two s complement? ecause the negation of an -bit value X is 2 X. Is binary addition working with two s complement numbers? 5 bits two s complement numbers (check yourself) xample: = 3 and X = 3. Then = 3 = 5 = 2 hould be I 2 = 2 = 2 = 2 2 = 3 2 = -4 2 = -3 2 = -2 2 = = = 2 6 = 2 7 = = 2-6 = es, it works (general proof left as 2-7 = 2 an exercise). ote that the carry out is, but ignored here. rithmetic ircuits and umbers (6/7) egative umbers, Two s omplement 23 rithmetic ircuits and umbers (7/7) ubtract 24 ut, in this case we need a subtract operator to get negative numbers (we have an adder) nother way to take the two s complement of a number X with bits: Invert all bit of number X and add. xample: = 3 and X = 3. X = 3 = 2 inv(x) = 2, 2 2 = 2 (general proof omitted) 2 = 2 = 2 = 2 2 = 3 2 = -4 2 = -3 2 = -2 2 = - ubtract is simple to implemented with a carry propagate adder (P): Invert input signal and set in =. out in = ote that setting carry in to adds to. We can easily create a circuit where = results in and = results in - out I I

7 25 26 ombinational vs. Logic I ircuit without memory (previous lecture) Output depends only on the input. There is no memory. out in 2 3 (this lecture) epends on both current and prior input values. s a consequence, sequential logic has memory. Today, we will learn about: Latches Flip-Flips Registers cknowledgement: The structure and several of the good examples are derived from the book igital esign and omputer rchitecture (23) by.. Harris and. L. Harris. ircuit with memory We will discuss other kinds of memories in course module 4: emory hierarchy. I I istability What is the difference between these two circuits? nswer: one, but both circuits contain a cycle. What is the value of? nalysis by considering two cases: ase I: ase II: = = oth cases are stable. The circuit is bistable. I 27 otation convention: T-connections connect, four way connections do not. This circuit has 2 stable states. Hence, it is a memory that can store bit of information. Problem: We cannot decide what to store (there is no input) R Latch What is the behavior of this circuit? nalyze the 4 cases for inputs and R. R is the T signal and R is the RT signal. If and R are zero, the circuit remembers the previous value, called pre. We have a memory R pre pre Problem. The awkward case =, R= results in that both and are zero. R I 2 n R latch can be implemented using different gates. This is the abstract symbol for an R latch. Problem 2. ixes the issues of what and when updates are made. It is hard to design large circuits this way.

8 Latch 29 Flip-Flop 3 The latch solves the problems with the R latch. It has one data input, and a clock input.? R pre pre The symbol? means don t care. It is used to simplify truth tables (we can skip one row in this case). ometimes a symbol X or is used to describe don t care. ymbol describing a latch: lso called a transparent latch or level-sensitive latch. =, the latch is transparent ( flows through to ). =, the latch is opaque (the latch blocks data from flowing through). I flip-flop is edge-triggered and not level-triggered. in master slave out out ase I: = The master is transparent and the slave is opaque. in flows to. These symbols describe Flip-Flops. ondensed symbol ase II: = The slave is transparent and the master is opaque. flows to out. The flip-flop (the standard flip-flop) copies to on the rising edge, and remembers its state all other times. I Resettable and nabled Flip-Flops 3 Register 32 resettable flip-flop resets the flip-flop to when a reset signal is active. RT n enabled flip-flop has an input. Its state changes only when = and there is a raising clock edge (alled WR in the exercise). RT The line above the signal name shows that the reset signal is active low: The reset is active on. True or False physical / This resettable flip-flop is synchronously resettable, meaning that it resets on a rising clock edge. It is is not asynchronously resettable where the reset is independent of the clock. nswer: True n -bit register consists of flip-flops that share the same clock input. 4-bit register built out of flip-flops (using condensed symbol notation) : 3: bstract form of a 4-bit register. ote that registers can also have enable signals, reset signals etc. I I

9 Problematic ircuits 33 Floating Values and Tristate uffers 34 Unstable circuit. Illegal value (X) = = What is the value of? What is the value of? nswer: it oscillates. This circuit is called a ring oscillator. nswer: = X, called an unknown or illegal value. For example, when a wire is driven to both and at the same time. This situation is called contention. tristate (or three-state) buffer has high impedance if the output enable signal is not active. ommonly used in buses when connecting multiple chips. If the buffers are not enabled at the same time, contention is avoided. Z Z When the enable signal is not active, the output is said to be floating (using symbol Z). I I Output nable Register 35 Register File (/2) 36 xercise: reate a 2-bit register that has an output enable (O) input signal. If O = then is floating, else it outputs the registers state. O O register file can be used to read and write data using an address. Writing bits is done by giving write data to W3, write address to 3, and setting write enable W3 to. 2 3 W3 This is a multi-ported register file. Two read ports and one write port. Reads and writes can be done in parallel. W3 R R2 Reading bits from read data port R is done by giving an -bit read address to. ame for the second read port (R2 and 2). I I

10 Register File (2/2) 37 Register-Transfer Level - ynchronous ircuits ecoder W3 W3 an also be implemented using tristate buffers (see exercises). R 2 R2 xample: Register file with address depth = 2 (4 different addresses) and -bit words ( = ). It is hard to analyze large asynchronous circuits that contain cycles. olution: esign synchronous sequential circuits, also called designing at the register-transfer level (RTL), which means that combinational logic is combined with registers states are only updated on clock edges Which of the following circuits are using RTL design / sequential synchronous logic? ombinational Logic ircuit es, with no feedback ombinational Logic ircuit o, because of latch. ombinational Logic ircuit o, has a cycle without register in the path I I Finite tate achines (Fs) 39 imple ealy achine xample 4 ynchronous Logics can be defined as Fs oore achine ( inputs, outputs, k states) inputs ext tate Logic k next state k state Output Logic outputs clock init st 2 nd 3rd ealy achine ( inputs, outputs, k states) inputs next k ext tate state k Logic state Outputs can be directly dependent on the inputs Output Logic outputs inputs next k ext tate state k Logic fter st, 2 nd etc. positive clock edge. state Output Logic outputs I I

11 4 42 dge-triggered Timing ethodology How fast can we run a circuit? The clock period must be longer than the worst-case of delays in the circuit. delay = t prop t combinational t setup t skew Time to propagate through the flip-flop or register. inputs The longest delay in the combinational logic. ecessary time before the rising clock edge. next k ext tate state k Logic race may occur when the values of state elements depend on the relative speed of logic elements in the circuit. The worst-case delay is computed for the feedback loop through the next state logic. state ompensate for clock skew: clock signals reach state elements at different time. Output Logic outputs ummary ome key take away points: ombinational Logic vs. Logic: ombinational logic has no memory, whereas sequential logic includes memory. Latches vs. Flip-Flops vs. Registers vs. Register File Flip-flops are edge triggered, registers combine flip-flops, and register files uses addresses to access data. ynchronous vs. synchronous ynchronous esign makes design work easier. ealy vs. oore achines oth are finite state machines (Fs). oore machines depend only on the state, whereas ealy machines depend on the state and the input. Thanks for listening! I I