Double Patterning OPC and Design for 22nm to 16nm Device Nodes

Transcription

1 Double Patterning OPC and Design for 22nm to 16nm Device Nodes Kevin Lucas, Chris Cork, Alex Miloslavsky, Gerry Luk-Pat, Xiaohai Li, Levi Barnes, Weimin Gao Synopsys Inc. Vincent Wiaux IMEC 1

2 Outline Introduction & DPT goals Decomposition and coloring Design OPC & Verification Wafer results Conclusions 2

3 Outline Introduction & DPT goals Decomposition and coloring Design OPC & Verification Wafer results Conclusions 3

4 DPT Styles Line-end cutting DPT H. Haffner, 2008 Sematech Litho Forum Litho-etch-litho-etch Litho-freeze-litho-etch M. Maenhoudt, 2008 Sematech Litho Forum K. Lucas, SPIE 2008 Spacer DPT (self-aligned DPT) Inoue-san, 2008 Sematech Litho Forum 4

5 Product goals for DPT High density, performance and yield; reasonable cost and speed; low risk. Design rule values reduced 30% Low design effort overhead automated layout creation, low rework Fast to develop and deploy Fully verifiable before patterning silicon Integrates with other process/device modules Large process margin Good overlay margin Symmetric patterns uniform mask density 5

6 Outline Introduction & DPT goals Decomposition and coloring Design OPC & Verification Wafer results Conclusions 6

7 Benefits of cost-model decomposition - with user defined constraints Basic decomposition Cost model-based decomposition SPIE Vol. 6521, 2007, paper 1K Unnecessary splitting No split required 7

8 Coloring is a global problem potentially infinite range of influence 8 L. Barnes, et. al. Bacus 2009

9 Convert polygon coloring to graph coloring A DPT coloring tool looks at polygons as nodes to be colored in a network. Converts a layout coloring problem into a graph coloring problem to simplify computational solution. Connected nodes need to be assigned opposite colors (if a solution exists, e.g., no DPT coloring compliance error). Layout polygons Graph representation 9

10 Distributing by network Straightforward to distribute if many small networks But, what about huge networks? 10 L. Barnes, et. al. Bacus 2009

11 Network of connected nodes to color 11 L. Barnes, et. al. Bacus 2009

12 Pruning 12 L. Barnes, et. al. Bacus 2009

13 Color global networks 13 L. Barnes, et. al. Bacus 2009

14 Color pruned nodes 14 L. Barnes, et. al. Bacus 2009

15 Pruning w/ grafting 15 L. Barnes, et. al. Bacus 2009

16 Color global networks and grafts grafts 16 L. Barnes, et. al. Bacus 2009

17 Color pruned and grafted nodes 17 L. Barnes, et. al. Bacus 2009

18 Pre-coloring of memory arrays For coloring speed, for predetermined cutting/symmetry, enables incremental fixes - removes these nodes from the global network 18 L. Barnes, et. al. Bacus 2009

19 How well does distribution work? 1 / TAT (hrs) # CPUs Good scalability seen up to cpus 19 L. Barnes, et. al. Bacus 2009

20 Triple Patterning tests: Penrose Tiling 3-colored Rhombus Tiling Penrose Tiling was proposed by the British Mathematician Roger Penrose in A pattern is created using a limited number of tiles, yet completely covers a surface with an infinitely repeatable pattern showing no translation symmetry. Rhombus Penrose tiling has 5-fold symmetry and has been shown to be 3-colorable.[1] It is also believed to underlie some examples of 800 year old Islamic art, such as this example from the Seljuk Mama Hatun Mosque in Tercan, Turkey. [1] Rhombic Penrose Tilings can be 3-Colored, Sibley and Wagon The American Mathematical Monthly Vol 107 No. 3 (Mar 2000) pp Penrose tiling overlaid on 800 year old Islamic decoration 20 C. Cork, et. al. PMJ 2008

21 Triple patterning for 16nm contacts Allowing odd cycles can give significant pattern density advantages for contacts. Certain layout restrictions allow only three mask layers need to be used. 3-coloring is an NP-complete problem. Limits applicability by network size. Penrose Rhombic Tiling showing Multiple odd cycle loops. Requires only 3 colors for compliance. 21 C. Cork, et. al. PMJ 2008

22 Outline Introduction & DPT goals Decomposition and coloring Design OPC & Verification Wafer results Conclusions 22

23 DPT for Memory Tests Metal 1 Memory Array Memory Array Row Decoder Column Circuitry Column Decoder This layout is currently manufacturable with single patterning. Array shows multiple odd-cycles all at about minimum design space. Can double patterning be used to shrink circuit area without significant manual redesign effort? 23 B-S. Seo, et. al. PMJ 2009

24 Design Rule Guidance memory blocks Memory Array Design compliant for global scaling Effective Scaling NxN 24 B-S. Seo, et. al. PMJ 2009

25 Design Rule Guidance periphery Row Decoder Min space x >> Min space y Effective Scaling: 1xN 25 B-S. Seo, et. al. PMJ 2009

26 Design Rule Guidance periphery Min space x << Min space y Effective Scaling: Nx1 Column Circuitry 26 B-S. Seo, et. al. PMJ 2009

27 Design Rule Guidance periphery Column Decoder Non critical layout no need to decompose Effective Scaling 1x1 27 B-S. Seo, et. al. PMJ 2009

28 Short range DPT Compliance errors Type A: T-Shaped Space Can be identified by a vertex having neighbors with small space in both X & Y directions Analogous coloring conflicts existed in layouts for alternating phase shift masks Type B: U-Bend Short Range Feature bends back upon itself Here the feature causes color conflict with itself as there is no room to split at the bottom of the U-shape. 28 C. Cork, VLSI-TSA 2009

29 Longer range DPT compliance issues Type B: U-Bend Long Range Feature bends back upon itself Here the feature causes color conflict because it allows for an odd # of small spaces between features inside the U. Type C: Jogged Feature Jog creates an odd cycle with neighbor. Close packing prevents splitting at the jog to resolve the odd cycle. 29 C. Cork, VLSI-TSA 2009

30 DRC Deck for DPT errors A A A B DRC Deck Finds 80-90% of M1 DPT errors. It runs times faster than DPT. It can run on design database formats Classifies DPT errors by type. C Undetected odd cycle 30

31 Outline Introduction & DPT goals Decomposition and coloring Design OPC & Verification Wafer results Conclusions 31

32 DPT Verification: Overlap Pinches Typically from corner rounding and line-end pullback at DPT cut location. Worst overlay direction hard to estimate from design intent 32 G. Luk-Pat, et. al. Bacus 2008

33 DPT Pinching: Electrical Impact For 40nm nominal line, current density increases 2.8x with CD=30nm and 4.5x with CD=20nm No pinch CD=40nm Pinching risk at overlap, max overlay error DPT layer 1 DPT layer 2 CD=30nm at pinch CD=20nm at pinch 33 C. Cork, VLSI-TSA 2009

34 OPC for DPT Traditional Pinching resistant Reference Line Mask 1 Mask 2 Misalignment aware Mask 1 Mask 2 DPT OPC Retargeting 34 X. Li, et. al. SPIE 2009

35 Outline Introduction & DPT goals Decomposition and coloring Design OPC & Verification Wafer results Conclusions 35

36 Wafer results 22nm DPT process Metal1 wafer patterns look good Split Mask Image Post OPC Wafer Image 36

37 Wafer results DPT splits & overlaps Small overlaps and tight spaces resolve well Split Mask Image Post OPC Wafer Image 37

38 Wafer results DPT conflict impact Wafer results look good except at coloring conflicts Split Mask Image Post OPC Wafer Image 38

39 Wafer results DPT conflict impact Process margin can be small near min allowed space 17 mj Double patterning effects can create sharp failure transitions 18 mj 39

40 Conclusions LELE DPT is a likely RET at 22nm & below Intelligent decomposition & coloring benefits product goals Accurate, fast full chip coloring is difficult but possible Design for DPT compliance essential for optimal density DRC for DPT is useful but not a complete solution DPT-aware OPC makes aggressive shrinks more manufacturable. DPT-aware verification is a requirement. Wafer process results show good promise overall 40