SEMICON Europe October Pushing Lithography to the Limits. Patrick Wong imec

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1 SEMICON Europe October 2009 Pushing Lithography to the Limits imec

2 Alternative double patterning processes : ready for (sub) 32nm hp? P. Wong, M. Maenhoudt, D. Vangoidsenhoven, V. Wiaux

3 Outline Introduction Litho-Process-Litho Process Development LPL process 32nm hp First 26nm hp Conclusions imec

4 Outline Introduction Litho-Process-Litho Process Development LPL process 32nm hp First 26nm hp Conclusions imec

Main options for 32nm 22nm HP and below NA-scaling k 1 -scaling resolution = k 1. λ-scaling λ NA High index n Glass = 1.50 193nm immersion n Air = 1.

44 193nm Immersion MASK A with double patterning MASK B Extreme Mask Ultra-Violet (EUVL : 13.5 nm) Optics 1.60 1.70 NA Max. NA is limited Min.

5 Main options for 32nm 22nm HP and below NA-scaling k 1 -scaling resolution = k 1. λ-scaling λ NA High index n Glass = nm immersion n Air = 1.00 n Glass = with single exposure n H2O = 1.44 n fluid = 1.64 n H2O = nm Immersion MASK A with double patterning MASK B Extreme Mask Ultra-Violet (EUVL : 13.5 nm) Optics NA Max. NA is limited Min. index n min n Resist = NA HM POLY 0.25 NA Source Resist (k 1 < 0.3) (k 1 = ) (k 1 = ) Stops out after water Immersion Minimum L/S is 37nm Likely the only option for 32nm Not production ready imec

6 Double patterning alternatives LELE Litho 1 LPLE Litho 1 Etch 1 Process Litho 2 Litho 2 No topo Same BARC Etch 2 Etch imec

Active, Poly layers DT most intuitive for Metal

7 Litho-Etch-Litho-Etch (LELE) 2D compatible processes double line vs double trench DL most intuitive for Active, Poly layers DT most intuitive for Metal layers 32hp Pitch 90nm Overlap 30nm Nominal Gap 54nm imec

8 Motivation Why LPLE LELE expensive and time consuming Simpler process, DP can be done completely in litho cluster (depending on technique) 1 etch step less Reduced cost of ownership compared to LELE imec

9 Litho-Process-Litho-Etch Alternatives Litho1 Process trick Coat resist 2 Litho2 Etch HM removal on resist 1 Coat freezing layer Positive/Positive resist Vapour freeze Thermal freeze Implant freeze Possible in Litho cluster imec

10 Coat freezing & posi posi alternatives Coat Freezing Layer Litho1 overcoat +bake +develop Coat resist2 Litho2 Posi posi Litho1 hardbake Coat special resist2 Litho2 imec

11 Outline Introduction Litho-Process-Litho Process Development LPL process 32nm hp First 26nm hp Conclusions imec

Litho 2 CDU Litho 1 CDU Litho 2 CDU data not corrected for

12 32nm hp CDU & LWR performance for JSR coat freeze MCD51 P128 5 points per field 88 fields per wafer LWR Litho 1 LWR Litho 2 CDU Litho 1 CDU Litho 2 CDU data not corrected for reticle non uniformity NA=1.0, 0.85/0.65, Dipole 40X imec

13 32nm hp CDU & LWR performance for TOK posi posi MCD51 P128 5 points per field 88 fields per wafer LWR Litho 1 LWR Litho 2 CDU Litho 1 CDU Litho 2 CDU data not corrected for reticle non uniformity NA=1.0, 0.85/0.65, Dipole 40X imec

14 LPL CDU results through batch maps, 1 st,middle and last wafers Pattern 1 pattern1: mean = 33.5nm 3sigma = 1.4nm pattern2: mean =32.9nm 3sigma = 1.3nm Excellent through batch uniformity Pattern 2 5 points per field, 68 fields per wafer, 5mm Edge Excl. NA=1.0, 0.85/0.65, Dipole 40X imec

15 Posi posi NOR Pattern JSR LFLE 31nm Litho Etch 77nm MCD / 44nm DHP / 00OVL Mag:20k Pi mJ/cm2 45.3nm PP005Tr2 30.5mJ/cm2 40.2nm Non-optimised OPC TOK LPL Mag:150k NA=1.35, 0.8/0.5, Annular XY polarised imec

Coat freeze DP Defectivity Full Process Relative

Defects 120 100 Immersion Particles Bridging

Monitor average DPT Actual defects comparable to

residues and bridging (more process optimisation

Immersion defects different manifestation 24%

16 Coat freeze DP Defectivity Full Process Relative Comparison of Average SPT Defects with DP Defects Immersion Particles Bridging Protrusion Residues SPT Daily Monitor average DPT Actual defects comparable to average DM defects Main changes = increase in residues and bridging (more process optimisation required), reduction in immersion defects Immersion defects different manifestation 24% 29% 3% 16% 28% Immersion Particles Bridging Protrusion Residues imec

17 Outline Introduction Litho-Process-Litho Process Development LPL process 32nm hp First 26nm hp Conclusions imec

JSR Coat freeze 26nm hp Litho 2 Process Window NA=1.35, 0.747/0.

for L1 & L2 Dose Group2 Doc: processwindowhonda.

F -0.07 E 38.65 36 34 32-0.18-0.16-0.14-0.12-0.10-0.08-0.06-0.

18 JSR Coat freeze 26nm hp Litho 2 Process Window NA=1.35, 0.747/0.626, Dipole 40X MCD39 P104 L2 FEM exposed on uniform L1 70nm PR for L1 & L2 Dose Group2 Doc: processwindowhonda.pd2 : AR090357_D04_L1_L2FEM_CD_Analysed_Gen F E ~180nm DoF, 28% EL, L1 average CD 27.4nm Focus imec

19 Outline Introduction Litho-Process-Litho Process Development LPL process 32nm hp First 26nm hp Conclusions imec

20 Conclusions 32nm hp LPLE Cost effective alternative processes show good litho performance, etch feasibility demonstrated, defectivity ok Excellent through batch and batch to batch process stability demonstrated Extendibility to 2D structures ongoing 26nm hp LPLE Feasibility at 26nm hp currently ongoing Resolution capability of alternatives towards 26nm hp demonstrated Overlay and pattern collapse become critical issues. imec

21 Acknowledgements Litho: G Murdoch, P. Foubert, D Van Den Heuvel, R Gronheid., T. Vandeweyer Etch: S. Locorotondo, M. Demand, E Altimirano Sanchez. Sokudo: C Rosslee, Y Theroude. TEL: S. Hatakeyama, K. Nafus, N. Bradon, M. McCarthy. Hitachi: T. Ishimoto. ENIAC J.U. LENS Project for funding imec

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Outline. Double Patterning 11/6/17. Motivation Techniques Future of Double Patterning. Rasha El-Jaroudi November 7 th

Outline. Double Patterning 11/6/17. Motivation Techniques Future of Double Patterning. Rasha El-Jaroudi November 7 th Double Patterning Rasha El-Jaroudi November 7 th 2017 reljaroudi@utexas.edu Outline Motivation Techniques Future of Double Patterning Rasha H. El-Jaroudi 2 1 Motivation Need to keep up with Moore s Law