ABSTRACT. Keywords: 3D NAND, FLASH memory, Channel hole, Yield enhancement, Defect inspection, Defect reduction DISCUSSION

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1 Yield enhancement of 3D flash devices through broadband brightfield inspection of the channel hole process module Jung-Youl Lee a, Il-Seok Seo a, Seong-Min Ma a, Hyeon-Soo Kim a, Jin-Woong Kim a DoOh Kim b, Andrew Cross b a SK hynix Inc, 2091 Gyeongchung-daero, Bubal-eub, Icheon-si, Gyeonggi-do , South Korea; b KLA-Tencor Company, One Technology Drive, Milpitas, CA 95034, USA ABSTRACT The migration to a 3D implementation for NAND flash devices is seen as the leading contender to replace traditional planar NAND architectures. However the strategy of replacing shrinking design rules with greater aspect ratios is not without its own set of challenges. The yield-limiting defect challenges for the planar NAND front end were primarily bridges, protrusions and residues at the bottom of the gates, while the primary challenges for front end 3D NAND is buried particles, voids and bridges in the top, middle and bottom of high aspect ratio structures. Of particular interest are the yield challenges in the channel hole process module and developing an understanding of the contribution of litho and etch defectivity for this challenging new integration scheme. The key defectivity and process challenges in this module are missing, misshapen channel holes or under-etched channel holes as well as reducing noise sources related to other none yield limiting defect types and noise related to the process integration scheme. These challenges are expected to amplify as the memory density increases. In this study we show that a broadband brightfield approach to defect monitoring can be uniquely effective for the channel hole module. This approach is correlated to end-of-line (EOL) Wafer Bin Map for verification of capability. Keywords: 3D NAND, FLASH memory, Channel hole, Yield enhancement, Defect inspection, Defect reduction DISCUSSION Defect inspections are an essential part of modern semiconductor manufacturing. Inspections can be inserted after most process steps. They are non-destructive and give inline identification or feedback about problems in the manufacturing flow by identifying baseline defect types as well as excursions or special events. Comparison of inspection results from several steps can often be used to quickly locate the root cause of a problem, by identifying where an issue first occurs in the process. However if a defect inspection recipe is insensitive, excursions or even important baseline defect types may be missed. If the recipe picks up too many noise or nuisance defects, false alarms may occur or the DOI may be missed among the high number of other defects. In process development, critical decisions may not be possible because the inspection misses the difference between different processes. Also valuable inspection tool time is wasted for inspections that yield no useful results. Inspection optimization on brightfield inspection tools is essential to maximize the material contrast and therefore maximize the sensitivity to defects of interest whilst suppressing noise or nuisance defect types. Today brightfield inspection systems offer great flexibility to cover a wide range of inspection applications. To enable this flexibility there is the ability to select certain wavelengths modes, apertures, wafer orientation, focus offset, directional e- field, pixel size and multiple post processing techniques for sensitivity improvement, noise reduction or sampling. Depending on the film stack, pattern of interest and defect types of interest, different combinations of modes and apertures can provide increased sensitivity to defects of interest or suppression of wafer noise. A rigorous inspection setup methodology is typically required in device development where a new device and process integration scheme are often encountered and previous inspection learning for a particular layer can only be used as a starting point, requiring verification and quantification of its performance in comparison to other modes. Probably the Advanced Etch Technology for Nanopatterning II, edited by Ying Zhang, Gottlieb S. Oehrlein, Qinghuang Lin, Proc. of SPIE Vol. 8685, 86850U 2013 SPIE CCC code: X/13/$18 doi: / Proc. of SPIE Vol U-1

2 most important aspect of recipe setup on a brightfield inspection system is to ensure the inspection tool is able to see the correct structures of interest with good contrast and resolution. The first step is to identify potential inspection modes and compare the signal of the defects of interest to the background wafer noise. Through this signal to noise analysis the best mode for a particular DOI / layer stack can be selected. Figure 1 shows such a methodology where multiple initial inspection modes are run as hot scans and then, after defect review, best modes can be selected for re-scan and a final mode selected for optimization. Setup Base Recipe Determine Initial Modes OSTS &Hot Scan Initial Modes Sample Defects for SEM Review SEM Review Sample Defects for Optics Selection Camera Down-Select Optics Selector Selection Hot Scan Best Modes Sample Defects for SEM Review SEM Review Final Optimization w/ ido NEF Run multiple Lots / Production Final Optimization Figure 1: Engineering / Process development inspection optimization flow Figure 2 below shows an example of this mode selection to maximize one of the key DOI types at the channel hole formation classified as a bunker defect. Proc. of SPIE Vol U-2

3 Mode A Mode B Mode C Mode D Mode E Mode F Mode G Figure 2: Mode selection to maximize sensitivity of bunker defects Mode A can be seen to provide both the best resolution of the pattern as well as the highest signal to the defect of interest and through this rigorous methodology can be identified as the best mode. 3D NAND devices and processes bring some new and unique inspection and review challenges, due to the nature of the devices, materials and structures involved. The channel hole is a key patterning step in the 3D NAND cell formation as this becomes the vertical channels for 16, 32, 48 or even 64 NAND cells stacked vertically [1]. The structure may be several microns high and therefore many of the defects of interest such as underetch or embedded defects can be buried. The channel hole under discussion in this paper is the key patterning step to form the hole into which the gate dielectric and channel are deposited. The nature of the device architecture and the materials involved make not only inspection a challenge but also defect verification, as we can no longer adequately classify all defects of interest by SEM review alone. The traditional optimization flow relies on SEM review for identification of defects of interest, as typically previous layer defects are not considered to be of interest. Here we must also consider real defects that are optically detected but SEM non-visible. In this case optical or defect patch review (a patch being the gray level image captured by the inspection tool) becomes an essential step in the defect optimization flow. Physical failure analysis has been used during development to confirm these defects types. Figure 3 below shows such a real, optically detected defect that was SEM non-visible and TEM cross section showed to be a buried defect of interest. Proc. of SPIE Vol U-3

4 Figure 3: Optically detected, SEM non-visible, buried defects are potential DOI for 3D NAND The final inspection for the 3D NAND development flow at SK hynix, the channel hole after clean inspection (ACI) step, was optimized to maximize both capture of surface defects / patterned defects verified by SEM as potential issues from the patterning process as well as these buried defects. Of particular interest were defects caused by underetch of the channel holes added during the channel hole patterning process. Also of interest during process development are any wafer level signatures that can be detected, as these provide clues for the process team to reduce initial defect issues and achieve optimized unit processes faster. The optimum inspection modes were the longer wavelength modes available on today s brightfield inspection tools, as predicted by theory to penetrate the 3D NAND cell stack, as penetration depth increases with wavelength. Investigation in this case showed the need for inspection modes selecting specific bands with broadband illumination to capture yield limiting defects, and for the channel hole module a mode was identified that best captured the defect types of interest. Initial example wafers showed a ring signature. This correlated well both at wafer level and die level to end of line electrical test results as shown in Figure 4 & Figure 5. Figure 4: Wafer level signatures seen post wafer inspection (PWI) - channel hole ACI and post electrical test Proc. of SPIE Vol U-4

5 PWI Defect Map Wafer Bin-Map Figure 5: Die level signatures seen post wafer Inspection (PWI) - channel hole ACI and post electrical test In addition, noise suppression techniques were essential for maximizing the capture of defects of interest. The mode selection and noise suppression requirements were confirmed with simulation studies both at SK hynix and KLA-Tencor to provide signal to buried defects of interest. Figure 6 shows simulation results comparing the expected signal for a buried defect between two of the inspection modes investigated. Mode B Mode A Figure 6: Simulation confirmation for buried DOI detection comparing Mode A & Mode B with noise suppression For semiconductor device development and manufacturing, both litho and post etch (typically post final clean) are two of the most critical inspection steps, and have been the focus of much of the brightfield inspection effort since inspection tools were introduced into the fab for line monitoring. These two processes are often the cause of the majority of patterning defects (though previous layer defects can make a significant contribution in some cases). As part of the inspection a comparison between post develop and post etch defectivity for the channel hole module was made. After develop inspection (ADI) is performed on product wafers after photoresist coating, exposure and development. It is used typically to try and identify both gross patterning issues as well as subtle patterning defects that can impact product yield or device reliability. Inspecting product wafers at ADI instead of ACI, where the wafer has been etched and Proc. of SPIE Vol U-5

6 cleaned) has several advantages. It shortens the feedback loop to litho-specific issues, allowing potential re-work and lowering yield risks associated with the litho process. There are multiple applications related to ADI, in addition to the production monitoring or engineering source identification applications we are utilizing here: there are also haze monitoring, scanner or reticle qualification / re-qualification, photo cell monitoring and process window qualification. However, because of the challenges associated with ADI inspection (especially lower contrast and prior level nuisance defects that could be seen through the resist coat), fabs often do not monitor ADI especially during process development, but instead focus only on the ACI step only. This can lead to slower learning of critical defect types and their potential sources or, in the worst case, wrong conclusions on potential defect sources. A study was performed comparing ADI and ACI results, to identify sources of baseline defect types in the channel hole formation module. ACI inspection results identified the defect spatial distribution of interest, and review showed both closed / misshapen contacts as well as bunker defects in the pareto. The source of both of these defect types were of particular interest to the Defect, Yield enhancement and Process teams in the optimization of the 3D NAND process. Figure 7: ACI partitioning result spatial signature of closed / misshapen channel holes A study of the ADI inspection step showed the same spatial distribution and identified the cause of this distribution to be related to resist coat (Figure 8), with the majority of defects classified as missing or misshapen channel holes (bad coating in the pareto). Figure 9 shows the defect source pareto, which provides the relative contribution by defect type for the two inspection steps of interest. This pareto chart can be used to visualize the relative number of defects at a final inspection step that were previously identified at one or more inspection steps earlier in the process. This analysis confirms the majority of patterning defects (bad coat) originated from the litho step.»oj -.P71711=74 il11fi1-j frï.iy Figure 8: ADI wafer distribution correlating to signature of interest Proc. of SPIE Vol U-6

7 80 Dd. type Process Coating Bunker Bomb Particle SNV Defect count 70 Defect count AC I Defect cou nt AD I Bomb Particle Figure 9: Defect source pareto for ADI and ACI The defect source pareto also confirms that the bunker defects are not present at ADI and are added in the post ACI pareto, thus it was confirmed that the bunker defects were associated with the channel hole etch process. CONCLUSIONS By utilizing best optical modes and noise reduction techniques available on broadband brightfield inspection tools, critical defect spatial distributions and defect types affecting the complicated stack structure of a 3D NAND device in the channel hole formation module were identified inline and compared to end of line electrical results. Physical failure analysis verified the defects as arising from both surface patterning and buried defects in the 3D NAND device structure. This method for defect learning, together with confirmation of the defects yield impact allowed the defect team to identify and fix the source of these issues, allowing rapid ramp of the prototype devices. This optimization relied critically on the longer wavelength modes available on the broadband optical inspection tool. Simulation studies of long wavelength modes confirmed the effectiveness of this approach for further increasing sensitivity to these critical buried defects. REFERENCES [1] Yoon Kim, Jang-Gn Yun, Se Hwan Park, Wandong Kim, Joo Yun Seo, Myounggon Kang, Kyung-Chang Ryoo, Jeong-Hoon Oh, Jong-Ho Lee, Hyungcheol Shin, Byung-Gook Park, Three-Dimensional NAND Flash Architecture Design Based on Single-Crystalline Stacked Array IEEE Transactions on Electron Devices, Vol. 59, No. 1, January 2012 Proc. of SPIE Vol U-7