UNlVERSITI MALAYSIA PERLIS. Peperiksaan Semester Pertama Sidang Akademik Januari 2013

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UNlVERSITI MALAYSIA PERLIS Peperiksaan Semester Pertama Sidang Akademik 2223 Januari 23 EKT22 - Digital Electronics II [Elektronik Digit IT] Masa : 3jam Please make sure that this question paper has

1 UNlVERSITI MALAYSIA PERLIS Peperiksaan Semester Pertama Sidang Akademik 2223 Januari 23 EKT22 - Digital Electronics II [Elektronik Digit IT] Masa : 3jam Please make sure that this question paper has ELEVEN () printed pages including this front page before you start the examination. [SUa pastlkan kertas soatan Inl mengandungl SEBELAS () muka sural yang bercetak termasuk muka hadapan sebetum anda memutakan peperlksaan ;n;.] This question paper has TWO (2) parts. There are PART A and PART B. {Kertas soatan Inl mengandungl DUA (2) bahaglan. Terdapat BAHAGIAN A dan BAHAGIAN B.] PART A: Answer ALL questions [BAHAGIANA : JawabSEMUA soatan.] PART B : Answer any TWO (2) questions only. [BAHAGIAN B : Jawab DUA (2) soatan sahaja] Di"tak old Unit Peperi!uatm &: Pengijazalttzn. Bahagian PfirtgU'll3lDI Alcodemik, Jabala" P~ndqftar.

2 -2- PART A [BAHAGlAN A} Question [Soalan I}, a) Briefly explain the concept of 'Clock Gating'. [T.,angkan s.ca,a,ingkas kons.p 'Selak D.nyul'.} [2 marksl markah] b) Discuss the advantage and disadvantage of serial and parallel adders, [B/ncangkan kel.b/han dan kel.mahan penambah sesi,i dan sela,i.} [4 marks! markah] c) The serial adder in Figure I uses TWO (2) 4-bit registers. Register M holds and Register N holds, The carry flip-flop is initially reset to O. Show the data contain in Register M, Register N, the carry flip-flop and sum of the Full Adder for each of the FOUR (4) shifts (Tl, T2, T3, and T4). Assume TO as initial state. [Penambah sesi,i dalam Rajah I menggunakan DUA () daftar 4-bit. Dqftar M mempunyai dala I I I dan Dajla, N memput)lai dala O. Fli~jop p.mbawa di,esel ke pada keadaan awal. Tunjuk kandungan dala dalam Dajlar M, Dajlar N.ji~jlop pembawa dan hasillambah Penambah Penuh selepas seliap atifakan bagi EMPAT (4) kali anjakan (TI, T2, T3 dan T4). Andaikan TO adalah keadaan usal.} Rc5el - ~C Clear 5 ReForM SRG4 SO FA X s- Shift Clock {) I '" / Serial input Reset..- p.e aear SI RegisterN SRG4 Figure {Rajah / SO t-- I y,-- Z C f-- Full Adder Carry D Qo - C R -.--.!i Reset [6 marks! markah]... 3/- DicetaJc okh Unit Peperilciaan & PengijazaMn. Btlhagian Pengunutm AluJdemik, JabatQJI Pendaftar.

-3- d) The following Register Transfer Language (RTL) is given as: [Bahasa Pemlndahan Dajlar (RTL) dlherlkan aepertl herlkut:] # Using multiplexer and basic logic gates, design the complete block

3 -3- d) The following Register Transfer Language (RTL) is given as: [Bahasa Pemlndahan Dajlar (RTL) dlherlkan aepertl herlkut:] # Using multiplexer and basic logic gates, design the complete block diagram including the control variables of KI and K2 for these registers implementing the conditional register transfer statement. [Menggunakan pemultiple/cs dan get-get loglk asas, rekahenjuk gambarajah blok yang lengkap termasuk pembolehubahan kawalan KJ dan K, herdasarkan penyataan pemlndahan dqf/ar yang diherikan. [8 marksl markah]...4/- Dicelak oieh Unit Peperllaaall & P... g/jazohtljl, Bohogla. Pe.gurus"" Akademll; Jabalan Pendaftar.

4 -4- Question 2 [Soalan2] State diagram provides a means for describing the behavior of sequential circuits. Refer to the state diagram in Figure 2, Xl and X2 are inputs to the circuit, while Zl and Z2 are the outputs. Assume)nitial state is SO. [Rqjah keadaan menyediakan cara untuk menerangkan perlakuan lilar jujukan. Rujuk kepada rajah keadaan pada Rajah 2. Xl dan Xl merupalcan masukan-masukan kepada /liar. semenlara Zl dan Z2 merupakan keluaran-keluaran lilar. Anggapkan keadaan awaj ialah pada SO.],, Figure 2 [Rqjah 2J a) Distinguish whether it is a Mealy or Moore model with supporting reason. [TenJui<an samada tanya model Mealy alau Moore tkngan sokongan hujah.] [2 marks/ markah) b) Produce the corresponding state table. [Hasi/kan jadual keadaan selaranya. J [6 marks! markah) c) Design the logic circuit using D flip-flops. Produce the Boolean equation for every output. [Rekaben/uk lilar logik tkngan menggunakan flip-flop D.HasilkLzlI persamaall Boolean bagi setiap keluaran.] [6 marksl markah) d) Develop a corresponding Algorithmic State Machine (ASM) chart. [Banguukan carta 'Algorithmic Stale Machine '(ASM) selaranya] [6 marks! markah). 5/- Dicetak oielt Unit Peperi!aaan & Pengijazahan, Sahagian Pengurusan A/cademik, Jabatan Pendqftar.

5 -5- Question 3 [Soalan3J a) State TWO (2) types of memory. Explain the main difference between these two types. [Senarailean DUA {2} jeni. ;;,gatan. Teranglean perbezaan ulama di an/ara kedua-dua jenis ingalan ini.j [2 marksl markah] b) Construct the complete block diagram for 256K x 6 RAM by using a decoder and the RAM chip in Figure 3. [Blna gambarajah bioi< lengleap bagi 2S6K x 6 RAM dengan menggunakan penyahkod dan cip RAM dalam Rajah 3.J 64K x 8 RAM Input data Address 8 6 DATA ADRS V 8 Output dala Chip select CS ReadlWlite R/W Figure 3 [Rajah3j [8 marksl markah] c) A system is to have the following set of register transfers, implemented using buses: [Satu sislem mempunyai kampulan pln.dahan daj/ar seperli berikal yang diimplemen/lean mengunakan bus:j CA: RI.-RO CB : RO.- RI, Rl.- RO CC : RI +- Rl, RO +- R2 Design a detailed logic diagram of hardware that implements a single bit of these register transfers. Consider CA, CB and CC as inputs for selector of multiplexer. [Releabentuk rajah logik lerperinci bagl perleakasan yang mengimplemenlasilean bil tungga/ pemlndahan daflar int. Perllmbangkan CA. CB dan CC sebagai masukan kepada pemilih un/uk pemullip/ej:s J [ markslmarkah]... 6/- DlcefDlc okh Unit Peperi/aaan ci: Peng{fazahan. Bahagian Pengunuan AkademiJc, Jabalan Pendafta,..

6 -6- PARTB [BAHAGIAN B} Question 4 [Soalan4} a) Define Register Transfer Language (RTL). [Definisikan Bahasa Pemindahan Daflar.j [2 markslmarkah] b) In Figure 4, there are THREE (3) n-bit 2-to-l multiplexers, each with its own select signal. Each register has its own load signal. Interpret the corresponding register transfers for the given control signals in Table. Redraw Table in answer sheets. [Bagl Rajah 4. terdopat TIGA (3) n-bit 2-to-l pemultipleks. setiap satu mempurryai isyarat pemllih sendiri. Setlap dqflar mempurryai isyarat masukan tersendiri. Kenaipasti pemindahan daflar yang berkaitan bagi isyarat-isyarat kawalan yang diberikan dalam Jadual. Lukis semulajadual J dafam kertasjawapan.} r+ r S 2-- MUX a, Select S()Sl S2 n r RO Load LClLIU _! S 2-t- MUX ~ I; Rl - ~ ~ S 2-- MUX, ; i R2 Figure 4 {Rajah ~J... 7/- Dicetak 4 Unit Peperibaan d: Pengfjazahan. &hagian Pengunutlrl Akodemilc, Jabtztan Pendqftar.

-7- " Table {Jaduallj Select Load SO SI S2 LO Ll L2 I I I I I I I I I I I I I Register Transfer [4 marks/markah] c) Using a synchronous, FOUR (4}-bit counter with a synchronous LOAD, design a

7 -7- " Table {Jaduallj Select Load SO SI S2 LO Ll L2 I I I I I I I I I I I I I Register Transfer [4 marks/markah] c) Using a synchronous, FOUR (4}-bit counter with a synchronous LOAD, design a Modulo-N counter with requirement stated below: {Menggunakan pembilang aegerak EMPAT (4)-bit dengan masukan aegera!, rekabenjuk satu pembllang Modulo-N dengan syarat berikut:] i) Synchronously preset "S" on RESET [Preaet segerakpatkl "8" apabi/a RESET} ii) LOAD "S" on terminal count "2" [Masukkan "8" apabl/a terminal pembi/ang "2"] [4 MarkslMarkah] d) Design an ALU that performs the following operations: {Rekabentuk ALU yang melaksanakan operasi-operasl berikut:] AvB B+ A+B sla A+B+l B A$B A I\B The result of the above design should be the logic diagram for a single state of the ALU. The design should have only a single carry line between stages and three selection bits. [Hasi/ rekabenjuk odalah sebagai rajah logik bagi salu tahap ALU. lanya mesti mempunyai hanya satu baris pembawa di anjara tahap-tahap dan t/ga bit pemillh.] [ markslmarkah]... 8/- Dicewk oieh Ullil Pep<rlluotm.I PengijO%lJhan, /Jahagitm P,ngtmI8OII Aka</lrnik,.Jabaton Pendqftar.

-8- Question 5 {SaolanS},. a) Discuss the '4-bit Binary Ripple Counter' with the aid of a schematic diagram. (Bincangkan mengenai 'Pembilang Riak Binari 4-bit' dengan bantuan rajah skematlk.

8 -8- Question 5 {SaolanS},. a) Discuss the '4-bit Binary Ripple Counter' with the aid of a schematic diagram. (Bincangkan mengenai 'Pembilang Riak Binari 4-bit' dengan bantuan rajah skematlk.] [4 markslmarkah] b) Refer to the Algorithmic State Machine (ASM) chart of a control unit in Figure 5, There are three states, two inputs, Xl and X2 and two outputs Zl andz2. (Rujuk kepada rajah Algorithmic Slate Machine (ASM) bagi suatu pengawaj palla Rajah S. Terdapat tiga keadaan, dua masukan, X dan Y dan dua keluaran Zl dan Z2.] Reset so Figure 5 [Rajah 5J i) Derive the corresponding state diagram. [Terbltkan rajah keadaan setaranya.] [5 markslmarkah] ii) Produce the corresponding state table. (Hasilkan Jadual keadaan setara.nya. J [5 markslmarkah) iii) Implement the ASM chart in Figure 5 by using one flip-flop per state. (lmplemenlasikan carla ASM di dalam Rajah S dengan menggunakan satuj/ip-j/op bagi satu keadaan.] [6 markslmarkah]... 9/- DicekJk ofeh Unit Ptperlksaan & Ptngliazahan. Bahag;a. P.ngIIIIMlIt Akadtmik. Jabatan P.ndqftor.

9 -9- Question 6 [Soalan6] a) Construct a basic block diagram for memory. [Bina gambarajah blok asas bagi ingalan.j [2 markslmarkah] b) With reference to the Control Word structure and the Encoding of Control Word table as specified in Appendix, obtain the l6-bit control word to implement each of the following microoperations : [Merujuk kepado struktur 'Control Word' don jadoal pengekod 'Control Word' seperti di da/am Lampiran, dopatkan 'Control Word' J6-bi/ bagi melaksanakan setlap mikrooperasi yang berikuj:] i) R5 +-- sr R5 ii) R7+--R4-2 [2 markslmarkah] c) Use Appendix as reference. The width of registers shown is 8-bits. Each register contains the same value as their register number (e.g. register R5 contains 5 in hexadecimal) before the execution of a control word. Determine the new register content as a result of the execution of each of the Control Words set given below: [Gunakan Lamplran sebagai rujukan. Sai. sellap dqftar yang ditunjukan adolah 8-bit. Setiap dqftar mengandungi nilal yang sama dengan nombor doftar (conlohnya, daj/ar R5 mempunyai nllai 5 dolam heksadesimaj) sebelum perlaksanaan 'Control Word'. Tentukan kandungan daftar baru hasi! perlaksanaan seliap 'Con/roT Word' yang diberikan di bawah:] i) Set A: ii) Set B: iii) SetC: I [6 markslmarkah] d) Design a logic schematic using D flip flop and a multiplexer (MUX) of one typical stage for a bidirectional shift register with mode of selection inputs SO, S I and S2. The register is to be operated according to the functions in Table 2. [Rekabenruk salu lilor logik menggunakan jti~jtop D dan salu pemulipleks (MUX) bagi dqftar anjak dwi-arah dengan masukan pitlhan mod SO, SJ dan S2. Daj/ar perlu beroperasi seperti jungsi dalam Jadual 2.]... /ll D/«tak.Ieh Unit Pepe,iJuaan & Pengyazaharo, Sahagian Penguru.san Akodemi/r, Jabata. Penda/lar.

Table 2 {Jadual2j SO 8 O S2 Register Operation {Operasi Daltar] No change [Tiadaperubahan} Shift right [Arifak /canan} Clear register {Padam daftarl Load parallel data [Muat daftar selari} Shift left

10 Table 2 {Jadual2j SO 8 O S2 Register Operation {Operasi Daltar] No change [Tiadaperubahan} Shift right [Arifak /canan} Clear register {Padam daftarl Load parallel data [Muat daftar selari} Shift left JAJlak kiri} Set register [Set thftar} No change [nada perubahanl Complement output [Keluaran peleng/cap} [ marksimarkahj li- Diatale ' Unit Pep<rilaotm & Pengijazalran, Bahagiml PetrglUlW»l &d<mik, Jaboiml P<JfdqfIar.

Appendix Lampiran I 5 4 3 2 9 8 7 6 5 4 3 2 M I AA I BA : FS I~~I DA- D Address ~ AA - A Address BA-BAddress MB-MuxB FS - Function Select MD-MuxD Il: RW - Register Write 6-bit Control Word Structure

11 Appendix Lampiran I M I AA I BA : FS I~~I DA- D Address ~ AA - A Address BA-BAddress MB-MuxB FS - Function Select MD-MuxD Il: RW - Register Write 6-bit Control Word Structure /Struktur 6 blt 'Control Word'j DA,AA. BA MB FS MD Functlon Code Function Code Functlon Code Function Code Function Code RO R R2 R3 R4 RS R6 R7 Register F+--.A. Constant F+--,A, + F+--,A,+B F+--.A+B+I F+--.A+B F+--.A +B+ I F +--A - F +--.A F +--.A I\B F+--AvB F+--.AeB F +--A loll F+--B F+--srB F+--slB Function Data In No write Write Encoding of Control Word Table [Jadual Pengekod 'Con/rol Word'j Dice/ale oleh U"lt Peperikloan & Pengijazahan. Sahagian Pengurwan AkDdemlk. Jabatart PendaftDr.

UNIVERSITI MALAYSIA PERLIS. DMT 233 Digital Fundamental II [Asas Digit II]

UNIVERSITI MALAYSIA PERLIS. DMT 233 Digital Fundamental II [Asas Digit II] UNIVERSITI MALAYSIA PERLIS Peperiksaan Semester Pertama Sidang Akademik 2013/2014 Oktober 2013 DMT 233 Digital Fundamental II [Asas Digit II] Masa: 3 jam Please make sure that this question paper has FIFTEEN