FPGA Development Techniques. Wednesday November 3, 2004 Polytech Orléans

Transcription

1 FPGA Development Techniques Wednesday November 3, 2004 Polytech Orléans

2 Agenda Static Timing Analysis Constraining an FPGA design and ensuring it meets performance requirements On-Chip Debugging Using a logic analyzer implemented inside the FPGA to quickly debug at full system speed Power Estimation & Analysis Obtaining an initial power estimate before starting your design & analyzing detailed results after implementation FPGA Development Techniques 2

3 Outline Static Timing Analysis Introduction Review of Basic Constraints When to Use Advanced Constraints Handling Multiple Clock Domains Analyzing Design Results Demonstration of Constraints Editor & Timing Analyzer to Floorplanner Cross-Probing On-Chip Debugging Power Estimation & Analysis FPGA Development Techniques 3

4 What are Timing Constraints for? The implementation tools do not try to find the placement & routing that will obtain the fastest speed Instead, the implementation tools try to meet your performance expectations Performance expectations are communicated with timing constraints Timing constraints cause the tools to improve the design performance by placing logic closer together so shorter routing resources can be used FPGA Development Techniques 4

5 Without Timing Constraints This design had no timing constraints or pin assignments entered with the design when it was implemented Note the logical structure of the placement and pins Xilinx recommends that you verify that your timing constraints are realistic before completing the functional verification of your design This design has a maximum system clock frequency of 50 MHz FPGA Development Techniques 5

6 With Timing Constraints This is the same design with three global timing constraints entered with the Constraints Editor It has a maximum system clock frequency of 60 MHz Note how most of the logic is placed closer to the edge of the device, where the pins have been placed FPGA Development Techniques 6

7 How do I add Constraints? Start the Constraints Editor GUI from the Process window will create a new Implementation Constrains source file and run the TRANSLATE step Can also be invoked at the command line by typing constraints_editor Or edit the constraints file a text file which contains constraints identified by a.ucf suffix FPGA Development Techniques 7

8 Constraints in the Design Flow Text Editor Text Editor EDIF or or NGC Synthesis VHDL 1. Enter Timing Constraints here and Physical Constraints here (not covered today) 3. Used by the implementation tools 4. Analyze results here FPGA Development Techniques 8

9 Specifying Constraints Usually written (automatically or by hand) in a separate file, one per project Documented in the Constraints Guide see doc\usenglish\books\docs\cgd\cgd.pdf or Constraints can also be directly embedded in source code or IP core netlists FPGA Development Techniques 9

10 Outline Static Timing Analysis Introduction Review of Basic Constraints When to Use Advanced Constraints Handling Multiple Clock Domains Analyzing Design Results Demonstration of Constraints Editor & Timing Analyzer to Floorplanner Cross-Probing On-Chip Debugging Power Estimation & Analysis FPGA Development Techniques 10

11 The PERIOD Constraint NET CLK PERIOD = 10 ns ; FPGA CLK This says, Data has 10nS to get from this flip-flop, to another flip-flop, here All synchronous elements (RAMs, FFs, MULTS) are identified by forward propagation of the CLK net. Note that I/O Pads are not covered by the PERIOD constraint! FPGA Development Techniques 11

12 The OFFSET IN - BEFORE Constraint OFFSET = IN 3nS BEFORE CLK ; UPSTREAM DEVICE FPGA Din CLK CLK This says, Data will be valid here, 3 ns BEFORE the clock arrives here The tools attempt to control internal data and clock delays for all flip-flops setup requirement (TsuFF). FPGA Development Techniques 12

13 The OFFSET OUT - AFTER Constraint OFFSET = OUT 4nS AFTER CLK ; FPGA CLK DOWNSTREAM DEVICE This says, Data will be valid here, 4 ns AFTER the clock arrives here The tools attempt to control internal data and clock delays to meet this clock-toout requirement. The downstream device s setup time and the board delay will help you set this value. Using a DLL or DCM can help improve this number! FPGA Development Techniques 13

14 The PADS to PADS Constraint TIMESPEC "TS_P2P" = FROM PADS TO PADS 15 ns; UPSTREAM DEVICE FPGA DOWNSTREAM DEVICE This says, from the input pad, Data has 15 ns to get to the output pad This constraint is required to constrain combinatorial logic paths (ie, don t contain any synchronous elements) within the FPGA. Purely combinatorial paths, while easily implemented with consistent timing in CPLDs, should be used with caution in FPGAs. FPGA Development Techniques 14

15 Outline Static Timing Analysis Introduction Review of Basic Constraints When to Use Advanced Constraints Handling Multiple Clock Domains Analyzing Design Results Demonstration of Constraints Editor & Timing Analyzer to Floorplanner Cross-Probing On-Chip Debugging Power Estimation & Analysis FPGA Development Techniques 15

16 Using Advanced Constraints Review of Basic Constraints showed how to fully constraint a simple, synchronous, single clock design Most real designs are more complicated than this! Many designs may require some of the following: Specifying different setup and clk-to-out values for different I/O pins on the same clock domain (ie microprocessor I/F) Defining multi-cycle paths (useful for clock enables) Ignoring some paths which aren t timing critical Clocks on non-global routing Forwarding clocks off-chip FPGA Development Techniques 16

17 OFFSET IN & OUT Revisited For certain interfaces, I/O pins in the same clock domain may have different setup & hold requirements Continue to use general OFFSET IN & OUT for entire clock domain, but add exceptions: OFFSET = IN 3 ns BEFORE CLK ; NET FAST_IN OFFSET = IN 1.8 ns BEFORE CLK ; NET SLOW_IN OFFSET = IN 4.2 ns BEFORE CLK ; Specific exceptions will take precedence over general constraint, without duplication in the timing report Wildcards, for example ADDR_BUS[*] can be used... FPGA Development Techniques 17

18 Creating Timing Groups To allow for more complex timing constraints, the notion of groups of elements is required Since logic paths start and stop at synchronous elements, the following keywords can be used: FFS LATCHES RAMS All flip-flops All latches All RAM elements Input & outputs can also be grouped: PADS All I/O pads Can be used globally and/or to create sub-groups FPGA Development Techniques 18

19 Slow Exceptions Slow Exceptions are FROM:TOs that define a different delay for portion of the design. The majority of the design is covered by a PERIOD constraint. Example 1: Using FROM:TO s only -- OK, but not best method 30 ns 60 ns IN CLK D Q D Q D Q FROM:flop1:TO:flop2:30 FROM:flop2:TO:flop3:60 OUT Example 2: Using PERIOD with a FROM:TO Slow Exception -- BEST, faster par & trce 30 ns 60 ns IN CLK D Q D Q D Q NET CLK PERIOD=30 FROM:flop2:TO:flop3:60 OUT FPGA Development Techniques 19

20 Multi-Cycle Delays Use INST to create groups by matching the symbol name NET CLK PERIOD = 10 ; INST CNT16/U1 TNM = CNT50 ; INST reg0 TNM = MYREGS ; TIMESPEC TS_MYBUS = FROM : CNT50 : TO : MYREGS : 20 ns ; TS_MYBUS D D Q reg0 Q reg1 MY_REG_0 MY_REG_1 CNT16 D Q reg2 D Q reg3 MY_REG_2 MY_REG_3 FPGA Development Techniques 20

21 FROM : TO Syntax Details TIMESPEC TS_name = FROM:group1:TO:group2:value; TIMESPEC defines the type of specification TS_name must always start with TS. Any alphanumeric character or underscore may follow Group1 designates the origin of the path Group2 designates the destination of the path Value is in ns by default. Other possible values are MHz or another time spec like TS_C2S/2 or TS_C2S*2 FPGA Development Techniques 21

22 Ignoring Selected Paths Why use Timing IGnore (TIG)? Not all paths in designs require timing specifications Decreases competition for routing resources When non-critical timing paths are included in time specifications, more important paths may be slower and may not meet time specifications The TIG constraint ignores all nets that fan forward from the specified element The TIG constraint prevents any constraints from being applied to the specified path FPGA Development Techniques 22

23 TIG Example UCF Syntax: NET NETC TIG ; NETA NETB NETC NETD NETC shown in the diagram is ignored. This will remove all constraints on 3 different paths NETA, NETB and NETD which overlap some parts of NETC s path will not be ignored FPGA Development Techniques 23

24 Syntax: TIG Attribute {NET PIN INST} name TIG = group1 [ group2, ]; name : element, net, or instance that is to be ignored group_name : optional field which ignores the net, instance, or pin in the listed group All paths that fan forward from the net or instance will not have any timing constraints applied to them The paths will be treated as if they don t exist Paths can be specified between & through groups, ie: TIMESPEC ts_ignr = FROM groupa THRU groupb TO groupc TIG ; FPGA Development Techniques 24

25 Clocks on non-global Routing Clocks which don t use BUFGs can be skewed INPUT 3.1 DQ_A 3.1 D Q_B 3.3 D Q_C CLOCK A B C This shift register will not work because of clock skew! 2 cycles Clock 3 cycles A & C Clock B Clock Q_A Q_B Expected operation Q_A Q_B Clock skewed version Q_C Q_C FPGA Development Techniques 25

26 Minimizing Clock Skew Global Clock networks, using GCK pin and BUFG, distribute clocks with minimal skew In the case of clocks on non-global routing, two constraints can help minimize skew: NET net_name USELOWSKEWLINES ; NET net_name MAXSKEW = 1 ns ; USELOWSKEWLINES will instruct the tools to use backbone local clock routing resources MAXSKEW will try to balance the clock delay FPGA Development Techniques 26

27 Forwarding Clocks off-chip When sending a clock off-chip, general purpose routing will be used, even if the clock is on BUFG To properly constrain this path, use the following: NET net_name MAXDELAY = 3 ns ; MAXDELAY can be used for any timing critical nets, not just clocks The Virtex-II/-II Pro/-4 & Spartan-3 IOB with its integrated DDR register provides a very effective way to send clock(s) off-chip with very little skew FPGA Development Techniques 27

28 Timing Constraint Priority Within a particular source: Highest Priority Lowest Priority FPGA Development Techniques 28

29 Tool Runtime Reduction Tips Limit number of time constraints Add PERIOD and OFFSET constraints through Xilinx Constraints Editor, instead of doing Advanced Analysis Consolidate similar timespecs to limit the number of time constraints Especially slow exceptions (TIG) Individual OFFSETs for every net with the same requirement Be aware of duplicate constraints created by synthesis tools (.ncf files) Remove FROM:TO constraints between related clocks Use Global constraints, then grouped or net constraints Limit analysis of unconstrained paths Group related I/O pads together and place early on Use higher placement effort, lower router effort FPGA Development Techniques 29

30 Outline Static Timing Analysis Introduction Review of Basic Constraints When to Use Advanced Constraints Handling Multiple Clock Domains Analyzing Design Results Demonstration of Constraints Editor & Timing Analyzer to Floorplanner Cross-Probing On-Chip Debugging Power Estimation & Analysis FPGA Development Techniques 30

31 Constraining Between Multiple Clock Domains By default, different clock domains are assumed to be unrelated (ie, no constraint applied between domains) Define clock groups: NET CLK_A TNM = A_GRP; NET CLK_B TNM = B_GRP; Define timing constraints: TIMESPEC TS_CLKA = PERIOD A_GRP 20; TIMESPEC TS_CLKB = PERIOD B_GRP TS_CLKA*2; TIMESPEC TS_CLKA2B = FROM: A_GRP: TO: B_GRP: 20; D Q D Q D Q CLK_A D Q OUT1 CLK_B FPGA Development Techniques 31

32 Constraining Between Multiple Clock Domains When generating clocks using a DLL or DCM, the phase & frequency relation will be determined automatically and handle the clock domain crossing To constrain clocks which have a phase relation but which enter using separate pins, use the following constraints: TIMESPEC TS01 = PERIOD clk0 10 ns; TIMESPEC TS02 = PERIOD clk180 TS01 PHASE + 5 ns; FPGA Development Techniques 32

33 Outline Static Timing Analysis Introduction Review of Basic Constraints When to Use Advanced Constraints Handling Multiple Clock Domains Analyzing Design Results Demonstration of Constraints Editor & Timing Analyzer to Floorplanner Cross-Probing On-Chip Debugging Power Estimation & Analysis FPGA Development Techniques 33

34 Analyzing Design Results Place & Route Report lists all constraints and the obtained results: Timing Score: WARNING:Par:62 - Timing constraints have not been met. Asterisk (*) preceding a constraint indicates it was not met Constraint Requested Actual Logic Levels * TS_clk = PERIOD TIMEGRP "clk" ns 6.450ns ns 7 HIGH % constraint not met. All signals are completely routed. Total REAL time to par completion: 2 mins 44 secs Total CPU time to par completion: 2 mins 39 secs Placement: Completed - No errors found. Routing: Completed - No errors found. Timing: Completed - 52 errors found. For more detail on why a constraint wasn t met, view the static timing analysis reports

35 Generating Timing Reports Post-Map Static Timing Report can be created after Map process May be useful for checking logic only delays early in the design process Post-Place & Route Static Timing Report created after Place & Route process Best way to get timing information on fully implemented design

36 Post-Map Versus Post-Place & Route Static Timing Reports The Post-Map Static Timing Report indicates whether or not your constraints are reasonable Contains actual block delays and minimum net delays What is reasonable? If less than 50 percent of the timing budget is used for logic delays, the Place & Route tools should be able to meet the constraint easily Between percent, software runtime will increase Greater than 80 percent, the tools may have trouble meeting your goals The Post-Place & Route Static Timing Report indicates whether or not your constraints were actually met Contains actual block delays and actual net delays calculated from Place & Route FPGA Development Techniques 36

37 Viewing Timing Reports Timing Reports are best viewed using the Timing Analyzer Provides index into report greatly facilitating navigation The Timing Analyzer can create custom reports for selected paths Note: Timing Reports can be created for designs without constraints Advanced Analysis option (trce -a) Useful for finding paths that may have not been constrained and obtaining their timing

38 Timing Report Example Clock edge and time added to clock name Link to Timing Improvement Wizard (failing paths only) Cross probing to Floorplanner and synthesis RTL and Technology views FPGA Development Techniques 38

39 Timing Reports Contents Command line options for the trce program Timing Constraints section Summary of each timing constraint Details on paths that fail to meet constraints Data Sheet section Setup/hold, clock to pad, timing between clock domains, and pad-to-pad delay information Organized in easy-to-read table format Timing Summary section Number of errors and Timing Score Constraint coverage

40 Post-Place & Route Static Timing Report Properties Report Type Error (failing) or Verbose (all) Number of Items in Error/Verbose Timing Report Analyze Skew for All Clocks Only necessary for clocks routed on general routing as others are skew checked automatically Stamp Timing Model Filename Timing Specification Interaction Report file FPGA Development Techniques 40

41 ProActive Timing Closure Cross-Probing to the Xilinx Floorplanner Link Link from from the the Xilinx Xilinx timing timing report report to to the the Floorplanner A graphical graphical view view provides provides powerful powerful insights insights for for timing timing debug debug strategies FPGA Development Techniques 41

42 Outline Static Timing Analysis Introduction Review of Basic Constraints When to Use Advanced Constraints Handling Multiple Clock Domains Analyzing Design Results Demonstration of Constraints Editor & Timing Analyzer to Floorplanner Cross-Probing On-Chip Debugging Power Estimation & Analysis FPGA Development Techniques 42

43 Cross-Probing to Floorplanner Example Click on Path OR Click on Net FPGA Development Techniques 43

44 Reference Material The Answers Database: support.xilinx.com latest information on advanced constaints: using the DCM with phase offset, DDR I/O, etc... The Constraints Guide syntax and examples for PERIOD, OFFSET, MAXDELAY, etc The Development Systems Reference Guide command line options for par, trce, etc On-line documentation: FPGA Development Techniques 44

45 Outline Static Timing Analysis On-Chip Debugging Traditional Debugging Techniques Introduction to On-Chip Debugging On-Chip Debugging Features Demonstration of On-Chip Debugging Power Estimation & Analysis FPGA Development Techniques 45

46 System Debug and Verification is Critical Pressure of Time-to-Market deadlines Design milestones need to be met The debug phase is typically the largest variable in the development cycle FPGA Development Techniques 46

47 Typical Board Debug Setup Download Cable Scope Probe Logic Analyzer 40-Pin Pod FPGA Development Techniques 47

48 FPGA Debug Issues FPGAs are getting bigger and faster Packages getting smaller with more pins, and pin pitches are smaller Number of board layers is increasing Test point headers are consuming valuable board space Access to logic analyzers FPGA Development Techniques 48

49 Existing Solution: FPGA Editor and Probe Bring internal nodes out to a pin All nets available Use any available pin Additional routing delay is given No need to re-run Place and Route!!! Run Bitgen and download FPGA Development Techniques 49

50 FPGA Editor and Probe FPGA Development Techniques 50

51 The Need for On-Chip Debug Traditional board level testing methods are not enough Need internal access to signals, nodes and system buses Integrated IP means wider, faster busses = more I/O pins dedicated to debug No direct access to IP within the FPGA Difficult to drive high speed clocks and signals off chip without introducing new problems High pin count, fine pitch packaging makes accessing pins nearly impossible FPGA Development Techniques 51

52 Outline Static Timing Analysis On-Chip Debugging Traditional Debugging Techniques Introduction to On-Chip Debugging On-Chip Debugging Features Demonstration of On-Chip Debugging Power Estimation & Analysis FPGA Development Techniques 52

53 The ChipScope Pro Solution Logic analysis core integrated in the FPGA Software interface to monitor and analyze results Access to all internal design nodes Many flexible trigger options Operates at the full system speed synchronous to the design clock up to 350 MHz Available for Virtex, Spartan-II and later FPGA families FPGA Development Techniques 53

54 Debugging with Chipscope Pro JTAG Connections USB port -or- Serial Port Simple! FPGA Development Techniques 54

55 The ChipScope Pro System IO Pads ILA IP Core PPC405 Core IO IO Pads Pads ILA IBACustom Logic Memory Array Embedded System Bus Custom Core ICON ILA Boundary Scan TAP Controller Target Connection ILA IO Pads FPGA fabric provides full internal visibility Access all the internal signals and nodes within the FPGA Access system busses implemented in the FPGA Debug occurs at or near system speeds Debug on-chip using the system clock Minimize pins needed for debug Access via the existing JTAG interface FPGA Development Techniques 55

56 ChipScope Pro Components ChipScope Pro Soft Cores ICON Integrated Control Core communication to BSCAN ILA Integrated Logic Analysis Core ATC2 ILA core with Agilent ATC2 support for off-chip data capture & pin reduction IBA Integrated Bus Analysis Core for CoreConnect OPB and PLB VIO Virtual Input Output cores for internal stimulus ChipScope Pro Software ChipScope Pro Core Generator ChipScope Pro Core Inserter ChipScope Pro Analyzer Support for logic and bus analysis Project-centric interface ChipScope Pro Communication Parallel Cable III and IV, MultiLINX, and Agilent FPGA Trace Port Analyzer via JTAG and Trace Port ChipScope Pro Device Support Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro & Virtex-4 FPGA Development Techniques 56

57 ChipScope Pro Analyzer ChipScope Pro Logic and Bus Analysis Interface Makes Debug and Verification Easy Multiple windows Bus Plotting (Data vs. Time, Data vs. Data) Windows Capture Mode Enables User to Compare Data Captured After Multiple Trigger Events New Listing Viewer Import Bus Token Files and View Instructions As They Occurred Core Polling Disable Eliminate Conflicts with Software Debugger and Other JTAG Tools VIO Console Assign Inputs, Pulse Trains and View Signal Activity New Print Support FPGA Development Techniques 57

58 Xilinx On-Chip Debugging Strategy Design with Debug and Verification in Mind Adopt an On-Chip Verification and Debug Strategy Define the ChipScope Pro Cores Needed to Debug and Verify Design Allocate Resources for ChipScope Pro Cores BlockRAM Slice Logic BSCAN USER1 or USER2 Include Connectors in PCB Design JTAG Optional High-Speed Trace Port Define Target Connection Cable JTAG (PCIV or MultiLinx) Agilent FPGA Dynamic Probing FPGA Development Techniques 58

59 Static Timing Analysis On-Chip Debugging Outline Traditional Debugging Techniques Introduction to On-Chip Debugging On-Chip Debugging Features Demonstration of On-Chip Debugging Power Estimation & Analysis FPGA Development Techniques 59

60 ChipScope Pro ILA Core User Selectable 1 to 4 Trigger Ports Up to 256 Channels Per Trigger Port Multiple Match Units on Same Trigger Port Up to 16 Match Units Trigger Condition Sequencer Define Complex Trigger Sequences that Include up to 16 States or Levels Over 300Mhz performance FPGA Development Techniques 60

61 ChipScope Pro IBA Cores ChipScope IBA Pro Cores IBA Core Supports CoreConnect OPB and PLB Supports Both PPC and MicroBlaze OPB/PLB Buses Automatic Mapping of Bus Signals to Trigger/Data Ports CoreConnect OPB Protocol Violation Detection FPGA Development Techniques 61

62 ChipScope Pro VIO Core ChipScope Pro VIO Core Insert virtual pins into your design Input or Output Synchronous or Asynchronous System Clock or JTAG clock Up to 256 bits each Inputs are Virtual LEDs Different Refresh Rates Available Outputs are Virtual DIP Switches Force Value or Pulse Train into FPGA FPGA Development Techniques 62

63 ChipScope Pro Core Generator Adding ChipScope Pro Cores During Design Entry ChipScope Pro Core Generator Specify ILA, ATC2, IBA and VIO Cores Generate Synthesizable HDL to Add to Design HDL Access any Signal or Node with the FPGA Under Test Define Internal or External Memory Sample Storage Requirements FPGA Development Techniques 63

64 ChipScope Pro ILA Core Generator Features Define the number of Trigger Ports, Width and Number of Match Units Used Expanded Bit Values and Functions Based on Match Type Enable and Define Trigger Sequence FPGA Development Techniques 64

65 ChipScope Pro IBA Core Generator Features Target CoreConnect Processor Local Bus (PLB) or On-Chip Peripheral Bus (OPB) Embedded PowerPC or Soft Core MicroBlaze Trigger Input/Output Logic Detects PLB and OPB Bus Activity Drive External Equipment or Additional Cores Optional OPB Protocol Bus Monitor Detect 32 IBM CoreConnect OPB Protocol Violations FPGA Development Techniques 65

66 ChipScope Pro Core Inserter Insert ChipScope Pro ILA/ATC2 Cores No changes to source code required, modifications are performed on postsynthesis netlist Support All Available Trigger Options Same Options as Core Generator Easy to Use Core Configuration Trigger Options Tab Capture Settings Tab Net Connections Tab Easy to Remove ChipScope Pro Cores Remove.CDC This File from Project Available for HDL or EDIF Flows Core Inserter doesn t currently support for IBA or VIO Cores FPGA Development Techniques 66

67 ChipScope Pro Core Inserter Add ChipScope Pro Cores to an Existing Design ChipScope Pro Core Inserter Add ILA and ATC2 Cores to an Existing Design Netlist ChipScope Pro and ISE Integration ChipScope File (.CDC) Added to Project as a Source, Associated With the Top Level Design Source User Double-Clicks.CDC to Set Parameters and Connections Versions of ISE and ChipScope Pro Must Match Set ChipScope Pro Core Parameters and Connections Via This Source Automatically Launch the ChipScope Pro Analyzer Inserter Called Automatically During Translate Stage FPGA Development Techniques 67

68 Multiple windows Bus Plotting data vs. time data vs. data New listing viewer More trigger options Core polling disable Eliminate conflicts with software debuggers or other tools using the JTAG chain ChipScope Pro Analyzer Features FPGA Development Techniques 68

69 Storage Qualification Improves On-Chip Data Storage Define Boolean storage qualification conditions Determine whether to capture and store individual data samples Use trigger and storage qualification together When to start and stop capture To specify data to capture Reduces required storage while maintaining full visibility FPGA Development Techniques 69

70 VIO Console in Analyzer VIO Console gives you control over Virtual I/O ports View activity Assign internal inputs to FPGA FPGA Development Techniques 70

71 ChipScope CLB Resource Utilization Single basic ILA with ICON core for Virtex / -E or Spartan-II / -IIE: Trigger/Data Width Flops LUTs Slices Percentage of XCV % % % % % % FPGA Development Techniques 71

72 ChipScope Block RAM Resource Utilization Single basic ILA with ICON core for Virtex / -E or Spartan-II / -IIE Trigger/Data Width 256 samples 512 samples 1024 samples 2048 samples 4096 samples 2 1 unit 1 unit 1 unit 1 unit 2 units 4 1 unit 1 unit 1 unit 2 units 4 units 8 1 unit 1 unit 2 units 4 units 8 units 16 1 unit 2 units 4 units 8 units 16 units 32 2 units 4 units 8 units 16 units 32 units 64 4 units 8 units 16 units 32 units 64 units Spartan-3 & Virtex-II / -II Pro / -4 BRAMs are four times larger FPGA Development Techniques 72

73 Integration with FPGA Editor Change data and/or trigger nets connected to ILA......without re-running PAR! Insert ILA and ICON into synthesized design Connect Clock, Control and Data Points to Cores Place and Route Design Change Data Capture Points With FPGA Editor Run BitGen Download Design Set Triggers Run ILA Chipscope FPGA Development Techniques 73

74 ILA in FPGA Editor Select new net to analyze FPGA Development Techniques 74

75 FPGA Dynamic Probe Measures new groups of internal FPGA signals in seconds without: Recompiling the design Impacting the timing of the design Save 15 min to 10 hours per new measurement Achieves wider internal visibility over a fixed number of pins 64 internal probe points for every pin conserves FPGA resources Save 8 hours per problem by not having to create a testbench Eliminates error prone & time consuming tasks Automates signal/bus labeling from FPGA design to logic analyzer Maps FPGA pins from board layout to logic analysis channels Save 2 to 30 minutes per new measurement FPGA Development Techniques 75

76 Agilent FPGA Dynamic Probe FPGA Dynamic Probe SW application supported by 1680/1690/16900 PC Board Probe MUX outputs of ATC2 core and PCB Signals Xilinx JTAG Cable Insert ATC2 core with ChipScope Pro FPGA ATC2 Dynamic control of ATC2 with your regular Xilinx Cable Works with Xilinx Virtex-4, Spartan-3, Virtex-II Pro and Virtex-II FPGAs JTAG Header FPGA Development Techniques 76

77 2, 4, 8, 16, or 32 input banks All banks have identical width (4 to 128 signals wide) Bank width determined by # of pins - each pin corresponds to 1 signal per bank Using optional 2X TDM in in state mode each pin corresponds to to 22 signals per per bank Agilent Trace Core (ATC2) 2 nd Generation Trace Core ATC2 Selection MUX Select 2X TDM JTAG Change input bank selection dynamically via JTAG Output to FPGA pins for debug Improved Signal Visibility Number of Debug Pins Maximum Internal Signals FPGA Development Techniques 77

78 Outline Static Timing Analysis On-Chip Debugging Traditional Debugging Techniques Introduction to On-Chip Debugging On-Chip Debugging Features Demonstration of On-Chip Debugging Power Estimation & Analysis FPGA Development Techniques 78

79 ChipScope Demonstration Block Diagram UART Rx Ain[15:0] Bin[15:0] [15:8] [7:0] LB a [15:8] [7:0] LB b FIFO 16 Byte CE a Rx_Data Rx_status Tx_status PROMstatus RAM_Data PROMin[7:0] BUTTONS [3:0] SWITCHES [7:0] Port 01 Port 00 Port 05 Port 04 Port 03 Port 02 KCPSM3 Program (BRAM) Port 14 Port 12 Port 11 Port 80 [17:16] [15:8] [7:0] *RAM address [17:0] * Common to both RAM devices RAM enables *WE *OE CE UB LB CE UB LB IC10 IC11 Ports E0-E3 Port A Dual Port RAM LED [7:0] 7-Segment Display DIN Port 40 PROM Reader Port 60 OE CCLK PROMin[7:0] 8 *OE [15:8] 16 IC10 [7:0] Data [15:0] Ain[15:0] 20-bit counter 2 MSBs A D dp,g,f,e,d,c,b,a decode ChipScope Probe Points AN3 AN2 AN1 AN0 Port C0 FIFO 16 Byte UART Tx Tx_status PROMstatus *OE [15:8] 16 IC11 [7:0] Data [15:0] Bin[15:0] FPGA Development Techniques 79

80 Four-Character, 7-Segment Control an individual character LED Display Details Drive anode control Low to select character 8 control lines light a specific segment on LED 4 anode control lines define which character responds FPGA Development Techniques 80

81 Outline Static Timing Analysis On-Chip Debugging Power Estimation & Analysis Initial Estimation Post-Implementation Analysis FPGA Development Techniques 81

82 Initial Power Estimation Online Estimation Tool: Available at: FPGA Development Techniques 82

83 Initial Power Estimation Tool Features Provide Resource Estimates: Save & Reload Data if required: FPGA Development Techniques 83

84 Outline Static Timing Analysis On-Chip Debugging Power Estimation & Analysis Initial Estimation Post-Implementation Analysis FPGA Development Techniques 84

85 Power Estimation with XPower Integrated in ISE s Project Navigator Operates on post-par netlist (NCD file) Generate stimuli manually or from timing simulation New Design Wizard: Load Design & Simulation Data Files FPGA Development Techniques 85

86 Power Estimation with XPower Step 1: Set / Verify Voltage, Ambient temperature, and Airflow Step 2: Set / Verify clock & input frequencies, and activity rates Step 3: Set / Verify Capacitive Loads for the outputs Step 4: Set / Verify DC loads for the outputs Step 5: Set / Verify enable rate for the bi-directional IO FPGA Development Techniques 86

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