NAME SYMBOL CHARACTERISTIC TABLE EXCITATION TABLE. S R Q(next) 0 0 Q. (hold) (reset) (set) 1 1? (undefined) J K Q(next) (hold) (reset) (set) 1 1 Q'
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1 Flip-flops By placing two latches in series, it is possible to create a flip-flop. The flip-flop is a memory element that depends on a clock signal and, therefore, it is edge-sensitive. Each flip-flop consists of an input section which is the master section and an output section which is the slave section. NAME SYMBOL CHARACTERISTIC TABLE EXCITATION TABLE S R Q(next) SR NOR implementation 0 0 Q 0 0 0? (undefined) Q(pres) Q(next) S R X X 0 J K Q(next) JK 0 0 Q Q' (toggle) Q(pres) Q(next) J K X 0 X 0 X X 0 Q(next) 0 0 Q(pres) Q(next) T T Q(next) 0 Q Q' (toggle) Q(pres) Q(next) T Symbols, characteristic and excitation tables for SR, JK, and T flip-flops
2 NAN flip-flop I The NAN version of the flip-flop consists of a total of 9 gates (8 NANs and NOT): OFFTIME = 00n ONTIME = 00n ELAY = 0nS STARTAL = OPPAL = 0 U8A U6A UA UA Q R Meg U9A U7A U4A UA Q_not 0 OFFTIME = 00n ONTIME = 00n ELAY = 50ns STARTAL = OPPAL = 0 U5A 74LS04 NAN flip-flop epending on its value, the clock signal () enables or disables the sections of the flip-flop separately. When =, the master section is active and produces a value that is used as an input for the slave section. When =0, the inverter produces a for the slave section which inputs the values produced by the master section in turn producing a value at the output of the circuit. The flip-flop is associated with a symbol which is: The NAN flip-flop has one non-inverted input called, a clock which changes between 0 and and two outputs called Q and Q. The clock is shown by the > sign inside the symbol. Q represents the value currently stored by the flip-flop and Q is its complement. The signals S and R are used to asynchronously set and reset the flip-flop (the device can be set or reset and these operations do not depend on the clock). Sometimes, bubbles are present at the S and R inputs to indicate that the signals are active-low signals (they set or reset the flip-flop when the signal is 0). 6
3 The characteristic table for the NAN flip-flop is shown below: Q(next) X Q 0 0 Characteristic table for the NAN flip-flop The characteristic table shows that the next state (Q) is a result of two possible input combinations. 0 will produce 0, will produce. The waveforms for the NAN flip-flop are show below: : : s 0.5us.0us.5us.0us.5us (UA:Y) Time Waveforms for the NAN flip-flop 0 produces 0 and produces. This device produces outputs on the falling edge of the clock. A flip-flop can be obtained from a JK flip-flop by placing an inverter between its inputs. 7
4 NAN flip-flop II This is another version of the flip-flop implemented with NAN gates. Unlike the previous flip-flop, the gate count is only 6 NAN gates (U5A has inputs). UA OFFTIME = 00n ONTIME = 00n ELAY = 0n STARTAL = OPPAL = 0 U4A U5A 74LS0 UA UA Q Q_not R Meg 0 U6A OFFTIME = 00n ONTIME = 00n ELAY = 50n STARTAL = OPPAL = 0 NAN flip-flop epending on its value, the clock signal () enables or disables the sections of the flip-flop separately. The flip-flop is associated with a symbol which is: The NAN flip-flop has one non-inverted input called, a clock which changes between 0 and and two outputs called Q and Q. The clock is shown by the > sign inside the symbol. Q represents the value currently stored by the flip-flop and Q is its complement. The signals S and R are used to asynchronously set and reset the flip-flop (the device can be set or reset and these operations do not depend on the clock). Sometimes, bubbles are present at the S and R inputs to indicate that the signals are active-low signals (they set or reset the flip-flop when the signal is 0). 8
5 The characteristic table for the NAN flip-flop is shown below: Q(next) X Q 0 0 Characteristic table for the NAN flip-flop The characteristic table shows that the next state (Q) is a result of two possible input combinations. 0 will produce 0, will produce. The waveforms for the NAN flip-flop are show below: : : s 0.5us.0us.5us.0us.5us.0us (UA:Y) Time Waveforms for the NAN flip-flop 0 produces 0 and produces. This device produces outputs on the rising edge of the clock. A flip-flop can be obtained from a JK flip-flop by placing an inverter between its inputs. Note: when initially powered up, the flip-flop is at about.5. 9
6 NOR flip-flop I The NOR version of the flip-flop consists of a total of 9 gates (8 NORs and NOT): OFFTIME = 00n ONTIME = 00n ELAY = 0nS STARTAL = OPPAL = 0 UA 74LS0 UA 74LS0 UA 74LS0 U4A 74LS0 Q R5 U5A 74LS0 U6A 74LS0 U7A 74LS0 U8A 74LS0 Q_not 0 Meg OFFTIME = 00n ONTIME = 00n ELAY = 50ns STARTAL = OPPAL = 0 U9A 74LS04 NOR flip-flop epending on its value, the clock signal () enables or disables the sections of the flip-flop separately. When =, the master section is active and produces a value that is used as an input for the slave section. When =0, the inverter produces a for the slave section which inputs the values produced by the master section in turn producing a value at the output of the circuit. The flip-flop is associated with a symbol which is: The NOR flip-flop has one non-inverted input called, a clock which changes between 0 and and two outputs called Q and Q. The clock is shown by the > sign inside the symbol. Q represents the value currently stored by the flip-flop and Q is its complement. The signals S and R are used to asynchronously set and reset the flip-flop (the device can be set or reset and these operations do not depend on the clock). Sometimes, bubbles are present at the S and R inputs to indicate that the signals are active-low signals (they set or reset the flip-flop when the signal is 0). 0
7 The characteristic table for the NOR flip-flop is shown below: Q(next) X Q 0 0 Characteristic table for the NOR flip-flop The characteristic table shows that the next state (Q) is a result of two possible input combinations. 0 will produce 0, will produce. The waveforms for the NOR flip-flop are show below: : : s 0.us 0.4us 0.6us 0.8us.0us.us.4us.6us.8us.0us (U4A:Y) Time Waveforms for the NOR flip-flop 0 produces 0 and produces. This device produces outputs on the rising edge of the clock. A flip-flop can be obtained from a JK flip-flop by placing an inverter between its inputs. Note: when initially powered up, the flip-flop is at about.5.
8 NOR flip-flop II This is another version of the flip-flop and this one is implemented with NOR gates. Just like for the first version of the NAN flip-flop, the gate count is only 6 gates (U5A has inputs). UA 74LS0 U4A 74LS0 UA 74LS0 Q R Meg OFFTIME = 00n ONTIME = 00n ELAY = 0ns STARTAL = OPPAL = 0 U5A 74LS7 UA 74LS0 Q_not 0 U6A OFFTIME = 00n ONTIME = 00n ELAY = 50nS STARTAL = OPPAL = 0 74LS0 NOR flip-flop epending on its value, the clock signal () enables or disables the sections of the flip-flop separately. The flip-flop is associated with a symbol which is: The NAN flip-flop has one non-inverted input called, a clock which changes between 0 and and two outputs called Q and Q. The clock is shown by the > sign inside the symbol. Q represents the value currently stored by the flip-flop and Q is its complement. The signals S and R are used to asynchronously set and reset the flip-flop (the device can be set or reset and these operations do not depend on the clock). Sometimes, bubbles are present at the S and R inputs to indicate that the signals are active-low signals (they set or reset the flip-flop when the signal is 0).
9 The characteristic table for the NOR flip-flop is shown below: Q(next) X Q 0 0 Characteristic table for the NOR flip-flop The characteristic table shows that the next state (Q) is a result of two possible input combinations. 0 will produce 0, will produce. The waveforms for the NOR flip-flop are show below: : : s 0.us 0.4us 0.6us 0.8us.0us.us.4us.6us.8us.0us (UA:Y) Time Waveforms for the NOR flip-flop 0 produces 0 and produces. This device produces outputs on the falling edge of the clock. A flip-flop can be obtained from a JK flip-flop by placing an inverter between its inputs.
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