SEQUENTIAL LOGIC. Sequential Logic

Transcription

1 EUENTIAL LOGIC equential Logic FF s LOGIC t p,comb 2 storage mechanisms positive feedback charge-based

2 Flip-Flop: Timing efinitions t t setup thold ATA TABLE t t pff ATA TABLE t Maximum Clock Frequency FF s Also: t cdreg + t cdlogic > t hold LOGIC t cd : contamination delay = minimum delay t p,comb 2

3 Latches versus egisters Latch: level-sensitive circuit passing the input to the output when the latch is enabled - otherwise it is in hold Positive Latch Negative Latch G G CLK CLK clk clk stable follows stable follows Edge-triggered register: samples the input on clock transition Positive Feedback: Bi-tability V i V o=v i2 V o2 V o V i2 = V o V i V o2 V i2 = V o A C V i = V o2 B 3

4 4 igital tegrated Circuits equential Logic Meta-tability V i2 = V o V i = V o2 C V i2 = V o V i = V o2 B δ δ Gain should be larger than in the transition region igital tegrated Circuits equential Logic -Flip Flop

5 JK- Flip Flop J K J n K n n+ n n (a) J K (c) (b) Other Flip-Flops T J J K K T Toggle Flip-Flop elay Flip-Flop 5

6 ace Problem t loop t t ignal can race around during = Master-lave Flip-Flop MATE LAVE J I K I PEET J K CLEA 6

7 Propagation elay Based Edge-Triggered N X N2 X t plh = Mono-table Multi-Vibrator Edge Triggered Flip-Flop J K J > K 7

8 CMO Clocked - FlipFlop M2 M4 M6 M M3 M8 M5 M7 Flip-Flop: Transistor izing 4. (7.2/.2) (3.6/.2) (.8/.2) V

9 6 Transistor CMO -Flip Flop M5 M2 M4 M M3 Charge-Based torage (b) Non-overlapping clocks (a) chematic diagram Pseudo-static Latch 9

10 Master-lave Flip-Flop A B Overlapping Clocks Can Cause ace Conditions Undefined ignals 2 phase non-overlapping clocks t 2

11 2-phase dynamic flip-flop 2 put ampled 2 put Enable Flip-flop insensitive to clock overlap M2 M6 M4 X M8 M3 C L M7 C L2 M M5 section section C 2 MO LATCH

12 C 2 MO avoids ace Conditions M2 M6 M2 M6 M3 X M7 M4 X M8 M M5 M M5 (a) (-) overlap (b) (-) overlap Pipelining a EG a EG. log EG EG. EG log EG b EG b EG Non-pipelined version Pipelined version 2

13 Pipelined Logic using C 2 MO C F C 2 G C 3 NOA CMO What are the constraints on F and G? Example Number of a static inversions should be even 3

14 NOA CMO Modules 2 3 PN PUN (a) -module Combinational logic Latch PN 4 (b) -module oubled C 2 MO Latches oubled n-c 2 MO latch oubled n-c 2 MO latch 4

15 TPC - True ingle Phase Clock Logic PUN tatic Logic PN cluding logic into the latch serting logic between latches Master-lave Flip-flops X Y (a) Positive edge-triggered flip-flop (b) Negative edge-triggered flip-flop (c) Positive edge-triggered flip-flop using split-output latches 5

16 chmitt Trigger V out V OH VTC with hysteresis V OL estores signal slopes V M V M+ V in Noise uppression using chmitt Trigger V in V out V M+ V M t t t + t p t 6

17 CMO chmitt Trigger M 2 M 4 V in X V out M M 3 Moves switching threshold of first inverter chmitt Trigger imulated VTC VX (V) Vout (V) V M+. V M V in (V) V in (V) 7

18 CMO chmitt Trigger (2) M 4 M 6 M 3 M 2 X M M 5 Multivibrator Circuits Bistable Multivibrator flip-flop, chmitt Trigger T Monostable Multivibrator one-shot Astable Multivibrator oscillator 8

19 Transition-Triggered Monostable ELAY t d t d Monostable Trigger (C-based) A B C (a) Trigger circuit. B V M (b) Waveforms. t t t 2 9

20 Astable Multivibrators (Oscillators) 2 N- ing Oscillator 5. V V 3 V 5 V (Volt) t (nsec) simulated response of 5-stage oscillator Voltage Controller Oscillator (VCO) M6 M4 chmitt Trigger restores signal slopes M2 I ref M I ref V contr M5 M3 Current starved inverter 6 t phl (nsec) V contr (V) propagation delay as a function of control voltage 2

21 elaxation Oscillator I I2 2 C t T = 2 (log3) C 2