HDBMn: A Novel Line Coding Scheme with Re-encoding Detection Assistance

Transcription

1 JOURNAL OF TLCOMMUNICATIONS, OLUM 5, ISSU 2, AUGUST 202 HDMn: A Novel Line Coding Scheme with Re-encoding Detection Assistance Christos S. Koukourlis Abstract In this paper an alternative Line Coding technique is described. This technique belongs to the general family of modified AMI (Alternate Mark Inversion) line coding, like the HD3 (High Density ipolar of order 3). The name given to the proposed technique is HDMn, i.e. High Density ipolar Manchester of order n. For simplification purposes, it will be referred as HDM3, i.e. n=3. The proposed scheme uses a much simpler decoder while maintains the number of transitions in the transmitted waveform. Due to the simplified receiver design a reduced R (it rror Rate) is expected. One of the motivations is to show that the HD3 coding scheme, which was adopted by the industry in RZ format during the last decades, was not optimally implemented. It will be shown that almost in all cases where an error gets in to the stream, the proposed method is superior compared to the ubiquitous HD3, because of the straightforward decoding of the incoming signal and the error detection capability of AMI which is preserved. An additional feature here is the clock recovery at the receiver which is extracted by re-encoding the decoded data and comparing the re-encoded waveform with the input waveform in order to reduce any phase ambiguity of the recovered clock. Index Terms AMI, 8ZS, Clock xtraction, -carrier, HD3, Line Coding, Re-encoder, Remodulator. u INTRODUCTION The digital transmission systems usually adopt three fundamental types of coding in order to improve their performance: source, channel and line coding. From these three the line coding has the general purpose of improving the transmission reliability and its introduction is founded more on practical considerations than on the intellectuality of information theory []. Traditionally the codes were designed to produce a digital pulse train with specific spectral properties. These properties generally include the absence of a DC component and the presence of a strong spectral component from which timing can be extracted [2]. So, this paper refers to a rather technical field and is supported by a comparative rather theoretical study, attempting to show that the HD3 coding scheme which was adopted by the industry in RZ format during the last decades in repeatered carrier systems could be implemented in a more straightforward and efficient way although preserving the spectral characteristics and absence of DC of the standard HD3 encoding scheme. In carrier systems, as applied in trunk telephony like the uropean -carrier system, several line coding techniques have been adopted [3], [4]. The common characteristic of these techniques is that the encoded stream must lack any DC component, and consequently any low frequency spectral content in order to ensure that the signal passes through galvanic isolated stages where appropriate transformers are used. This capability is ensured by using bipolar techniques like the AMI (Alternate Mark Inversion) where the mark level (usually logic one) is denoted Christos S. Koukourlis is with the Department of lectrical and Computer ngineering, Democritus University of Thrace, Telecommunications Systems Lab, Xanthi, GR-6700, Greece alternatively by positive and negative pulses of equal value, while the space level (say logic zero) is denoted by the zero line voltage, i.e. absence of pulse. Although the new technologies like ADSL, DSL, and the other IP based systems are now being widely deployed, current technologies that have given good service over many years will remain in use, as a result of their wide deployment, for the years to come. There are still many applications where an tranceiver can be used, like PDH Multiplexers, ATM Switches, ISDN Terminals, xdsl Modems and Radio Modems [5]. Despite that in some text books the HD3 is referred either as NRZ or RZ, the format that is used in industrial applications of -carrier is Return-to-Zero [5], and this is also the case where the proposed method is applicable. The early and simpler members of this encoding family, like the AMI, suffer by prolonged absence of transitions due to many consecutive logic zeroes and may be deliberately result in lack of system synchronization at the receiver side, because the clock recovery stage of the receiver synchronizes itself on the transitions of the received waveform. So, for the purpose of preventing the prolonged lack of transitions, several more advanced methods like HD3 and xzs [3] have been adopted in order to insert pulses which result in transitions, but in some way these inserted pulses should be recognized as such and not interpreted as logic ones at the receiver side. For example the HD3 line code which is used in all levels of the uropean -carrier system replaces any instance of four consecutive 0 bits with the pattern 000, i.e. when four consecutive zeroes are to be coded, the fourth zero is encoded as pulse which seems like logic one, but of the same polarity of the previous pulse transmitted (called ipolar with x-zero Substitution, where x=8 for the North American T carrier system, x=6 for T2 and x=3 for T3.

2 2 violation pulse, ) in order to be discriminated from the valid logic ones. If the coding method was continuing in this way, then, for prolonged series of zeroes, each fourth pulse would have the same polarity of the previous, resulting in the accumulation of long series of the same polarity pulses, giving rise to the accumulation of DC component, actually cancelling the first desirable characteristic which was the lack of DC. So, HD3 uses a more complicated algorithm according to which the encoder replaces any instance of 4 consecutive 0 bits with one of the patterns "000" or "00". The choice of "000" or "00" is made so that the number of pulses, which are also called balancing pulses or extra ones, between consecutive pulses is odd. In other words, successive pulses are of alternate polarity so that no DC component is introduced. The encoding techniques like HD3 use complex encoding and decoding circuitry and also complex state diagrams when implemented as finite state synchronous machines [6], [7]. For example an HD3 encoder must implement as many as 32 machine states [6]. In contrast, the proposed method uses a different and much more simplified rule in order to insert violations : The violation of the RZ-AMI rule is not on the identical polarity of the pulse inserted, but on the time instant (position) that the pulse occurs during the bit period. In this paper the HDM3 version, which directly compares with the well known HD3, has been developed and constructed for a bit rate of 2 Mbps, although it is applicable for any rate, depending on the electronics employed. 2 NCODING/DCODING RULS OF HD3 For the purpose of highlighting the complexity of the most frequently applied HD3 encoding scheme, its rules are presented here. In Fig a sample of an HD3 encoded signal is shown. The pulses denoted by and are not actual logic ones and must be recognized by the decoder and interpreted as logic zeroes. According to the encoding rules of HD3, every time a sequence of transmitted bits occurs to be 0000, the fourth bit changes to a level with the same polarity as the previously transmitted pulse, i.e. by violating the rule of alternating polarity ( pulse). zeroes, each pattern of 0000 is replaced either by a +00+ pattern or by a -00- pattern depending on the polarity of the last transmitted pulse. In order to accomplish the decoding, the receiver must keep at least three next time intervals and at least one previous time interval in memory. An HD3 receiver has to interpret any received pulse as one of three cases: logic one ( ), violation pulse ( ) or extra one ( ). To accomplish this task it has to know the polarity and the distance (in clock cycles) of both the previous and the next pulses to the current one: If the previous pulse is of the same polarity (in any distance or alternatively, according to the encoding rule, at a distance of 3 or 4 clock periods) the current pulse is considered as a and definitely it is interpreted as a logic zero. If the distance of the previous pulse is one, then the receiver has to check if the next pulse has the same polarity and lies in a distance of three clocks. In this case the current pulse is an extra one ( ) and must be interpreted as logic zero also. If the status of the current pulse does not fall in any of the two previous cases it is interpreted as logic one. Although the rules of encoding are well-known [3] and presented in Table, the decoding rules of HD3, as summarized in Table 2, are given here in order to correspond to the encoding rules, as they are implemented in the hardware which is developed for comparative study. TAL NCODING RULS OF HD3 TAL 2 DCODING RULS OF HD3 HD3 Fig.. HD3 Line Code: the pulses denoted by and are not actual logic ones and must be recognized by the decoder. In the case of longer sequences of zeroes this is not adequate, as soon as violation pulses (of the same polarity) will give rise to a DC component. In these cases an extra one is added ( ) in the place of the first zero of the 0000 pattern, i.e. different polarity to the previous pulse while the fourth bit of the 0000 pattern is replaced also by a violation pulse i.e. of the same polarity to the just inserted pulse. In conclusion, for long sequences of 3 HDMn, TH NOL NCODING SCHM From the above description the complexity of the HD3 encoding/decoding format is obvious, although the above rules can be easily implemented and manufactured in hardware. Seeking for an encoding scheme that prevents the prolonged transmission of consecutive zeroes, but at the same time keeping strictly the rule of toggling the polarity of the transmitted pulses we ended up with the proposed method, HDMn as a general format, or

3 3 HDM3 to be directly compared with the ubiquitous HD3. This method uses a different and much more simplified rule in order to insert violations. Actually, the violation of the AMI rule is not introduced by violating the rule of alternative pulse polarity, but violating the time position that the pulse occurs during the bit period. To clarify this, let s consider that we have AMI RZ encoded data, Fig. 2, which means that the alternate polarity pulses are generated during the first half of the clock period. According to the proposed method, when a violation pulse is to be inserted, the rule of alternate polarity pulses is not violated as in HD3, but it is maintained, as explained above. The violation regards the time position of the inserted pulse which takes place during the other half of the bit interval. This alteration of time interval during which the pulse is inserted gives rise to the letter M, from the well known Manchester encoding scheme, in the name of the proposed technique, HDMn, or HDM3. In Fig. 2, for clarification purposes, the AMI line code as well as the HD3 and HDM3 line codes are given. Also, another line code, named HDM3* is given. This code inserts the data into the first half clock period and the violation to the second one. Unfortunately, when a long series (multiple of four) of zeroes is followed by a logic one, this gives rise to a pulse pattern which swifts from all negative to all positive (or vice-versa) without stepping through zero voltage. This is shown in Fig.2 in the dashed square of the waveform named HDM3*. Although this does not seem to be a problem, it could amplify some spectral lines and intuitively the encoding rule of HDMn is somewhat modified, which now becomes the information (data) being inserted in the second half while the violation pulse is inserted in the first half of the bit duration. Also, comparing HDM3* and HDM3 in Fig. 2, the latter seems to have two transitions instead of one (but of full height). AMI HDM3* HDM3 HD3 Fig. 2. AMI, HDM3 and HD3 Line Codes compared. HDM3* is as intermediate step for explanation purposes. The proposed encoding scheme maintains the density of violations ( pulses) and spectral properties of HD3, i.e. it gives rise to the necessary transitions for the clock recovery stage of the receiver and, at the same time, does not pose any problem of DC accumulation since the rule of alternate polarity pulses is strictly maintained. On the receiver side, after the recovery of the clock waveform, the decoding of the received signal is extremely simple as the clock waveform just samples the data waveform always during the second half of the bit period where the transmitted information lies and never during the first half where the violation pulses lie. Compared to HD3, this greatly simplifies the decoding rule, which, in the case of HD3, is rather complicated as shown in Table 2 because the HD3 receiver has to keep several bits of the bit pattern in order to decide which was the actual transmitted data and not confuse any violation pulses or the so called extra ones ( pulses) from interpreted as logic ones. Actually, the major goal of the receiver is restricted to the clock recovery, since the decoding is extremely simple for the proposed method. Then the decoding is achieved simply by sampling the rectified HDM3 waveform by a D flip-flop triggered by the rising edge of the recovered clock. The timing is shown in Fig. 3. HDM3 HDM3 rectified Recovered Clock RZ Decoded data NRZ Decoded data Fig. 3. An illustration of decoding an HDM3 encoded waveform. The violation is entered into the first half of the bit interval (clock period), while the data at the second one. 4 CLOCK RCORY DATA R-CODING Regarding the implementation of the proposed method, the recovery of the clock at the receiver is based on the use of a Digital Phase Locked Loop (DPLL), the 74HC297. This device is manufactured by several companies. In our case the DPLL was introduced to an Altera chip (PM 7064LC44-0) from the appropriate library, together with the rest of the circuitry. ased on this, the clock recovery itself is simple, but other design problems were introduced, specifically the 80 0 phase ambiguity of the recovered clock. As previously mentioned, before the decoding, the incoming data has to be somewhat rectified. This takes place, as will be explained below, by a combination of analog comparators and an OR gate which sums all the pulses, either positive or negative, in a unipolar pulse stream. The recovered clock can have a 80 0 phase ambiguity because the recovery is based on both kinds of pulses, i.e. actual data or violation pulses. It is possible instead of the real data to decode the violation pulses as data due to 80 0 phase ambiguity of the recovered clock. This uncertainty, although similar to the one in PSK modulation, obviously cannot be cancelled by using some kind of differential encoding. Initially, the incoming waveform is decoded by randomly selecting one of the two 80 o recovered clock waveforms. The decoded data produced by this decoding are reencoded at the receiver giving a locally produced HDM3

4 4 waveform in order to be compared with the received one. The local encoder at the receiver inserts the violation pulses according to the encoding rule but actually the reencoded waveform does not need to be bipolar. It is sufficient and more appropriate that the re-encoded waveform is like the rectified HDM3 waveform. The two rectified waveforms, after the appropriate synchronisation with the same clock at the receiver, are compared: if identical, the randomly selected clock is the appropriate one, otherwise the inverted clock is selected and the decoding proceeds correctly. Additionally, for stability purposes, the decision for clock phase selection is not taken immediately after the detection of a single incompatibility, but it is delayed for at least three incompatibility detections in order to cancel erroneous actions. rules of Table 2. In the HD3 every single bit is detected by sampling appropriately during the bit interval and then applying the decoding rules, while in the proposed HDM3 scheme any bit is detected just by sampling the incoming waveform (it is meaningless to mention that the sampling takes place in the second half) without further decoding. It is straightforward to assume that if both waveforms (HD3 and HDM3) are affected by the same level of noise they will exhibit identical probability of bit error in the transmitted signal over the channel. However, due to the required memory of the HD3 decoder each error can affect as many as three decoded bits, as illustrated in Fig.4. On the contrary, in the proposed scheme, each channel error will result at most to one data error since no further decoding is applied. 5 COMPARATI STUDY OF IT RROR RAT PRFORMANC A mathematical analysis of the R improvement would require studying the HD3 decoder as a Markov process. The impact of every possible input detection error would have to be examined for every possible state of the process to determine the bit errors it would cause. The individual state R could then be evaluated taking into account the probability of a sample detection error P e and the respective steady state probability. The total R of the system would be the sum of these individual-state error probabilities. However, such an analysis is beyond the scope of this technical paper, particularly since the presented study is not about the HD3 system as is, but a modified implementation which renders this analysis irrelevant, as the R is evaluated directly by the sample detection error probability, i.e. P e. Instead, it will be illustrated that in the HD3 scheme a single sample error, at the physical layer, can result in multiple bit errors in several cases due further decoding, whereas in the proposed HDM3 system a single sample error at the physical layer results mostly in one bit error, which is sufficient to make the point that the R performance is improved. So, the R performance of the proposed method (HDM3 case) will not be studied independently but comparatively to the industry dominating coding scheme, the HD3. One of the goals of this paper is to show that the HD3 coding scheme, in the manner that it was adopted during the many previous years, was not the optimum one. From Table 2 it can be seen that the HD3 decoder must take into account as much as four incoming bits in order to decide about the final value of a specific bit because any error introduced affects the decision of other bits giving rise to new errors after decoding. There are two cases of errors in the physical layer level: a is missing or a is erroneously interpreted as such in a place that it does not exist. For the case of HD3 this is analysed in Table 3. It must be emphasized here that the errors inserted in the transmitted signal (physical layer) of Fig. 4 are denoted by while the symbol under the recovered data, at the bottom of each pattern, marks the position of the error in the decoded data stream. These errors have been marked by applying the (a). A is missing (b). A is missing (either polarity). (c). A is missing (either polarity). (d). A same polarity pulse is inserted between and (e). A same polarity pulse is inserted between and. (f). An opposite polarity pulse is inserted between and. (g). An opposite polarity pulse is inserted between and. (h). A pulse (either polarity) is inserted between two successive. Fig. 4. ach waveform, affected by an error at the physical layer, corresponds to one case of Table 3. Above each waveform the correct data are given, while below this the decoded data are given. Where denotes the position of rror. This results in higher R for the HD3 when compared to the proposed scheme since the HDM3 decoder s decision is straightforward in contrast to that of HD3. As deduced from Table 3, due to this effect, the HDM3 coding scheme exhibits on the average more than three times better R than the HD3 scheme. Moreover it must be emphasized again that the proposed scheme maintains the error correction capability of AMI (i.e. the rule of alternate polarity signaling is never violated in AMI and also in HDM3) while this is not possible for the HD3 case, due to the inherent violation. This means that in any case of same polarity error pulse insertion, the error will be self corrected in HDM3, boosting the error correction capability since the receiver knows the expected polarity. Also, it can be observed from Fig. 4 and Table 3, that there is only one occasion (Case d) where the HD3 scheme self corrects the error pulse inserted, because, although a pulse exists, it is translated as violation (which results in logic 0 after decoding) because it has the same polarity with the previous pulse. ven in this case, if the detection of a was stricter, i.e. examining the exact distance

5 5 from the previous pulse (3 or 4 clock periods to accept as a ) the result would be against the HD3 scheme. TAL 3 COMPARISON OF RROR HAIOUR OF HD3 AND HDM3 CODS HDM3 bipolar input Removal of bipolar signaling ( rectification ) Clock Recovery Stage (DPLL) Re-Coder Recovered Clock Decoder Stage Decoded Data Fig. 6. lock diagram of the HDM3 decoder. The block diagram of the decoder is shown in Fig. 6. oth the phase comparators of the 74HC297 DPLL which is adopted for clock extraction are employed (XOR Phase Detector and dge Controlled Phase Detector). In the present case a ten stage loop has been adopted, i.e. the counter of the DPLL counts up to!= 2 0 =024. The crystal of the receiver needs to be eight times higher, i.e. 6 MHz in order to recover the 2 Mbps associated clock. 6 DSIGN AND IMPLMNTATION The proposed encoding scheme has been implemented for a bit rate of 2Mbps instead of the nominal 2,048 Mbps of the uropean standard. Although it is not essential to mention this detail, it is done here since the measurements with spectrum analyzer or oscilloscope (which are to appear later) must be justified in a more practical sense. The first stage of the HDM3 encoder, Fig. 5, is a foursuccessive-zeroes detector which serves for the insertion of the violation pulses and combines them to the actual data. Two pulse streams are produced which drive the two inputs of a differential amplifier which finally produces the bipolar signal. quivalently the two pulse streams could be combined on a line transformer. For experimental purposes this stage was built around a high frequency op amp (AD8047). 7 HARDWAR IMPLMNTATION In Fig. 7 photographs of the implemented encoder and decoder are shown. In the Altera chips, in addition to the HDM3 encoder/decoder, AMI and HD3 pairs of encoders/decoders have been incorporated so that the experimental measurements can be compared. The selection of the encoding/decoding scheme takes place via the DIP switches shown in the pictures. NRZ input data Detection of 0000 data pattern Insertion of pulses Conversion to two streams for positive and negative pulses ipolar Signaling Differential Stage HDM3 output (ipolar RZ signaling) Fig. 5. lock diagram of the HDM3 ncoder. Fig. 7. Photo view of the experimental implementation of the encoder / decoder stages.

6 6 8 XPRIMNTAL RSULTS Several osciloscope and spectrum analyzer image captures are given. In Fig. 8 the insertion of violation pulses is shown. Fig. 9 shows random HDM3 encoded data in bipolar format and the rectified version of this data at the first stage of the decoder. In Fig. 0 the unipolar re-encoded data with the synchronized unipolar received data are shown, while the middle trace shows that their algebraic difference is almost zero. In Fig. the recovered clock is shown. Finally, Fig. 2 shows both random input data and the decoded data waveforms. Fig. 0. Upper trace: HDM3 waveform at the decoder s input. Lower trace: Recovered Clock. Fig. 8. Upper Trace: Data (scrambler output). Lower trace: ncoder output. It is noted that the violation pulse lies in the first half of the bit duration. Fig.. Upper trace: Original data. Lower Trace: Decoded data. A delay is obvious. Fig. 9. Upper trace: HDM3 encoded data in bipolar format. Lower trace: Rectified data at the first stage of the decoder. Fig. 9. Upper Trace: Unipolar Re-coded data waveform. Lower trace: synchronized unipolar received data. Middle trace: the algebraic difference of the two is almost zero. In Fig. 2 the spectral densities of HDM3, HDM3*, HD3 and AMI are presented. As stated previously, all these encoding schemes have been implemented in the same Altera chip and can be selected via the DIP switches of the experimental boards. Fig. 2. Spectra of Line coding schemes of HDM3, HDM3*, HD3 and AMI. For all the above measurements the frequency span of the spectrum analyzer is 6 MHz with center frequency 3 MHz. For experimental purposes the input data of 2 Mbps rate were generated in an 8-flip-flop long pseudorandom generator (scrambler) incorporated in the Altera chip. The spectra shown in Fig. 3 look almost identical, as expected. Since the input data source is not guaranteed to produce an uncorrelated data stream, the above spectra

7 7 present minor differences depending on the capture instant because of the unavoidable data correlation [8]. 9 CONCLUSION In this paper an alternative line coding scheme for data transmission is proposed and described. It is directly comparable to the uropean -carrier standard for data transmission, HD3. specially the receiver design is greatly simplified giving rise to lower R, while the transition density of the transmitted signal is maintained the same as in HD3. Also, the clock recovery is assisted by a re-encoding technique, in order to overcome any phase ambiguity of the recovered clock at the receiver. ACKNOWLDGMNT The author wishes to thank Mr. Dimitrios C. Chrysostomidis, graduate student of the Telecommunications Systems Laboratory of Democritus University of Thrace, for his collaboration in the implementation and construction of the hardware of both the encoder and decoder. RFRNCS [] G.L. Cariolaro, G.L. Pierobon and G.P. Tronca, "Analysis of Codes and Spectra Calculations", Int. Journal of lectronics, ol.55, No., pp.35-79, 983. [2].S.osik, "The Spectral Density of a Coded Digital Signal", ell System Technical Journal, ol.5, No.4, pp , 972. [3] ricsson Telecom A, Telia A, Understanding Telecommunications, Studentenliterature, Lund, Sweden, 998. [4] ITU-T G.703, Series G: Transmission Systems and Media, Digital Systems and Networks, Digital Terminal quipment General Physical/lectrical Characteristics of Hierarchical Digital Interfaces ITU-T Recommendation G.703. [5] A.asilliou, K. Gounaris, K. Adaos, D. Mitsainas, G.Alexiou, D. Nikolos, Development of a Reusable Transceiver Suitable for Rapid Prototyping, I International Workshop on Rapid System Prototyping, Clearwater, FL, USA, Jul 999, pp [6] D. Keogh, The State Diagram of HD3, I Trans. Comm., ol. COM-32, No, Nov. 984, pp [7] Yang Zhang, Xiumin Wang, Yuduo Wang, "A New Design of HD3 ncoder and Decoder ased on FPGA," Conference on Hybrid Intelligent Systems, International, vol., pp , 2009 Ninth International Conference on Hybrid Intelligent Systems, [8] G.L. Cariolaro and G.P. Tronca, "Spectra of lock Coded Digital Signals", I Trans. Comm., vol. COM-22, pp , Oct Christos S. Koukourlis was born in Kavala, Greece, on August 3, 957. He received the lectrical ngineering Diploma in 98 and the Ph.D degree in lectrical ngineering in 990 both from the Democritus University of Thrace, Xanthi, Greece. He currently serves as Dean of the School of ngineering of Democritus University of Thrace. He served also as Head of Department of lectrical & Computer ngineering of Democritus University of Thrace where he also serves as Associate Professor working on digital modulation and high spectral efficiency techniques. His interests also include Data Transmission over T roadcasting, Power Line Modems, Direct Digital Synthesis (DDS) methods, Communications Networks and Fleet Management (GPS based) Systems over GSM network.