Down - (DW Sampler Hold Buffer * Digital Filter * Fig. 1 Conceptual bunch-by-bunch, downsampled feedback system.

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1 Bunch-by-Bunch Feedback for PEP II* G. Oxoby, R. Caus, N. Eisen, J. Fox, H. Hindi, J.Hoefich, J. Osen, and L. Sapozhnikov. Stanford Linear Acceerator Center, Stanford University, Stanford, CA I. Linscott Stanford University, Stanford, CA ABSTRACT The proposed PEP II B factory at SLAC requires a feedback to damp out ongitudina synchrotron osciations. A time domain, downsamped, bunch-by-bunch feedback system in which each bunch is treated as an osciator being driven by disturbances from other bunches is presented as we review the evoution of the system design. Resuts from a synchrotron osciation damping experiment conducted at the SLAC/SSRIJSPEAR riqg are aso presented in this paper. HNTR~DU~TI~N _ Figure 1 is a conceptua diagram of such a system. The phase of each bunch is detected The feedback system design incorporates a and a correction kick for each bunch is phase detector to provide a measure of the computed and appied by a kicker. The bunch phase, digita signa processing to downsamper aows each digita signa compute an error correction signa and a kicker processor (DSP) to hande more bunches and, system to correct the energy of the bunches. A consequenty, reduces the size of the system. downsamping scheme has been impemented The hod buffer hods the ast kick vaue to reduce the size of the hardware. computed for each bunch. Other driving terms and disturbances Down - (DW Samper Hod Buffer * Digita Fiter * Noise Fig. 1 Conceptua bunch-by-bunch, downsamped feedback system. * Work supported by Department of Energy contract DE-AC03-76SFOOS 15. Presented at the Internationa Workshop on B-Factories: Acceerators and Experiments, Tsukuba, Japan, November 17-20,1992.

2 . 2. SYSTEMREQUIREMENTS 3. DIGITALSIGNALPROCESSORS 2.1 PEP II Specifications: 476 MHz RF frequency Every other RF bucket popuated 4.2 ns inter-bunch period Up to 1746 bunches without ion cearing gap 1658 popuated bunches with gap 7.3,ts revoution period 140 ps synchrotron period. 2.2 Feedback requirements: Detect the bunches phase osciation Provide a 90 phase shift at the osciation frequency Suppress DC components in the error signa Provide a processing gain usefu with a noisy front-end Provide +/- 15 inear phase range correction Provide OS, or better, measurement resoution Impement saturated imiting on arge osciations * Output power 2.5 kw at GHz. The commercia activity in DSPs in recent years has ead to a wide choice of devices for audio and speech appications. These devices are aso we suited to synchrotron frequencies in the range of 7-10 khz. When used to impement an acceerator feedback system, they offer the additiona advantage that the fiter can be configured via software to match the particuar operating characteristics of the machine. Figure 2 is a bock diagram.of the origina PEP I ongitudina feedback system proposa using DSP devices to impement a finite impuse response (FIR) fiter Such a system to contro the arge number of bunches in the PEP II rings requires many DSPs. It was recommended by a review board that the number of DSPs be reexamined. 4.DOWNSAMPLING References 3 and 4 present the downsamping approach in detai. Our ongitudina feedback system for PEP I takes advantage of the fact that the revoution frequency at which we sampe the phase osciation is greater than the synchrotron frequency. This inherent oversamping aows use of the downsamping, 2.3 Impementation of the feedback: The various options to impement an acceerator feedback are discussed in detai in Refs. 1 and 2. Anaog and digita approaches are compared, and the approach chosen for the ongitudina feedback systems in PEP II is a digita signa processing technique. Fig. 2 Longitudina downsamper. feedback system without?a

3 in which information about a particuar bunch osciation is used ony every n revoutions, and a new correction signa is updated every n revoutions. This approach aows the -processing system to operate coser to the Nyquist imit and reduces the number of mutipy accumuate operations in the fiter by a factor of /n*. The downsamped ongitudina feedback scheme was examined and simuated. The resuts suggest that it coud contro the couped bunch osciation with dynamics simiar to a 20-tap fiter. The frequency response of the 20-tap and 5-tap fiters are shown in Fig. 3. Figure 5 shows a conceptua bock diagram of such a processing farm. In the spirit of the PEP II technica practice, the downsamped processing scheme was reviewed, approved, and a detaied study of the system architecture recommended. 5. SYSTEM ARCHITECTURE Muti-processor systems have many appications and are typicay based on 1.4 I I I m I * I i- P 8 cn 1.2- (a) A downsamping factor of four was recommended for PEP II. Figure 4 shows that kicker signas appied to the bunch are now a coarser approximation of the idea feedback kick. The downsamping reduces the size of the DSP farm consideraby, and the bus bandwidth required to move data within the system is reduced by a. factor n. However the downsamper and hod buffer need to be impemented with high speed eectronic circuitry running at the bunch frequency. 40 I I e (41 =-1.2 L g 0.8 H g 'Z m 0.4 z t. 0 5 n-o.4 d d IQ fwj@w ww - Fig. 3 Frequency response of n- (dashed ine) and n=4. O Turn number 7059A72 Fig. 4 Response of the downsamped fiter with hod buffer. In (a), the squares are samped vaues of the osciation. (b) shows idea and downsamped outputs to a kicker.

4 - RF Timing 1 v (ZZ~%e detector) Digi&i;er Address - Dua- * - generation go rt down-samper od -r- buffer FJig. 5 Bock diagram of a downsamped standard parae buses such as VME, MutibusII or a new comer in the fied, Futurebus+. The ongitudina feedback for PEP II being a muti-processor system, we chose to use a bus with a we defined protoco to distribute the data. The VMEbus was seected because of _ its architecture, the avaiabiity of assembed chassis with power, cooing and various sizes of backpanes. Interface chip-sets are avaiabe to hep the designer adhere to the protoco and severa side buses, such as VMX, VMS and VSB are specified. The VMEbus is a computer architecture with 32 bit data and 24 bit wide address buses. It can aso be used as a 64-bit-wide mutipexed address and data bus under revision D. There is a proiferation of commerciay avaiabe VME based board products, many of them with DSPs. However, most of the DSP boards commerciay avaiabe have foating point devices and arge on-board memory. They are designed to accept arge bocks of data on which they effect some compicated, sow computation. These subsystems are typicay used for speech recognition, image reconstruction and the ike. They are not we suited to an acceerator feedback appication which is I/O bound and has a short fiter code which requires itte memory. The design of our DSP boards wi have four DSP integrated feedback system with downsamper. Vernier w (to power ampifier) A5 circuits per 6 U VME board. Since the ADC and DAC are eight bits wide, the data from four bunches and four bunch kicks wi each form a 32 bit word. The 32 bit wide VMEbus protoco wgs recommended. This permits us to address the DSP boards with each transfer and perform a read-modify-write cyce rather than doing bock transfers which require dupication of addressing circuitry on the downsamper-hod buffer and the DSP boards. It aso guarantees data integrity. The ongitudina feedback for PEP II presents a particuar chaenge to meeting the data distribution bandwidth. Even with downsamping by four, the amount of data sent from the downsamper to the DSPs and from the DSPs to the hod buffer is overwheming. The data to and from a DSP is one byte wide. The aggregate data rate to maintain is therefore one byte every 16.8 ns, or 119 MBytes per second. Of course, the VMEbus cannot sustain such a data rate. Faced with this restriction we are compeed to distribute the data over two or more VMEbuses. A review was conducted to critique the proposed VME based architecture. very strong warnings were expressed, one to avoid pushing the bus technoogy and the other to expand the contro interface definition.

5 Ethernet I I VSBbus From comb gererator Ethernet Fig. 6 PEP II Longitudina feedback architecture. Another facet of the architecture has to do with the downoading of the code and coefficients to the DSPs, and the system contro and monitoring. These functions can be performed at the ow data rate of a few khz. The VMEbus can be used for downoading as ong as this is done prior to operating the system, since the data transfers wi consume the bus bandwidth during running. Another path had to be found for the contro and monitoring functions. We seected the VME subsystem bus, VSBbus, as the contro, monitoring and downoading path. The VSBbus has a 32-bit mutipexed address and data bus, read-modify-write capabiity, and singe interrupt eve. One of the often cited drawbacks of the VSBbus is its imitation to six sots. In the PEP II ongitudina feedback system design, it forces the designer to imit data transfers to a reasonabe rate. For exampe, if the time for a DSP to execute the fiter is ps, as determined experimentay, a DSP board can be accessed ony every 1~s or onger, with five DSP boards per VMEbus segment, three VME/VSBbus segments are required, and the aggregate read-modify-write data rate per VMEbus segment is now reduced to 37 Mbytes per second. Figure 6 shows the architecture we propose. We chose to package the phase detector, ADC, downsamper and hod-buffer, DAC and the ampitude moduator into a VXIbus mainframe, because of its good eectromagnetic shieding, cooing, and system power. It has power for the ECL circuitry, and its 1.2 inch board spacing aows for arge anaog components. Each VME/VSBbus segment has an interface to the downsamper and hod-buffer via a

6 Gigabit rate data ink and a commerciay avaiabe microcomputer which is used for oading the DSPs, contro and monitoring. This architecture has been reviewed and approved, and the detaied design of the components is in progress. A prototype wi be buit and instaed at the Advanced Light Source (ALS) at LBL OSCILLATION DAMPING AT SPEAR._ A aboratory prototype ongitudina feedback system as described in Ref. 5 has been deveoped. This mode impements a fu speed (500 MHz) front end phase detector with digita signa processing for a imited number of bunches. It has been tested on the SLAG/ SSRL storage ring SPEAR. As the SPEAR storage ring does not have a wideband kicker, it is not possibe in this configuration to contro mutipe bunches, though it is possibe to measure muti-bunch effects using the fast front end. It is possibe to operate this feedback system around a singestored bunch by using the main RF cavity as a beam kicker to demonstrate the behavior of a singe bunch acted upon by a digita feedback system. This approach foows naturay from the ogica mode of the bunch-by-bunch system. The behaviors of the various fiter parameters (tap ength, downsamping factor, etc.) can be studied with a rea beam, and the performance of the front end comb generators, digitizers etc. measured using reaistic conditions. For this experiment the beam was sensed by a button type BPM eectrode and processed by the prototype B factory front end shown in Fig. 7. The phase detector and phase-ocked master osciator were operated at eight times the SPEAR RF frequency (2864 MHz or 8 x 358 MHz) using a comb generator circuit deveoped for PEP II, shown in Fig. 8. The front end digitizer was run at the nomina 4 ns digitizing cyce, and a simpe programmabe downsamper hod-buffer circuit for singe bunch was impemented. A singe DSP was used to compute the feedback fiter, and the feedback signa was then put back into the beam via a phase shifter acting on the RF cavity...,*- Fig. 7 Photographs of the feedback front end prototype.

7 Fig. 8 Comb generators for PEP II (ong) and ALS Mart). For this experiment we used a 5-tap FIR fiter operating with a downsamping factor of eight. The SPEAR ring was operated with a nomina synchrotron frequency of 32 khz. The revoution frequency in SPEAR is 1.28 MHz. Thus, a downsampe by 8 fiters updates a new resut every 8 turns, -whie the ring itsef requires approximatey 40 orbit revoutions to compete a synchronous osciation. Figure 9 shows the resuts of downsamping by eight. Frequency domain measurements for this system can be made by driving the beam through the RF cavity whie observing the response of the beam as a function of f&quency.figure 10 shows the magnitude and phase response of the beam transfer function for an open oop configuration, and for cosed oop gains of 18 and 28 db.in this figure, the open oop gain shows a weaky damped harmonic osciator. The natura damping present in this case is due to Robinson damping as we as radiation damping. The configuration with 28 db of oop gain barey dispays any resonant behavior, and suggests that the transient response of the combined system wi damp in just a few cyces. The time response of the system can be observed in Fig. 11. In this experiment the feedback oop is opened, and a gated burst at 4 I+6 revoutions 6; 9 Rter input and output with dowzpinging factor of % 01 I I Frequen (khz) F!rO Maenitude (a) and ease (b) resvonse ra sinoge buncvh for open kop and cosed oo); gains of 18 and 28 db. the synchrotron frequency is appied via the RF cavity. This excitation burst drives a growing synchrotron osciation of the beam. The excitation is then turned off and the feedback system oop cosed. The damping transients of the beam can then be studied for various designs of feedback fiter and overa oop gain. The figure shows the damping transient of such a gated burst for a 33 db oop gain configuration, which provides damped transients of ony a few cyces. An aternative method of studying the transient response is to operate the feedback system with overa

8 provided expertise and enthusiasm for the SPEAR experiment. REFERENCES: N k: 11 t-ho0 ps Time ime tpsponse of an excited bunch and theep fiter output. positive feedback for short intervas, which causes any noise present at the synchrotron frequency to produce growing osciations. After an interva with positive feedback, the gain is made negative to damp the osciation. This can be made periodic, and the growth/damping rates studied for various configurations of fiter gains, such as phase shifts and eectronic imperfections. 7. SUMMARY. This system design is the work of a coaboration between staff at SLAC, LBL, Stanford University Eectrica Engineering department and INFN Frascati. This group is preparing the detaied design for the prototype ongitudina feedback system to be instaed at the LBL ALS faciity, and coaborating on the system design of the transverse feedback Acknowedgements ()J. D. Fox et a., Feedback Impementation Options and Issues for B Factory Acceerators SLAC-Pub-5932 Conference on B Factories: The State of the Art in Acceerators, Detectors and Physics, Stanford, CA, Apri (2)J. D. Fox et a., Mutibunch Feedback-- Strategy, Technoogy and Impementation options SLAC-Pub-5957 Acceerator Instrumentation Workshop, Berkeey, CA,. October (3)H. Hindi et a., Down Samped Signa Processing for a B Factory Bunch-by-Bunch Feedback System SLAC- Pub rd European Partice Acceerator Conference, Berin, Gemany, March (4)H. Hindi et a., Downsamped Bunch-by-- Bunch Feedback for PEP II SLAC-Pub-5919 Conference on B Factories: The State of the Art in Acceerators, Detectors and Physics, Stanford, CA, Apri (5)D. Briggs et a., Prompt Bunch-by-Bunch Synchrotron Osciation Detection via a fast Phase Measurement SLAC-Pub-5525 Workshop on Advanced Beam Instrumentation, KEK, Tsukuba, Japan, Apri The ideas presented in this paper refect the contributions of many peope at SLAC, LBL, Stanford University and INFN Frascati. The authors wish to thank Jonathan Dorfan and Mike Zisman for their continued support, Femming Pederson from CERN for numerous recommendations, and the staff at SPEAR who