NEW DEVELOPMENTS IN SEGMENT ANCILLARY LOGIC FOR FASTBUS"

Transcription

1 I NEW DEVELOPMENTS IN SEGMENT ANCILLARY LOGIC FOR FASTBUS" Hemut V. Waz and Boris Bertoucci Stanford Linear Acceerator Center Stanford University, Stanford. Caifornia SLAC-PUB-2990 October 1982 (I/A) Abstract Segment Anciary Logic hardware for FASTBUS systems provides ogica functions required in common by a devices attached to a segment. It contros the execution of arbitration cyces, and geographica address cyces, and generates the system handshake responses for broadcast operations. The mandatory requirements for Segment Anciary Logic in the FASTBUS specifications are reviewed. A detaied impementation based on ECL ogic is described, and the hardware to be used on an ECL cabe segment for an experimenta FASTBUS system at SLAC is shown. I. Introduction FASTBUS is a proposed standard data bus for moduar, high-speed data acquisition and contro systems. It has been deveoped by the Fast System Design Group of the U.S. NIM Cormnittee with participation from the European ESONE Committee. FASTBUS systems can be configured from mutipe bus segments. These segments are abe to operate independenty or ink together seectivey for exchange of data. Two or more crate segments may be connected by means of a cabe segment. The impementation of segments and execution of some operations require circuitry which is common to a devices residing on such segments. This is referred to as Anciary Logic and contains hardware for arbitration timing contro, geographica addressing, system handshake generation for broadcast cyces, run-hat contro, and signa ine terminations for the segment bus. The requirements for Anciary Logic contained in the FASTBUS Specifications wi be reviewed and discussed in detai. An ECL design for a standard crate segment Anciary Logic unit has been deveoped. Design detais wi be shown to iustrate impementation of the FASTBUS specifications. A prototype Anciary Logic Modue for a differentia ECL cabe segment has been buit. This hardware wi be used as part of an experimenta FASTBUS data acquisition and contro system for one of the partice detectors at SLAC. The presentation in this paper assumes basic famiiarity with the FB Specification. II. Basic Anciary Logic Requirements This discussion of Anciary Logic (ANC) requirements is basedion Section 7 of the FASTBIJS (FB) Tentative Specification. Two bock diagrams and two tabes of definitions and ogic equations are presented to iustrate these requirements. The diagrams are not based on any particuar hardware reaization. Hence inputs to fip-fops, registers, atches, and timers assume ony ogic eve sensitivity; for fip-fops S-R=1 inputs cause no change, CLR input overrides S and R; an enabed timer asserts its output at the end of its time interva; the timer is reset and initiaized by the CLR input. A. Arbitration Timing Contro Section The ATC section is shown in Fig. 1 and Tabe'. This contains ogic functions for ATC, Arbitration Inhibit (AI), System Handshake (SHL), and Run-Hat (RH) Contro. Run-Hat Logic monitors the manua RH switch of the segment. A hat request from the switch inhibits new arbitration cyces. Upon competion of an arbitration cyce in progress and reease of the bus by the current master, the Bus Hated (BH) and AK ines are asserted. * Work supported by the Department of Energy, contract DE-AC03-76SF BAR BPS* BDS BMSO BWT EAR EGK 845 BAK BWT +LPJ LJ SYSTEM HANDSHAKE Fig. 1. ATC section basic bock diagram. ATC LOGIC Tabe 1. ATC section definitions and ogic equations. Definitions htak - Bus Ceanup Time after AK(d) TM1 - Arbitration Timer for AG= (EZ) TM2 - GK(u) Timeout (GKTO) TM3,4 - Bus Deay Timers ATA - Broadcast Address Response Deay ATD - Broadcast Data Response Deay HRQ - Hat Request MSP - Mastership Pending EZ - Enabe AL Sum PWR CLR - Power-on Cear Nwr - No Wait Asserted ES- - Enabe System Handshake SET BH SET AG RES AG CLR AG CLR MSP CLR AI SET DK RES DK - IAK2 LOGIC HRQ.(MSP + IAG + BGK + BAS + BWI + OAK)* BAR.HRQ*. BGK". BWI* * MSP" BAS" &UC*. BGK". BUT".MSP EE.ZAL* + PWR CLR + IBRB*BBH* GKTO + PWR CLR + /BRB*BBH* PWR ~LR + /BRB.BBH* Optiona Fast Reset (Presented at the Nucear Science Symposium, Washington, D.C., October 20-22, 1982.)

2 ATC Logic contros the timing of arbitration cyces, Two fip-fops and two timers reguate the execution of an arbitration cyce. Pending arbitration requests set the AG fip-fop when GK(d) is received from the current master. This starts the arbitration cyce and enabes timer TM. Participating masters assert their arbitration eve on the bus for priority resoution. When TM1 signas competion of the arbitration time (EL), the A ines are tested. If arbitration eve zero (ZAL=O an error condition) is found, AG is ceared. Otherwise the arbitration vector corresponds to the winning (highest priority) master and the Mastership Pending (MSP) fag is set. Now the arbitration cyce wi wait for the current master to reease the bus by terminating its AS-AK ock. After AK(d) is received and the bus has setted (ATAK deay), the ATC resets AG. This signas the prending master to assert GK and take bus mastership. The ATC enabes timer TM2. Receipt of GK(u) from the pending master resets the MSP fag and thereby re-enabes the SET AG gate. Aternatey if no GK response is received in time, timer TM2 wi compete the arbitration cyce by cearing the MSP fag. The Arbitration Inhibit fip-fop asserts AI with AG(u) at the start of an arbitration cyce. This inhibits issuance of new AR requests by masters obeying the assured access protoco. Now AI remains set unti a pending AR requests have been serviced, thus assuring bus mastership to ow priority masters independent of the rate of requests from high priority masters. Timer TM3 requires AR=0 for at east two bus deays before resetting AI and enabing a new set of arbitra- tion requests. System Handshake Logic for broadcast operations is shown at the bottom of Fig. 1. For broadcast cyces, handshake responses are generated by the SHL on behaf of a save modues residing on a segment. Hence a transitions 6f AK and DK are deayed by ATA and ATD respectivey to aow the sowest saves to participate successfuy in the broadcast. Propagation of address cyces [AS(u) and AK(u)1 and data cyces CDS(u) and DK(u), and for bock transfers DS(d) and DK(d) from the broadcast master through a addressed segments to the end of each broadcast branch is controed by WAIT generated by segment interconnect (SI) modues and the NWT timer TM4 in each SHL. With this mechanism AS(u) and DS(t) wi propagate to the end of a branch with WT= asserted by each SI aong the path. On the ast segment no WT is seen and the SHL generates AK(u) or DK(t) as appropriate. Now SIs on this ast segment cear WI and the SHL on the next segment back toward master asserts acknowedge responses after its NWT timer TM4 has eapsed. In this fashion AK(u) and DK(t) are returned back to master. The use of WT* in the ogic for AK and DK generation impements genera WAIT rues. The optiona fast reset shown in the RES DK equation is not mandatory. This resets DK immediatey without NWT for non-bock transfer cyces. B. Geographica Address Contro Section The GAC requirements are shown in Fig. 2 and Tabe 2. GAC consists of an EG generator and a simpe FB save with two CSR registers. The EG generator detects geographica addresses. The address decoding ogic (EGA) recognizes two formats for geographica addresses and rejects address 255 (FF hex) reserved for the GAC save device. For a vaid geographica address operation EG is set after an address decoding deay ATAS, seected by the designer to satisfy the decoding time requirements of a particuar impementation and to meet the specification for maximum EG deay after AS(u). The GAC save device recognizes reserved geographica address 255 (ALA) in CSR space. The save contains two CSR registers which are addressed by a 2-bit NTA register. The NTA register is accessabe (RDNTA, LDNTA) via secondary address cyces. The CSR#O register is BWT* RDNTA SETSEL - EAS+ RDCSRO -1 FF >R SELECT FF SEL -+ LDNTA RDNTA n I I/I ID Number CSR E x0. 0 REG IAD ~ 16 (ease GP) (3t:t6) I I I E Buffer Buffer E t- \I IAD 24 IAD(3!: 8) 26 I-E I:,... ;.IAD Fig. 2. GAC section basic bock diagram. Tabe 2. GAC section definitions and ogic equations. Definition ATAS - ATDS - ATDK - ALA - EGA - PWR CLR - s SET SEL = SET EG = RES EG = ALA = EGA = ISS<Z:> = RDCSR!?i = RDCSR3 = LDCSR3 = RESCSR3 = LDNTA = RDNTA = Address Decoding Deay Data Decoding Deay Data Response Deay Anciary Logic Address Enabe Geographica Address Power-On Cear ALA. (BMS=I) BAK* * ABAS EGA.ABAS.(BMS=0+1)* CBEG+BAK+PWR CLR+/BRB*BBH*I* BAS*+BAK+PWR CLR+/BRB.BBH* CBAD<31:0>=HEX(GP0...0FF FF)I CBAD<7:0 >=HEX(FF)** [BAD<31:8>=HEX.(GP ) (IBAD<31:2>=1+BAD0$1)*(LMS=2)*LRDX*DS1 + (LMS=O+2)*.DS + (LMS=O)*C(NTA=1+2) + (NTA=~)~LRD*I~DS~ (m=0). (NTA=O). LRD ix1 (LMS=0). (NTA=3) LRD. DS (LMS=0). (NTA=3) LRD*. DS * BDK" PWR CLR+JBRB*BBH* (LMS=2) LRD" DS BDK* (LMS=2) LRD *DS LT IAK -2-

3 Tabe 3. Anciary ogic timing specifications. Item Description Time Cns 19" Crate 15 m Cabe Segment Segment ATC Section ATAK Bus Cean-up Time after AK(d)--Minimum Puse Down Time MIN TM1 Arbitration Timer for AG= MIN TM2 GK(u) Timeout --Master Address Timeout MIN 650 a30 TM3 Bus Deay Timer for AR=O-- 2 xbus Deay MIN TM4 Bus Deay Timer for WT=O--2 xbus Deay MIN ATA Broadcast Address Response Deay for AK(t) MIN W5,6) MAX ATD Broadcast Data Response Deay for DK(t) MIN ( JX,8) MAX GAC Section ATAS Save Address Decoding Deay--EG Deay i- ATDS Save Data Decoding Deay ATDS+ATDK 5;- ATDK Save Data Response Deay for DK(t) Both Sections IRB Reset Bus Integration for RB(u) MIN MAX PWR CLR Power-On Cear--Design Choice * Aow for Circuit Propagation Deays. read-ony and contains the mandatory 16-bit ID number. The CSR#3 register is 24-bit read-write and stores the segment base address (GP) used for geographica addressing. Save status response SS=6 is generated for error conditions. For secondary address write cyces a invaid NTA vaues are rejected. Ony codes MS=&!+2 for random data and secondary address cyces are accepted. Finay write cyces to CSR#O are rejected. An optiona input register is shown to sampe the MS and RD ines at DS(u) time. C. Anciary Logic Timing Specifications The timing specifications for ANC Logic are summarized in Tabe 3. This tabe is based on Tabe A.1.2 of the FB Specifications. Vaues are given for ANC Logic utiizing ECL for a 19" crate segment bus and a 15 m cabe segment bus. III, Crate Segment Impementation A design for a standard crate segment ANC Logic has been deveoped. The impementation is based on IOK ECL integrated circuits and is packaged on two rear-mounted printed circuit boards. The ATC Board contains the ogic described in Section II.A, Fig. 1 and Tabe 1 above. Impementation detais are simiar to the design bock diagram shown for the cabe segment in Fig. 4. The board aso contains bus drivers, receivers and terminating resistors for the crate segment backpane. The board design utiizes approximatey sixteen I.C. packages. The GAC Board is shown in Fig. 3. The design satisfies a ogic requirements discussed in Section II.B, Fig. 2 and Tabe 2. The hardware accommodates a 12-bit GP segment base address. Approximatey thirty 10K ECL I.C. packages are utiized IV. Cabe Segment Impementation A design for a Cabe Segment Anciary Logic has been deveoped and buit at SLAC to be used in a Liquid Argon Contro System on the Mark II detector. The proposed system incudes a VAX-FASTBUS interface, a microcontroer modue, anaog mutipexer modues, tiac output modues, one segment interconnect unit, a cabe segment (15 meters), a cabe segment anciary ogic modue and terminators. The VAX-FASTBUS interface and the microcontroer modue are described in two papers at this Symposium.4r5 WT PI%-19 Fig. 3. Crate GAC board design bock diagram.

4 The impementation of the Cabe Segment Anciary Logic uses 10K ECL ogic, differentia ine drivers and receivers and active terminators for the Cabe Segment connected through the Auxiiary Connector. The hardware is packaged in a 'singe width FB modue. This modue impements a the standard features described before with the exception of the ine MS2 (not used). A timing vaues are for a 15 m cabe. The ID of this modue is [ hex] and the CSR Register 3 is 8-bit wide. In Figs. 4 and 5 a summations (E) and products (II) are done at the receiver outputs (wired OR/AND). Figure 6 shows a typica active terminator circuit with 100 R impedance for the differentia signa ines of the Cabe Segment. Each differentia ine requires one termination circuit at each end of the cabe. Ony one modue is expected to assert a ine at any given time (except for AR, WT, and SR ines). Hence a unit current vaue of 8 ma wi be switched at the termination resistors (56 Q) at each end of the cabe (16 ma tota for the driver circuit). This yieds a differentia votage signa of 0.8 V at the receiver inputs. In order to aow a variabe number of modues to be connected to the Cabe Segment, the stacking of unit current vaues has to be compensated. This is achieved by means of an operationa ampifier controing a current source. Hence the current through the termination resistor is maintained at 8 ma. Finay the termination votage VTER~+ is common to a ines and is adjusted to set the quiescent votage eves for the differentia ines in reference to VREF seected as VBB. V. Summary and Acknowedgements Detais in this paper are based on the June 1982 FASTBUS Tentative Specifications. A appicabe changes made in this document by the FB Working Groups through October 1982 have been incuded. However the fina U.S. Department of Energy document of the FASTBUS Specifications may incude additiona minor changes affecting FB ANC Logic. The Crate ANC Logic design shown in Section III is presenty in PC ayout.2 Prototypes of the ATC and GAC boards are expected by the end of December The Cabe ANC Logic modue shown in Section IV has been fabricated as a wirewrap prototype and is present! being tested.3 CABLE SEGMENT GAC LOGIC BDS > :DK ZBADi L J TIPICAL TMERCRCUT (TM,./..I, Fig. 4. Cabe ATC section design bock diagram. EBAD(24-31) TBAD( 8-231> D i +ei Oi connaction J?.(. Fig. 5. Cabe GAC section design bock diagram.

5 -1 r F.8. / AUX CONN. L -/.I v [-.ZW] s 56 IOK pa34o3 1-8.(n-)mA -1.3v IOK MPQ 3904 TYPICAL CABLE SEGMENT TERMINATORS [ J Common 10 rhe other CKTs xX > ~F;fq~;.-P TYPICAL CABLE SEGMENT LINE DRIVERS/RECEIVERS.. a Fig. 6. Typica ECL differentia terminators and ine interface. The Anciary Logic requirements and Differentia Cabe Segment detais presented in this paper are based on earier contributions by a number of peope on the FASTBUS committee, incuding R. Downing (University of Iinois), L. Paffrath (SLAC), L. Pregernig (CERN), E. J. Barsotti (FNAL), and W. K. Damon (TRIUMF). Continued support of this work by R. S. Larsen is gratefuy appreciated.- References "FASTBUS Tentative Specification," U.S. NIM Committee, avaiabe from L. Costre, NBS, Washington, D.C. FASTBUS Crate Anciary Logic Documentation, ATC Board SLAC , and GAC Board SLAC FASTBUS Cabe Anciary Logic Documentation, SLAC FASTBUS Host Interface for VAK/VMS, E. J. Siskind, Brookhaven Nationa Laboratory; paper contributed to the IEEE Nucear Science Symposium, Washington, D.C., October A FASTBUS Controer Modue Using a Mutibus MPU, S. R. Deiss, Stanford Linear Acceerator Center; paper contributed to the IEEE Nucear Science Symposium, Washington, D.C., October Fig. 7. Prototype cabe anciary ogic modue. -5-